CN109684722A - It is a kind of for prevent chip system power up leak electricity design circuit - Google Patents
It is a kind of for prevent chip system power up leak electricity design circuit Download PDFInfo
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- CN109684722A CN109684722A CN201811583951.0A CN201811583951A CN109684722A CN 109684722 A CN109684722 A CN 109684722A CN 201811583951 A CN201811583951 A CN 201811583951A CN 109684722 A CN109684722 A CN 109684722A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
Abstract
It is a kind of for prevent chip system power up leak electricity circuit, wherein, chip system includes Power Management Unit and functional unit, Power Management Unit includes bandgap voltage reference module, the first output LDO module and provides the second output LDO module of DVDD, and the first output LDO module and the second output LDO module include the first level conversion submodule；The outside of chip system only provides a chip enable signal EN_LDO, analog power end AVDD, digital power end DVDD and ground terminal AVSS；Functional unit includes a simulation top layer reverser module and multiple function sub-modules；Each of multiple function sub-modules include that second electrical level transform subblock and second signal are forced shutdown device；Wherein, before chip enable signal EN_LDO arrival, simulate the reverse signal that top layer reverser module utilizes DVDD, it goes to control each second signal and is forced shutdown device, so that the modules in multiple functional modules are before DVDD is powered on, the output current potential of second electrical level transform subblock is all 0, that is, ensures that the enable signal of each in multiple functional modules is low.
Description
Technical field
The present invention relates to CMOS analogue layout fields more particularly to power management direction to examine with system electrification
Consider, and in particular to a kind of for the design scheme for preventing chip system power up from leaking electricity.
Background technique
With the development of CMOS integrated circuit technology, the integrated level of electronic product is higher and higher.It is traditional by external power supply
Directly to chip power supply mode often since the factors such as unstable not can guarantee the normal work of chip, meanwhile, in order to improve
Application, many chips have carried complete power management module.
The electronic product big for one often has the chip of many different function simultaneously or does not work simultaneously,
It is generally necessary to go to control its function by configurable, reusable bus interface, and the mutual transmission of data is carried out, that is, forms one
The relationship of a MS master-slave (master-slave).
Master controller usually only sends individual signals and goes to control the unlatching from device, and chip only passes through reception one and starts to refer to
Show signal (enable signal) it is necessary to go to complete the function of entire chip, wherein power management module plays highly important
Role.
Due to having differences between the supply voltage between simulation, number and interface, the power supply of modules is by respectively
Need certain driving capability.Therefore, level conversion is also a key problem in technology.In general, analog power voltage is externally supplied,
And interface and the supply voltage of number then pass through low pressure difference linear voltage regulator (LDO) generation.
However, the difference of difference and power-on time between each supply voltage, resulting in chip disparate modules may
There can be certain electric leakage, this is unacceptable for product.Therefore, at the beginning of chip design, especially power supply pipe
Module is managed, should just consider that power up prevents the design of electric leakage.
Summary of the invention
In order to achieve the above object, single for external trigger control signal, and the chip of analog power excitation is only provided
Design considers that The present invention gives a feasible effective design methods for electric leakage is powered on.Specifically, technology of the invention
Scheme is as follows:
It is a kind of for prevent chip system power up leak electricity circuit, the chip system include Power Management Unit and
Functional unit, the Power Management Unit include bandgap voltage reference module, the first output LDO module and provide the of DVDD
Two output LDO modules, the first output LDO module and the second output LDO module include the first level conversion submodule；Institute
State chip system outside only provide a chip enable signal EN_LDO, analog power end AVDD, digital power end DVDD and
Ground terminal AVSS；Wherein, the functional unit includes a simulation top layer reverser module and multiple functional modules；It is the multiple
Each of functional module includes that second electrical level transform subblock and second signal are forced shutdown device, wherein when the core
Before piece enable signal EN_LDO arrives, the simulation top layer reverser module utilizes the reverse signal of DVDD, goes to control each institute
It states second signal and is forced shutdown device, so that the modules in the multiple functional module, before DVDD is powered on, described second is electric
The output current potential of flat transform subblock is all 0, that is, ensures that the enable signal of each in the multiple functional module is low.
Further, the second electrical level transform subblock includes cross-coupled circuit；The signal is forced shutdown device packet
Include the 2nd COMS transistor；The source electrode of the 2nd COMS transistor meets ground terminal AVSS, and grid connects the end ANA-PD, and drain electrode connects friendship
Pitch the output end of coupling circuit.
Further, it further includes the first COMS transistor that the signal, which is forced shutdown device,；The first COMS transistor
Source electrode meets analog power end AVDD, and grid connects the end ANA-PD, and drain electrode connects the source of the cross-coupled circuit.
Further, the simulation top layer reverser module includes phase inverter and sluggish submodule, the sluggishness submodule
The phase inverter is set to increase the lagging characteristics for preventing the second output LDO module output jitter for providing DVDD.
Further, the simulation top layer reverser module is including further including antistatic submodule, the antistatic submodule
The leakage of the input terminal and the COMS transistor M0 of DVDD is serially connected in including resistance R0 and COMS transistor M0, the resistance R0
Pole；The grid and source electrode of the COMS transistor M0 meets the ground terminal AVSS.
Further, the Power Management Unit further include voltage-stablizer reverser module, it is described first output LDO module with
And the second output LDO module of the offer DVDD, the second output of the first output LDO module and the offer DVDD
LDO module includes that the first level conversion submodule and the first signal are forced shutdown device；As the chip enable signal EN_LDO
Before arrival, the voltage-stablizer reverser module utilizes the reverse signal of EN_LDO, goes to control each first signal pressure pass
Disconnected device, so that described first exports LDO module and the second output LDO module for providing DVDD before EN_LDO is powered on,
The output current potential of the first level conversion submodule is all 0, that is, ensures that the second output LDO module for providing DVDD exists
The enable signal of EN_LDO is all low.
Further, the first level conversion submodule includes cross-coupled circuit；2nd COMS transistor；Described
The source electrode of two COMS transistors meets ground terminal AVSS, and grid connects the end ANA-PD, and drain electrode connects the output end of cross-coupled circuit.
Further, it further includes the first COMS transistor that first signal, which is forced shutdown device,；The first COMS crystal
The source electrode of pipe meets analog power end AVDD, and grid connects the end ANA-PD, and drain electrode connects the source of cross-coupled circuit.
Further, it further includes the drain electrode access one in the 2nd COMS transistor that first signal, which is forced shutdown device,
A capacitor to ground.
A kind of solution there is electric leakage for chip system power up provided by the present invention, it is ensured that in core
Before the DVDD of piece system arrives, electric leakage is not generated.It is more comprising level conversion (level shift) especially for having the function of
The circuit of module, for example, row decoding array etc. in imaging sensor, at this time not with greater need for the work of guarantee level conversion functional module
There can be electric leakage, otherwise, it will carry out bigger leakage current to entire chip belt, and then influences total system work, specifically,
The advantage is that:
1., in the case where chip exterior controls signal and the limited mode of power supply excitation, having carried out may before chip life's work
The case where leaking electricity considers, improves the reliability of system；
2., level conversion in chip disparate modules (level shift) function module circuit is optimized, is prevented
It causes to leak electricity in electric process；
3., directly using chip operation enable signal control power management module level conversion (level shift) function
Energy modular circuit does not increase additional resources of chip consumption；
4., chip top-layer by the reverse signal of DVDD go control modules in level conversion (level shift) function
Modular circuit reduces the complexity of circuit design.
Detailed description of the invention
Its example embodiment is described in detail by referring to accompanying drawing, above and other feature of the invention and advantage will become
It is more obvious.
Fig. 1 show the present invention for the signal of the circuit arrangement for preventing chip system power up from leaking electricity and corresponding timing
Figure
Fig. 2 show the present invention and is applied to each function of chip for the circuit arrangement for preventing chip system power up from leaking electricity
Level switch module circuit diagram in energy module
Fig. 3 show the present invention for the simulation top layer reverser module prevented in chip system power up leakage circuit
Physical circuit schematic diagram
Fig. 4 show the first level conversion submodule in the first output LDO module of the present invention and the second output LDO module
Circuit simulation figure
Specific embodiment
1 and Fig. 4 with reference to the accompanying drawing, specific embodiments of the present invention will be described in further detail.It should be noted
Be that attached drawing is all made of very simplified form, using non-accurate ratio, and only to it is convenient, clearly reach aid illustration
The purpose of the present embodiment.
It should be noted that the present invention, which is directed to the circuit for preventing chip system power up from leaking electricity, is suitable for corresponding chip system
System, the chip system generally include Power Management Unit and functional unit.Power Management Unit include bandgap voltage reference module,
Second output LDO module of the first output LDO module and offer DVDD, the first output LDO module and the second output LDO module
It include the first level conversion submodule；Wherein, the first output LDO module is that the 1.8V for powering to IO exports LDO module,
And providing the second output LDO module of DVDD is output module of the 1.2V for digital power system.First output LDO module provides
The VDD_IO of 1.8V, that is, the supply voltage of interface circuit.AVDD is the analog power voltage of entire chip, is higher than 1.8V；
Chip operation analog power voltage typically 2.6~3.6V.The outside of chip system only provides a chip enable signal
EN_LDO, analog power end AVDD and ground terminal AVSS.
Referring to Fig. 1, Fig. 1 show the present invention for the circuit arrangement and correspondence for preventing chip system power up from leaking electricity
The schematic diagram of timing.Chip piece will start to work normally it may first have to which guarantee powers on normally, so it is defeated to first have to control first
LDO module and the second output LDO module are started to work out, remaining module then according to register electrification reset after, start normal
Work, so that the chip completes the function of itself.Therefore, the signal obtained from master controller only one, i.e., LDO is opened
Beginning work indication signal (EN_LDO signal).
It will be apparent to those skilled in the art that in general, after analog power voltage (AVDD) powers on, EN_LDO signal is not
Before transmission, namely number and interface circuit are not all started to work.Need to guarantee that module all in chip is off shape at this time
Otherwise state has electric leakage.
The present invention has carried out different processing with remaining functional module for the power management module in chip, and is added to
One simulation top layer inverter modules and pressure stabilizing reverser module.
For power management module, default register is all set to 0 under normal circumstances, this is because digital power is not
Before powering on, register value can not be all written, and output is entirely 0.However, need to be skipped since LDO at this time needs to be first begin to work
The work default register value of first output LDO module and the second output LDO module is all set to by the write-in of register value
0.But register write-in needs to control by digital module, before digital power (DVDD) does not power on, traditional level conversion (level
Shift) two numeral inputs of circuit not can guarantee, and therefore, it is required 0 that the output valve of level shift, which not can guarantee,
Level.In an embodiment of the present invention, the first level conversion submodule is optimized, is carried out reversely using EN_LDO signal,
The first level conversion submodule of control is removed, makes it before digital power arrival, output is ensured of 0, to ensure that LDO's is normal
Work.
Specifically, in an embodiment of the present invention, Power Management Unit further includes voltage-stablizer reverser module, when chip makes
Before energy signal EN_LDO arrives, voltage-stablizer reverser module utilizes the reverse signal of EN_LDO, goes to control each first level turn
Submodule is changed, so that first exports LDO module and the second output LDO module for providing DVDD before EN_LDO is powered on,
The output current potential of first level conversion submodule is all 0, that is, ensures the second output LDO module for providing DVDD in EN_LDO
Enable signal be all low.
Further, in an embodiment of the present invention, functional unit is also improved, makes which increase a moulds
Quasi- top layer reverser module, the DVDD inversion signal ANA_PD of simulation top layer reverser module output, goes to control multiple functions
The second electrical level transform subblock and signal that each of module includes are forced shutdown device.Wherein, when chip enable signal
Before EN_LDO arrives, simulation top layer reverser module utilizes the reverse signal of DVDD, goes to control each second electrical level conversion submodule
Block, so that the modules in multiple functional modules, before DVDD is powered on, the output current potential of second electrical level transform subblock is all
0, that is, ensure that the enable signal of each in multiple functional modules is low.
Specifically, referring to Fig. 2, Fig. 2 show the present invention for the circuit side for preventing chip system power up from leaking electricity
Case is applied to the level switch module circuit diagram in each functional module of chip.
In an embodiment of the present invention, which may include a simulation top layer reverser module and multiple functions
Module；Each of multiple functional modules include that second electrical level transform subblock and signal are forced shutdown device, wherein work as core
Before piece enable signal EN_LDO arrives, simulation top layer reverser module utilizes the reverse signal of DVDD, goes to control each second electricity
Flat transform subblock so that the modules in multiple functional modules are before DVDD is powered on, second electrical level transform subblock it is defeated
Current potential is all 0 out, that is, ensures that the enable signal of each in the multiple functional module is low.
It includes the first COMS transistor (being indicated in figure with M10) and the 2nd COMS transistor (in figure that signal, which is forced shutdown device,
It is indicated with M9)；First COMS transistor series connection between analog power end AVDD and the input terminal of second electrical level transform subblock,
2nd COMS transistor is attempted by between the output and ground AVSS of second electrical level transform subblock.As shown in Fig. 2, first
The source electrode of COMS transistor meets analog power end AVDD, and grid connects the end ANA-PD, and drain electrode connects the defeated of second electrical level transform subblock
Enter end；The source electrode of 2nd COMS transistor meets ground terminal AVSS, and grid connects the end ANA-PD, and drain electrode connects second electrical level transform subblock
Output end.In the present embodiment, second electrical level transform subblock includes cross-coupled circuit.
In an embodiment of the present invention, relatively traditional level shifting circuit increases M9 and M10 pipe, by PD signal
Control.Traditional level shifting circuit, due to when DVDD is not powered on, input signal VIN after phase inverter, signal VID and
VIB voltage is uncertain, such as the VIND signal in Fig. 4 analogous diagram；Usual VID and VIB signal all very littles, close ground potential,
When VID and VIB signal go control analog portion when, it will so that simulation branch medium voltage x point or y point be in one between
Current potential between analog power and ground, cause analog power to ground a current path, to cause to leak electricity.
The effect of M10 transistor is to have blocked leakage current paths, in PD signal connection simulation top layer reverser module
DVDD inversion signal ANA_PD, when DVDD is low, ANA_PD is height so that two branches in cross-coupled circuit with
Separate between power supply, even if x y point is in intermediate potential, the access of electric current will not be generated.
The effect of M9 transistor is to force drawing to be arrived y point signal low then before DVDD arrival, so that second electrical level conversion
Module output is low.So that the enable signal of each module be it is low, do not work, also just there is no electric leakage.When DVDD is powered on
It completes namely ANA_PD sets the closing of 0, M9 pipe, the output of second electrical level transform subblock is then determined according to input, restores normal
Level conversion function.
It should be noted that the second electrical level transform subblock of multiple functional modules uses the inversion signal of DVDD in chip
Control, since the voltage of DVDD is usually 1.2V, the turn threshold of simulation top layer reverser module needs to be arranged to lower
Value.In an embodiment of the present invention, the normal value of analog power is 2.8V, 2.6~3.6V of range, keeps the simulation top layer reversed
Device module needs to guarantee enough pull-down capabilities, so that phase inverter can work normally.
Referring to Fig. 3, Fig. 3 show the present invention for the simulation top layer prevented in chip system power up leakage circuit
Reverser module physical circuit schematic diagram.As shown, the simulation top layer reverser module of M1~M6 transistor composition increases
Sluggish submodule, the sluggishness submodule make phase inverter increase the second output LDO module output jitter for preventing from providing DVDD
Lagging characteristics prevent the shake of DVDD power supply, ensure that the stabilizer of simulation top layer reverser functions of modules.
In addition, it further includes antistatic submodule that simulation top layer reverser module, which includes, which includes resistance
R0 and COMS transistor M0, the effect of resistance R0 and OMS transistor M0 are then ESD in order to prevent.The resistance R0 is serially connected in
The drain electrode of the input terminal and COMS transistor M0 of DVDD；The grid and source electrode of COMS transistor M0 meets ground terminal AVSS.
In an embodiment of the present invention, the first level conversion submodule in power management module then utilizes that EN_LDO's is anti-
Phase signals are controlled.The level conversion of relatively other functional modules has done closer one-step optimization.EN_LDO opens complete to DVDD
This section of process is powered on entirely, and the inversion signal of EN_LDO has been low, namely is released to the M9 in the first level conversion submodule
The control of pipe.But at this time in order to guarantee the first output LDO module and second output LDO module in the first level conversion submodule it is defeated
0 is remained as out, selects to access a capacitor to ground in y point, to maintain low level, prevents passing through for other skip signals from posting
Raw capacitor interferes its bring.
In general, in an embodiment of the present invention, the inversion signal of EN_LDO then passes through simple phase inverter and generates.Due to master
The EN_LDO signal level that controller issues is 1.8V, and analog power range is 2.6~3.6, therefore, first order phase inverter
Turn threshold also will be arranged lower, can just guarantee the normal work of phase inverter.
Referring to Fig. 4, Fig. 4 show the first level in the first output LDO module of the present invention and the second output LDO module
Transform subblock circuit simulation figure.As shown, 7 curves are AVDD signal curve, EN_LDO letter respectively from top to bottom in figure
The PD signature tune at the first end level conversion submodule PD in number curve, the first output LDO module of control and the second output LDO module
Line, the input signal VINB and VIND signal curve after level-one, two-stage digital phase inverter respectively, digital power DVDD signal
Curve, second electrical level transform subblock y point signal (net48 in figure), level-one level shift final output signal curve.
As stated above, present invention is mainly applied to the self-powered management module in System on Chip/SoC, the power management modules
Main to provide the power supply of interface circuit comprising a linear voltage regulator, a linear voltage regulator provides digital power, and outside only mentions
The case where for a triggering open signal and analog power, earth signal.Present invention utilizes a top layer inverter modules,
And by improving drain conditions of the level shifting circuit in each sub-function module come anti-locking system before normal work.It mentions
High reliability of chip during system electrification.
Above-described to be merely a preferred embodiment of the present invention, the patent that the embodiment is not intended to limit the invention is protected
Range is protected, therefore all with the variation of equivalent structure made by explanation and accompanying drawing content of the invention, similarly should be included in this
In the protection scope of invention.
Claims (9)
1. a kind of for the circuit for preventing chip system power up from leaking electricity, the chip system includes Power Management Unit and function
Energy unit, the Power Management Unit include the second of bandgap voltage reference module, the first output LDO module and offer DVDD
LDO module is exported, the first output LDO module and the second output LDO module include the first level conversion submodule；It is described
The outside of chip system only provides a chip enable signal EN_LDO, analog power end AVDD, digital power end DVDD and connects
Ground terminal AVSS；It is characterized in that, the functional unit includes a simulation top layer reverser module and multiple functional modules；It is described
Each of multiple functional modules include that second electrical level transform subblock and second signal are forced shutdown device, wherein work as institute
Before stating chip enable signal EN_LDO arrival, the simulation top layer reverser module utilizes the reverse signal of DVDD, goes control each
A second signal is forced shutdown device, so that the modules in the multiple functional module are before DVDD is powered on, described
The output current potential of two level conversion submodules is all 0, that is, ensures that the enable signal of each in the multiple functional module is
It is low.
2. according to claim 1 for the circuit for preventing chip system power up from leaking electricity, which is characterized in that described the
Two level conversion submodules include cross-coupled circuit；It includes the 2nd COMS transistor that the signal, which is forced shutdown device,；Described
The source electrode of two COMS transistors meets ground terminal AVSS, and grid connects the end ANA-PD, and drain electrode connects the output end of cross-coupled circuit.
3. according to claim 2 for the circuit for preventing chip system power up from leaking electricity, which is characterized in that the letter
Number being forced shutdown device further includes the first COMS transistor；The source electrode of the first COMS transistor connects analog power end AVDD, grid
Pole connects the end ANA-PD, and drain electrode connects the source of the cross-coupled circuit.
4. according to claim 2 for the circuit for preventing chip system power up from leaking electricity, which is characterized in that the mould
Quasi- top layer reverser module includes phase inverter and sluggish submodule, and the sluggishness submodule, which increases the phase inverter, prevents institute
It states and the lagging characteristics of the second output LDO module output jitter of DVDD is provided.
5. according to claim 4 for the circuit for preventing chip system power up from leaking electricity, which is characterized in that the mould
For quasi- top layer reverser module including further including antistatic submodule, which includes resistance R0 and COMS transistor
M0, the resistance R0 are serially connected in the drain electrode of the input terminal and the COMS transistor M0 of DVDD；The grid of the COMS transistor M0
Pole and source electrode meet the ground terminal AVSS.
6. -5 is any one of for the circuit for preventing chip system power up from leaking electricity, feature according to claim 1
It is, the Power Management Unit further includes voltage-stablizer reverser module, the first output LDO module and the offer DVDD
Second output LDO module, the first output LDO module and the second output LDO module for providing DVDD include the
One level conversion submodule and the first signal are forced shutdown device；Before chip enable signal EN_LDO arrival, the pressure stabilizing
Device reverser module utilizes the reverse signal of EN_LDO, goes to control each first signal and is forced shutdown device, so that described the
One output LDO module and the second output LDO module for providing DVDD are before EN_LDO is powered on, first level conversion
The output current potential of submodule is all 0, that is, ensure it is described provide DVDD second output LDO module EN_LDO enable signal all
It is low.
7. being directed to the circuit for preventing chip system power up from leaking electricity described according to claim 6, which is characterized in that
The first level conversion submodule includes cross-coupled circuit；2nd COMS transistor；The source of the 2nd COMS transistor
Pole meets ground terminal AVSS, and grid connects the end ANA-PD, and drain electrode connects the output end of cross-coupled circuit.
8. according to claim 7 for the circuit for preventing chip system power up from leaking electricity, which is characterized in that described the
It further includes the first COMS transistor that one signal, which is forced shutdown device,；The source electrode of the first COMS transistor connects analog power end
AVDD, grid connect the end ANA-PD, and drain electrode connects the source of cross-coupled circuit.
9. according to claim 8 for the circuit for preventing chip system power up from leaking electricity, which is characterized in that described the
It further includes drain electrode access one capacitor to ground in the 2nd COMS transistor that one signal, which is forced shutdown device,.
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| CN201811583951.0A CN109684722B (en) | 2018-12-24 | 2018-12-24 | Design circuit for preventing electric leakage in power-on process of chip system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811583951.0A CN109684722B (en) | 2018-12-24 | 2018-12-24 | Design circuit for preventing electric leakage in power-on process of chip system |
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| CN109684722B CN109684722B (en) | 2022-12-27 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113448413A (en) * | 2021-08-30 | 2021-09-28 | 辰芯科技有限公司 | Power-on reset device, power-on reset method, computer device and readable storage medium |
| CN116366051A (en) * | 2023-03-21 | 2023-06-30 | 辰芯半导体（深圳）有限公司 | Level shift circuit and level shifter |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101951175A (en) * | 2010-08-17 | 2011-01-19 | 深圳市核达中远通电源技术有限公司 | Flyback synchronous rectification control circuit |
| US9257973B1 (en) * | 2014-11-04 | 2016-02-09 | Texas Instruments Incorporated | Supply-state-enabled level shifter interface circuit and method |
-
2018
- 2018-12-24 CN CN201811583951.0A patent/CN109684722B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101951175A (en) * | 2010-08-17 | 2011-01-19 | 深圳市核达中远通电源技术有限公司 | Flyback synchronous rectification control circuit |
| US9257973B1 (en) * | 2014-11-04 | 2016-02-09 | Texas Instruments Incorporated | Supply-state-enabled level shifter interface circuit and method |
Non-Patent Citations (1)
| Title |
|---|
| 杨紫薇等: "一种针对低功耗MCU关断模式的功耗优化方法", 《微电子学与计算机》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113448413A (en) * | 2021-08-30 | 2021-09-28 | 辰芯科技有限公司 | Power-on reset device, power-on reset method, computer device and readable storage medium |
| CN113448413B (en) * | 2021-08-30 | 2021-11-30 | 辰芯科技有限公司 | Power-on reset device, power-on reset method, computer device and readable storage medium |
| CN116366051A (en) * | 2023-03-21 | 2023-06-30 | 辰芯半导体（深圳）有限公司 | Level shift circuit and level shifter |
| CN116366051B (en) * | 2023-03-21 | 2024-02-13 | 辰芯半导体（深圳）有限公司 | Level shift circuit and level shifter |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109684722B (en) | 2022-12-27 |
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