CN103885563A - Management circuit for self-powered microprocessor protection device microprocessor - Google Patents
Management circuit for self-powered microprocessor protection device microprocessor Download PDFInfo
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Abstract
A management circuit for a self-powered microprocessor protection device microprocessor comprises a watchdog circuit, a power monitoring and resetting circuit and a logic enabling circuit, wherein the logic enabling circuit is connected with the output end of the watchdog circuit and the output end of the power monitoring and resetting circuit. When the power monitoring and resetting circuit outputs effective power signals and the watchdog circuit outputs resetting signals, resetting signals of the microprocessor are output. Resetting false operation generated in the power-on and power-off processes of an external power source are avoided. Resetting false operation caused by delayed resetting when a general watchdog circuit is used after the power is connected can be avoided. The power monitoring and resetting circuit is connected with the microprocessor and provides effective signals, synchronous with the watchdog circuit, of the external power source, real-time monitoring of the state of the external power source and synchronizing of the watchdog circuit can be achieved by the microprocessor, and false operation due to the fact that the microprocessor can not forecast the state of the watchdog circuit can be avoided. Based on the synchronous signals, active peripheral circuit management is achieved, and the power consumption is reduced.
Description
Technical field
The present invention relates to a kind of microprocessor reset circuit, specifically a kind of self-powered microcomputer protecting device microprocessor management circuit.
Background technology
Microcomputer protector of electric power system; adopt embedded microprocessor technology; the detection of circuit electric current and voltage and breaker control, fault in switch cabinet equipment are judged, realize the function such as fault actions and alarm, are the visual plants of electric system power transmission and distribution safe and reliable operation; A large amount of uses of ring main unit, constantly increased the demand of microcomputer protecting device in recent years, had promoted the development of self-powered microcomputer protecting device.So-called self-powered microcomputer protecting device is without external dedicated power supply; and current transformer by its access wherein one group of winding with certain output power realize power taking; self-powered microcomputer protecting device passes through electricity-getting mutual inductor; in the situation that primary system has load current; induce the electric current for powering; realize the power supply of protective device, the operation that maintains microcomputer protecting device realizes protection and the control of electric power primary system.
Because circuit primary side current is with the fluctuation of load, when its power supply instability, particularly line maintenance load excise, self-powered microcomputer protecting device just cannot obtain external power source, and microcomputer protecting device microprocessor dead electricity cannot be moved; In order to make the quick response external fault of microprocessor realize real time monitoring function, must make microprocessor keep operation, can not make microprocessor frequent starting because externally fed is interrupted.When a circuit is sent a telegram here suddenly, because of microprocessor, to restart the time long, and monitoring and protecting in time misses protection action moment.
Therefore the microprocessor of self-powered microcomputer protecting device must adopt battery backup powered operation mode, and microprocessor completes after one-shot, by battery backup operation.In the time that external power source has electricity, protective device is by external power source, and when after external power source dead electricity, peripheral circuit loses power supply.Microprocessor, by powered battery, keeps operation.In the time that primary system is sent a telegram here again, microprocessor can drop into monitoring and guard mode fast without restarting.
Electric system high reliability request makes the microprocessor of microcomputer protecting device need to adopt outside complete autonomous watchdog circuit to realize the requirement of the anti-deadlock of microcomputer protecting device.As being called in " a kind of controlled watchdog reset system ", Chinese invention patent CN101281414B, name announce a kind of controlled watchdog reset system; comprise watchdog circuit and microprocessor; and be the system power supply of watchdog circuit and microprocessor power supply; between described watchdog circuit and microprocessor, be connected a buffer circuit; in the time of system power supply normal power supply; the reset signal of watchdog circuit resetting pin is passed to microprocessor reset terminal by buffer circuit, and the feeding-dog signal of microprocessor I/O pin is passed to watchdog circuit hello dog pin; In the time of system power supply power-off, described buffer circuit cut-off, cuts off contacting between watchdog circuit and microprocessor.Its effect, for having reduced system power dissipation, improved the serviceable life of battery, stopped the watchdog circuit system reset problem causing of delaying work simultaneously, improved widely the reliability of system.
But in this scheme, the threshold voltage of Vcc startup triode Q2 needs only 2V above, and normal Vcc supply voltage is 5V, the thresholding of ADM705 voltage monitoring is 4.65V, therefore there is the situation of several misoperations in when work in this circuit: (1) external power source Vcc powering up or power down process in occur that misoperation: Vcc is adding in electric process and power down process, its voltage is lower than ADM705 threshold voltage (4.65V) but higher than being enough to open in the interval of above-mentioned triode Q2 voltage.Now, because Vcc does not reach watchdog chip ADM705 threshold voltage, the output RESET that resets is low level.Vcc is enough to triode Q2 Base injection electric current simultaneously, and by triode conducting, therefore the collector of triode Q2 can be dragged down by RESET, namely draw the reset terminal of resistance R 12 to become low level by connecting, produce reset signal, if this state duration is enough long, can cause microprocessor error starting.(2) after outside power supply electrifying, Vcc voltage reaches ADM705 threshold voltage 4.65V requirement, still there will be reset misoperation: reach after ADM705 monitoring voltage thresholding at Vcc voltage, Vcc has met service requirement, now known according to ADM705 electrifying timing sequence figure, reach after threshold voltage 4.65V at Vcc, reset RESET signal still needs through t
rS(200ms), after time delay, just become high level.Therefore, foregoing circuit continues to produce the reset misoperation signal of 200mS will describe the reset misoperation producing in (1) after.
Summary of the invention
For this reason, the present invention resets and drops into when solving and only having realized external power source Vcc in prior art and have electricity, the Vcc isolation exit function that resets during without electricity, there is the reset problem of misoperation of external power source Vcc in power up and dead electricity process, thereby provide a kind of power on and dead electricity process in also there will not be misoperation, really realized the microprocessor management circuit of the reliability application of watchdog reset.
For solving the problems of the technologies described above, the present invention realizes by the following technical solutions:
A kind of self-powered microcomputer protecting device microprocessor management circuit,
Comprise watchdog circuit, remove output terminal be connected with microprocessor house dog, the clear signal that microprocessor sends triggers Watch Dog Timer zero clearing, overtime at described Watch Dog Timer, output reset signal;
Also comprise: power supply monitoring reset circuit, its external external power source, its output terminal is connected with described watchdog circuit and microprocessor respectively, in the time that external power source reaches threshold value, out-put supply useful signal, when external power source is during lower than threshold value, out-put supply invalid signals;
Logic-enabled circuit, be connected respectively with the output terminal of described watchdog circuit and described power supply monitoring reset circuit, in the time of described power supply monitoring reset circuit out-put supply useful signal and described watchdog circuit output reset signal, just export microprocessor reset signal.
Preferred described watchdog circuit is the watchdog circuit of pulsed output.
Preferred described watchdog circuit comprises backfeed loop and Watch Dog Timer, and the input end of described backfeed loop is connected with the output terminal of described Watch Dog Timer, and the output terminal of described backfeed loop is connected with described power supply monitoring reset circuit.
Preferred described logic-enabled circuit comprises current-limiting resistance R12, logic triode Q11, described logic triode Q11 is negative-positive-negative transistor, the emitter of described logic triode Q11 is connected with the output terminal of described Watch Dog Timer, the base stage of described logic triode Q11 is connected with the output terminal of described power supply monitoring reset circuit by current-limiting resistance R12, and the collector of described logic triode Q11 is connected with microprocessor the RESET input.
Preferred described logic-enabled circuit comprises on-off circuit and output circuit, described on-off circuit is connected respectively with the output terminal of output circuit, described Watch Dog Timer and the output terminal of described power supply monitoring reset circuit, and described output circuit is connected with microprocessor the RESET input.
Preferred described output circuit is open collector output circuit or open-drain output circuit.
Preferred described on-off circuit comprises triode Q1, described triode Q1 is P-channel field-effect transistor (PEFT) triode, the gate pole of described triode Q1 is connected with the output terminal of described Watch Dog Timer by resistance R 2, the source electrode of described triode Q1 is connected with the output terminal of described power supply monitoring reset circuit, and the drain electrode of described triode Q1 is connected with the input end of described output circuit.
Preferred described output circuit is open-drain output circuit, described open-drain output circuit comprises resistance R 3, one end of described resistance R 3 is the input end of described open-drain output circuit, the other end of described resistance R 3 is connected with the gate leve of triode Q2, the source electrode of described triode Q2 is connected with its gate leve by resistance R 4, also ground connection of the source electrode of described triode Q2, the drain electrode of described triode Q2 is connected with microprocessor the RESET input.
Preferred described backfeed loop comprises diode D4, the anode of diode D4 is connected with the output terminal of described Watch Dog Timer, the negative electrode of described diode D4 is connected with the input end of comparer, the two ends of described diode D4 are also parallel with resistance R 1, described resistance R 1 is connected one end of capacitor C 1 with the parallel connection point of the negative electrode of described diode D4, the other end ground connection of described capacitor C 1, the output terminal of described comparer is connected with the input end of described power supply monitoring reset circuit.
Preferred described Watch Dog Timer, described power supply monitoring reset circuit and the integrated integrated circuit that is set to of described comparer.
Technique scheme of the present invention has the following advantages compared to existing technology,
(1) self-powered microcomputer protecting device microprocessor management circuit of the present invention, comprise watchdog circuit, remove output terminal be connected with microprocessor house dog, the clear signal that microprocessor sends triggers Watch Dog Timer zero clearing, described Watch Dog Timer is overtime, output reset signal, power supply monitoring reset circuit, its external external power source, its output terminal is connected with described watchdog circuit and microprocessor respectively, in the time that external power source reaches threshold value, out-put supply useful signal, when external power source is during lower than threshold value, out-put supply invalid signals, logic-enabled circuit, be connected respectively with the output terminal of described watchdog circuit and described power supply monitoring reset circuit, in the time of described power supply monitoring reset circuit out-put supply useful signal and described watchdog circuit output reset signal, just export microprocessor reset signal, when having realized external power source and having had electricity higher than threshold value, the reset signal of watchdog circuit sends to microprocessor from logic-enabled circuit, realize and resetting, in the time that external power source does not have electricity, be that external power source is lower than threshold value, described power supply monitoring reset circuit out-put supply invalid signals, can not meet the logic output condition of described logic-enabled circuit, therefore the reset signal conductively-closed of described watchdog circuit, avoid external power source power on and dead electricity process produce reset misoperation, and the reset misoperation problem that uses general watchdog circuit to cause due to one section of time-delay reset after power supply electrifying.Simultaneously, described power supply monitoring reset circuit is connected with microprocessor, the external power source of synchronizeing with watchdog circuit useful signal is provided, realize the synchronous of the implementing monitoring of microprocessor to outside power supply status and watchdog circuit, the misoperation of having avoided microprocessor cannot predict house dog state and to cause, and based on this synchronizing signal, realize active peripheral circuit management, power-dissipation-reduced function.
(2) self-powered microcomputer protecting device microprocessor management circuit of the present invention; described watchdog circuit is the watchdog circuit of pulsed output; described watchdog circuit comprises backfeed loop and Watch Dog Timer; the input end of described backfeed loop is connected with the output terminal of described Watch Dog Timer; its output terminal is connected with described power supply monitoring reset circuit; by described backfeed loop is set, to realize pulse width adjustable; to adapt to the requirement of different microprocessors to outside reseting pulse width; can arrange flexibly, there is applicability widely.
(3) self-powered microcomputer protecting device microprocessor management circuit of the present invention, described logic-enabled circuit comprises current-limiting resistance, logic triode, described logic triode Q11 is negative-positive-negative transistor, the emitter of described logic triode Q11 is connected with the output terminal of described Watch Dog Timer, the base stage of described logic triode Q11 is connected with the output terminal of described power supply monitoring reset circuit by current-limiting resistance R12, the collector of described logic triode Q11 is connected with microprocessor the RESET input, only be provided with a small amount of peripheral discrete component, circuit is simple, cost is low, be applicable to using on a large scale.
Accompanying drawing explanation
For content of the present invention is more likely to be clearly understood, below according to a particular embodiment of the invention and by reference to the accompanying drawings, the present invention is further detailed explanation, wherein
Fig. 1 is the structured flowchart of one embodiment of the invention;
Fig. 2 is the circuit theory diagrams of one embodiment of the invention;
Fig. 3 is the circuit theory diagrams of one embodiment of the invention.
Embodiment
The embodiment of self-powered microcomputer protecting device microprocessor management circuit of the present invention is provided below.
Embodiment 1
Self-powered microcomputer protecting device microprocessor management circuit of the present invention; as shown in Figure 1; comprise watchdog circuit; described watchdog circuit is the watchdog circuit of pulsed output; pulse width can be realized adjustable; to adapt to the requirement of different microprocessors to outside reseting pulse width; described watchdog circuit is removed output terminal with microprocessor house dog and is connected; the house dog feeding-dog signal of microprocessor output pulsed, utilize this signal rising edge and or negative edge realize the zero clearing of Watch Dog Timer.Described Watch Dog Timer is overtime, output reset signal, also be provided with power supply monitoring reset circuit, its external external power source, as external power source by diode to microprocessor power supply, in order to make the voltage of power supply monitoring reset circuit input identical with the voltage of microprocessor, external power source is also connected with described power supply monitoring reset circuit by diode, the output terminal of power supply monitoring reset circuit is connected with described watchdog circuit and microprocessor respectively, in the time that external power source reaches threshold value, threshold value is set according to supply voltage and microprocessor voltage, described power supply monitoring reset circuit out-put supply useful signal, when external power source is during lower than threshold value, out-put supply invalid signals, also be provided with logic-enabled circuit, be connected respectively with the output terminal of described watchdog circuit and described power supply monitoring reset circuit, in the time of described power supply monitoring reset circuit out-put supply useful signal and described watchdog circuit output reset signal, just export microprocessor reset signal.
It is as follows that the present invention realizes principle: in the time that outer power voltage has electricity higher than threshold value, described power supply monitoring reset circuit out-put supply useful signal, add the reset signal of the above watchdog circuit, meet the output logic of described logic-enabled circuit, the reset signal of watchdog circuit can send to microprocessor from logic-enabled circuit, realize and resetting, in the time that external power source does not have electricity, external power source is lower than threshold value, described power supply monitoring reset circuit out-put supply invalid signals, can not meet the logic output condition of described logic-enabled circuit, therefore the reset signal conductively-closed of described watchdog circuit, avoid external power source power on and dead electricity process produce reset misoperation, and the reset misoperation problem that uses general watchdog circuit to cause due to one section of time-delay reset after power supply electrifying, simultaneously, described power supply monitoring reset circuit is connected with microprocessor, the external power source of synchronizeing with watchdog circuit useful signal is provided, realize the synchronous of the implementing monitoring of microprocessor to outside power supply status and watchdog circuit, the misoperation of having avoided microprocessor cannot predict house dog state and to cause, and based on this synchronizing signal, realize active peripheral circuit management, power-dissipation-reduced function.
Embodiment 2
On the basis of the self-powered microcomputer protecting device microprocessor management circuit described in embodiment 1, described watchdog circuit comprises backfeed loop and Watch Dog Timer, as shown in Figure 2, described Watch Dog Timer, described power supply monitoring reset circuit and described comparer be integrated being arranged on integrated circuit in the present embodiment, in reality, adopt chip MAX706, the input/output terminal of each circuit adopts the pin of MAX706 chip, the input end that the WDI end of described MAX706 chip is described Watch Dog Timer, it is connected with the general purpose I/O pin of microprocessor, the house dog feeding-dog signal of described IO pin output pulsed, utilize the rising edge of this signal and negative edge to realize the zero clearing of Watch Dog Timer, the output terminal that the WDO end of described MAX706 chip is described Watch Dog Timer, WDO end output high level after described Watch Dog Timer starts, and in timing course, keep high level, when described Watch Dog Timer overtime, WDO holds output low level, and keep low level, until be eliminated, after described Watch Dog Timer is eliminated, WDO end recovers to keep high level.External power source EVcc is connected with the power supply input pin Vcc of described MAX706 chip by diode D3, gives chip power supply, and another external power source EVcc returns microprocessor power supply, makes MAX706 chip and microprocessor have identical voltage.
The RESET of MAX706 chip holds as power supply monitoring reset circuit output terminal, and its level state shows that whether external power source is effective.RESET end output high level shows that external power source reaches threshold value (if MAX706S is 2.93V) and reliable and stable (RESET end is through just exporting high level after the delay confirmation of 200ms), and RESET holds after power supply low pressure threshold, output low level immediately.As the indication of external power source state, reliable in real time with the RESET end output of MAX706.Access microprocessor is convenient to program and is responded in time.The RESET end of MAX706 is gone back one end of contact resistance R5, the other end ground connection of described resistance R 5, described RESET end is realized drop-down by resistance R 5, resistance R 5 value 10k ohms are between 100k ohm, to guarantee that circuit is under dead electricity quits work situation, this pin keeps low level, avoids microprocessor erroneous judgement, the GND end ground connection of described MAX706 chip.
Described logic-enabled circuit comprises current-limiting resistance R2, logic triode Q11, described logic triode Q11 is negative-positive-negative transistor, the emitter of described logic triode Q11 is connected with the WDO end that the output terminal of described Watch Dog Timer is MAX706 chip, the RESET end that the base stage of described logic triode Q11 is MAX706 chip by current-limiting resistance R12 with the output terminal of described power supply monitoring reset circuit is connected, and the collector of described logic triode Q11 is connected with microprocessor the RESET input.
The logic theory of described logic-enabled circuit is: the RESET end output high level that only has MAX706, WDO end output low level simultaneously, the high level output of RESET end is the Base injection electric current to described logic triode Q11 by current-limiting resistance R12, flow to emitter and flow into low level WDO end, now logic triode Q11 conducting, its collector is switched on, identical with emitter voltage, namely the level of WDO end has been applied to the emitter of logic triode Q11, and the reset pin of connected microprocessor is reduced to low level state, realize reset.Above-mentioned logic shows, this logic-enabled circuit is after externally fed is normal (RESET end keeps high level output) and just send reset signal in Watch Dog Timer overtime (WDO holds output low level) situation only.And this situation may be only microprocessor program run fly, do not remove in time that house dog causes, the reset misoperation of having avoided other factors to produce completely, under above-mentioned enabled state, in all the other situations, can not reset to microprocessor output, therefore avoided external power source in power up, dead electricity process, and in the time powering on, Vcc voltage reaches thresholding and the RESET output of MAX706 still keeps in 200ms low level process, exports unnecessary reset misoperation.
Described backfeed loop comprises diode D4, the anode of diode D4 is that WDO end is connected with the output terminal of described Watch Dog Timer, the negative electrode of described diode D4 is that PFI end is connected with the input end of comparer, the two ends of described diode D4 are also parallel with resistance R 1, described resistance R 1 is connected one end of capacitor C 1 with the parallel connection point of the negative electrode of described diode D4, the other end ground connection of described capacitor C 1, the output terminal of described comparer is that PFO end is that MR end is connected with the input end of described power supply monitoring reset circuit, the comparative voltage benchmark of described comparer is 1.25V, PFI end input voltage is greater than 1.25V, PFO output high level, otherwise PFI end input voltage is less than 1.25V, PFO holds output low level.
The principle of work of described backfeed loop: power on and reach after voltage threshold at external power source EVcc, WDO end output high level, charge to capacitor C 1 by diode D4 and resistance R 1 simultaneously, diode D4 can accelerate charging process, makes the voltage in capacitor C 1 exceed fast 1.25V and reach the logic high voltage identical with Vcc.Detect by described comparer, comparer PFO end output high level, high level output can not exert an influence to described power supply monitoring reset circuit to MR end, now, has completed watchdog circuit and peripheral circuit initialization.RESET holds after powering on, and its output becomes high level from low level, and described Watch Dog Timer starts timing, and WDO end keeps output high level.When described Watch Dog Timer not at the appointed time (MAX706 provides the time span of 1.6s) removed by microprocessor, Watch Dog Timer is overtime, WDO holds output low level.Now logic-enabled circuit logic condition meets, i.e. WDO end output low level, and RESET end output high level, described logic-enabled circuit output low level, microprocessor resets and is triggered.Meanwhile, WDO holds output low level, moves resistance R 1 one end to low level.Capacitor C 1 starts to discharge (diode D4 cut-off, inoperative) to WDO end by resistance R 1, and the voltage on PFI end starts to decline, until lower than after comparator reference 1.25V, PFO holds output low level, drives the MR end of Low level effective, makes RESET output low level.Meanwhile, the Watch Dog Timer zero clearing that is reset, WDO end is set recovery high level.RESET end output low level, WDO end output high level, described logic-enabled circuit reset output is closed, and microprocessor resets and finishes, and restarts working procedure.WDO end recovers output high level, restart to charge to capacitor C 1 fast by diode D4 and resistance R 1, make PFI terminal voltage exceed fast 1.25V, recover the high level state of PFO end and MR end, recover after high level at MR end, the RESET end of MAX706 chip recovers output high level after 200ms time delay, and Watch Dog Timer also restarts timing, repeats last round of operational process.Said process, RESET end has one section of short time low level state that not external power source decompression causes, because microprocessor is now also starting and resume operation in process, the short time low level of RESET end, does not affect microprocessor and restarts the judgement to outside power supply status.Said process moves repeatedly, has just realized the watchdog circuit of pulsed output.Wherein, the reseting pulse width that acts on microprocessor determines by electric capacity R1 and C1 discharge time, refers to that capacitor C 1 discharges by resistance R 1 this discharge time, and PFI terminal voltage drops to the lasting time of 1.25V process by 3.3V.Therefore the parameter of control capacittance C1 and resistance R 1, the reseting pulse width that can regulate this circuit to export, to adapt to the requirement of different microprocessors to outside reseting pulse width, makes circuit of the present invention have applicability and dirigibility widely.
Embodiment 3
On the basis of the self-powered microcomputer protecting device microprocessor management circuit described in embodiment 1, described watchdog circuit comprises backfeed loop and Watch Dog Timer, described Watch Dog Timer, described power supply monitoring reset circuit and described comparer be integrated being arranged on integrated circuit in the present embodiment, in reality, adopt chip MAX706, the input/output terminal of each circuit adopts the pin of MAX706 chip, the input end that the WDI end of described MAX706 chip is described Watch Dog Timer, it is connected with the general purpose I/O pin of microprocessor, the house dog feeding-dog signal of described IO pin output pulsed, utilize the rising edge of this signal and negative edge to realize the zero clearing of Watch Dog Timer, the output terminal that the WDO end of described MAX706 chip is described Watch Dog Timer, WDO end output high level after described Watch Dog Timer starts, and in timing course, keep high level, when described Watch Dog Timer overtime, WDO holds output low level, and keep low level, until be eliminated, after described Watch Dog Timer is eliminated, WDO end recovers to keep high level.External power source EVcc is connected with the power supply input pin Vcc of described MAX706 chip by diode D3, gives chip power supply, and another external power source EVcc returns microprocessor power supply, makes MAX706 chip and microprocessor have identical voltage.
The RESET of MAX706 chip holds as power supply monitoring reset circuit output terminal, and its level state shows that whether external power source is effective.RESET end output high level shows that external power source reaches threshold value (if MAX706S is 2.93V) and reliable and stable (RESET end is through just exporting high level after the delay confirmation of 200ms), and RESET holds after power supply low pressure threshold, output low level immediately.As the indication of external power source state, reliable in real time with the RESET end output of MAX706.Access microprocessor is convenient to program and is responded in time.The RESET end of MAX706 is gone back one end of contact resistance R5, the other end ground connection of described resistance R 5, described RESET end is realized drop-down by resistance R 5, resistance R 5 value 10k ohms are between 100k ohm, to guarantee that circuit is under dead electricity quits work situation, this pin keeps low level, avoids microprocessor erroneous judgement, the GND end ground connection of described MAX706 chip.
Described logic-enabled circuit comprises on-off circuit and output circuit, as shown in Figure 3, described on-off circuit comprises triode Q1, described triode Q1 is P-channel field-effect transistor (PEFT) triode in the present embodiment, the gate pole of described triode Q1 is that WDO end is connected by resistance R 2 and the output terminal of described Watch Dog Timer, the source electrode of described triode Q1 is that RESET end is connected with the output terminal of described power supply monitoring reset circuit, and the drain electrode of described triode Q1 is connected with the input end of described output circuit.
In the present embodiment, described output circuit is open-drain output circuit, described open-drain output circuit comprises resistance R 3, one end of described resistance R 3 is the input end of described open-drain output circuit, the other end of described resistance R 3 is connected with the gate leve of triode Q2, the source electrode of described triode Q2 is connected with its gate leve by resistance R 4, also ground connection of the source electrode of described triode Q2, the drain electrode of described triode Q2 is connected with microprocessor the RESET input, the mode that can convert as other, described triode Q1 can also be PNP triode, described output circuit can also be open collector output circuit.
This logic-enabled circuit only just sends reset signal from described open-drain output circuit at externally fed normal rear (RESET end keeps high level output) in Watch Dog Timer overtime (WDO holds output low level) situation.And this situation may be only microprocessor program run fly, do not remove in time that house dog causes, the reset misoperation of having avoided other factors to produce completely, under above-mentioned enabled state, in all the other situations, can not reset to microprocessor output, therefore avoided external power source in power up, dead electricity process, and in the time powering on, Vcc voltage reaches thresholding and the RESET output of MAX706 still keeps in 200ms low level process, exports unnecessary reset misoperation.
Described backfeed loop comprises diode D4, the anode of diode D4 is that WDO end is connected with the output terminal of described Watch Dog Timer, the negative electrode of described diode D4 is that PFI end is connected with the input end of comparer, the two ends of described diode D4 are also parallel with resistance R 1, described resistance R 1 is connected one end of capacitor C 1 with the parallel connection point of the negative electrode of described diode D4, the other end ground connection of described capacitor C 1, the output terminal of described comparer is that PFO end is that MR end is connected with the input end of described power supply monitoring reset circuit, the comparative voltage benchmark of described comparer is 1.25V, PFI end input voltage is greater than 1.25V, PFO output high level, otherwise PFI end input voltage is less than 1.25V, PFO holds output low level, the principle of described backfeed loop is identical with above-described embodiment 2.
The embodiment that can convert as other, described Watch Dog Timer, described power supply monitoring reset circuit and described comparer can adopt independent circuit setting, realize function same with the above-mentioned embodiment, in the present embodiment, be set to integrated circuit for reducing costs, reducing circuit space is set, is preferred set-up mode.
Obviously, above-described embodiment is only for example is clearly described, and the not restriction to embodiment.For those of ordinary skill in the field, can also make other changes in different forms on the basis of the above description.Here without also giving exhaustive to all embodiments.And the apparent variation of being extended out thus or variation are still among the protection domain in the invention.
Claims (10)
1. a self-powered microcomputer protecting device microprocessor management circuit,
Comprise watchdog circuit, remove output terminal be connected with microprocessor house dog, the clear signal that microprocessor sends triggers Watch Dog Timer zero clearing, overtime at described Watch Dog Timer, output reset signal;
It is characterized in that, also comprise:
Power supply monitoring reset circuit, its external external power source, its output terminal is connected with described watchdog circuit and microprocessor respectively, in the time that external power source reaches threshold value, out-put supply useful signal, when external power source is during lower than threshold value, out-put supply invalid signals;
Logic-enabled circuit, be connected respectively with the output terminal of described watchdog circuit and described power supply monitoring reset circuit, in the time of described power supply monitoring reset circuit out-put supply useful signal and described watchdog circuit output reset signal, just export microprocessor reset signal.
2. microprocessor management circuit according to claim 1, is characterized in that, described watchdog circuit is the watchdog circuit of pulsed output.
3. microprocessor management circuit according to claim 1 and 2, it is characterized in that, described watchdog circuit comprises backfeed loop and Watch Dog Timer, the input end of described backfeed loop is connected with the output terminal of described Watch Dog Timer, and the output terminal of described backfeed loop is connected with described power supply monitoring reset circuit.
4. according to the arbitrary described microprocessor management circuit of claim 1-3, it is characterized in that, described logic-enabled circuit comprises current-limiting resistance R12, logic triode Q11, described logic triode Q11 is negative-positive-negative transistor, the emitter of described logic triode Q11 is connected with the output terminal of described Watch Dog Timer, the base stage of described logic triode Q11 is connected with the output terminal of described power supply monitoring reset circuit by current-limiting resistance R12, and the collector of described logic triode Q11 is connected with microprocessor the RESET input.
5. according to the arbitrary described microprocessor management circuit of claim 1-3, it is characterized in that, described logic-enabled circuit comprises on-off circuit and output circuit, described on-off circuit is connected respectively with the output terminal of output circuit, described Watch Dog Timer and the output terminal of described power supply monitoring reset circuit, and described output circuit is connected with microprocessor the RESET input.
6. microprocessor management circuit according to claim 5, is characterized in that, described output circuit is open collector output circuit or open-drain output circuit.
7. according to the microprocessor management circuit described in claim 5 or 6, it is characterized in that, described on-off circuit comprises triode Q1, described triode Q1 is P-channel field-effect transistor (PEFT) triode, the gate pole of described triode Q1 is connected with the output terminal of described Watch Dog Timer by resistance R 2, the source electrode of described triode Q1 is connected with the output terminal of described power supply monitoring reset circuit, and the drain electrode of described triode Q1 is connected with the input end of described output circuit.
8. according to the arbitrary described microprocessor management circuit of claim 5-7, it is characterized in that, described output circuit is open-drain output circuit, described open-drain output circuit comprises resistance R 3, one end of described resistance R 3 is the input end of described open-drain output circuit, the other end of described resistance R 3 is connected with the gate leve of triode Q2, the source electrode of described triode Q2 is connected with its gate leve by resistance R 4, also ground connection of the source electrode of described triode Q2, the drain electrode of described triode Q2 is connected with microprocessor the RESET input.
9. according to the arbitrary described microprocessor management circuit of claim 3-8, it is characterized in that, described backfeed loop comprises diode D4, the anode of diode D4 is connected with the output terminal of described Watch Dog Timer, the negative electrode of described diode D4 is connected with the input end of comparer, the two ends of described diode D4 are also parallel with resistance R 1, described resistance R 1 is connected one end of capacitor C 1 with the parallel connection point of the negative electrode of described diode D4, the other end ground connection of described capacitor C 1, the output terminal of described comparer is connected with the input end of described power supply monitoring reset circuit.
10. according to the arbitrary described microprocessor management circuit of claim 1-9, it is characterized in that described Watch Dog Timer, described power supply monitoring reset circuit and the integrated integrated circuit that is set to of described comparer.
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