CN204376884U - Satellite receiver system-halted reset device - Google Patents
Satellite receiver system-halted reset device Download PDFInfo
- Publication number
- CN204376884U CN204376884U CN201520056692.1U CN201520056692U CN204376884U CN 204376884 U CN204376884 U CN 204376884U CN 201520056692 U CN201520056692 U CN 201520056692U CN 204376884 U CN204376884 U CN 204376884U
- Authority
- CN
- China
- Prior art keywords
- pin
- integrated package
- ground connection
- resistance
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Direct Current Feeding And Distribution (AREA)
Abstract
The utility model discloses a kind of satellite receiver system-halted reset device, comprises audio detection, time delay and power-off restarting element circuit, and control signal is from audio frequency, and it exports and controls directly to be connected in series to decoder supply line; Audio signal adjusts through potentiometer RW1, delivers to 5 pin of integrated package U1, at 1 pin and 10 ~ 18 pin of U1, just has and exports by the level of audio voltage height change, drawn by 1 pin of this level as control signal from U1, deliver to delay circuit through photoelectrical coupler U2; 2,3 unit 2A, 2B, 2Y, 3A, 3B, 3Y and resistance R8, electric capacity C4, the potentiometer RW3 of the inner NAND gate of power-off restarting electricity routing integrated block U4 form single-shot trigger circuit; This device embedded access decoder power supply circuits, this circuit of only single power-off restarting, can not have an impact to other circuit function of complete machine; Overcoming recovers to crash need turn off the defect of restarting power supply again, avoids because frequent switching on and shutting down of crashing too much bring unnecessary electron injury to receiver.
Description
Technical field
The utility model relates to a kind of satellite receiver electronic circuit applying electronic device, particularly satellite receiver system-halted reset device.
Background technology
At present, known satellite receiver deadlock phenomenon is the Universal Faults that receiver often occurs.Satellite receiver crashes, and be exactly satellite receiver inner demoder because many factors circuit has been absorbed in endless loop, the releasing and oneself can not reset, only having artificial powered-down to start shooting could reset again, and this is also the technology that present people often adopt.The method such as introduced in " Chinese cable TV " 3 phases in 2009 " reply that digital satellite receiver easily crashes an and measure " literary composition, and " China Electronics's net " (http://www.21ic./app/powr//201206/126159.ntm) " design and fabrication of satellite receiver deadlock restore circuit " etc., what adopt is exactly the mode that the mode of restarting complete machine power supply solves that satellite receiver crashes, their defect is exactly because the shutoff of complete machine and restart power supply, bring unnecessary voltage will certainly to other parts of receiver, rush of current, if fault occurs more frequent, unnecessary electron injury will be caused to receiver.
Utility model content
The utility model object is closed electricity and restart for overcoming power supply to bring electron injury defect to complete machine, and whether receiver crashes to provide one to identify, automatically recovers to reset, and can not affect the satellite receiver system-halted reset device of other function of complete machine.
The utility model provides a kind of circuit arrangement for powering of Embedded access receiver decoder, and effect automatically resets when detecting that satellite receiver crashes.According to satellite receiver deadlock audio signal disappear feature, this device according to audio level height change and with or without, make the control signal of circuit arrangement.Carry out restarting of control circuit; The decoder circuit that it is only absorbed in endless loop to occurring to crash is single to be resetted, and can't affect other functions of complete machine.
The utility model is divided into audio detection circuit, delay circuit and power-off restarting three unit circuit.Control signal is from audio frequency, and the output of this delay circuit controls the supply line be directly connected in series to decoder.Its flow process is, draws a shunting sign, deliver to audio detection circuit from satellite receiver audio output, by photoelectrical coupler, then to delay circuit.If there is deadlock situation to occur, delay circuit just exports a high level to power-off restarting circuit through a time delays.The concrete technical scheme adopted for solving its technical problem is:
A kind of satellite receiver system-halted reset device, comprises audio detection circuit, delay circuit and power-off restarting element circuit, it is characterized in that: control signal is from audio frequency, and the output of this delay circuit controls the supply line be directly connected in series to decoder; Audio signal adjusts through potentiometer RW1, delivers to 5 pin of integrated package U1, at 1 pin and 10 ~ 18 pin of U1, just has and exports by the level of audio voltage height change, drawn by 1 pin of this level as control signal from U1, deliver to delay circuit through photoelectrical coupler U2; 2,3 unit 2A, 2B, 2Y, 3A, 3B, 3Y and resistance R8, electric capacity C4, the potentiometer RW3 of the described inner NAND gate of power-off restarting electricity routing integrated block U4 form single-shot trigger circuit; Resistance R6 through 1,2 pin of integrated package U4 to voltage stabilizing didoe D11 ground connection; 3 pin of U4 connect 4 pin of U4,5 pin to 8 pin of U4 to 2 pin of integrated package U3,1 pin, resistance R7 meet power supply 5V; Power supply 12V through 9 pin of 6 foot meridian capacitor C4, U4 of resistance R8, integrated package U4 to potentiometer RW3 ground connection; 10 pin of integrated package U4 are to interrupteur SW ground connection; Power supply 12V connects 3 pin of U3, the 4 pin ground connection of U3 through 4,5 pin of resistance R9, relay J S; 1 pin of section end 3.3v-in contact relay JS in decoder supply line, 2 pin of section end 3.3v-out contact relay JS under decoder supply line, 3 pin of JS are through luminous tube D12 to resistance R10 ground connection.
Audio input interface A-in in described audio detection circuit connects 5 pin of potentiometer RW1 to integrated package U1 through R3 ground connection; Power supply 12V through 3,9 pin of U1 to electric capacity C1 ground connection; 6 pin of integrated package U1,7 pin are through resistance R2, R1 ground connection, and 8 pin of integrated package U1 are through R1 ground connection, and 6 pin, 7 pin of U1 are connected with 8 pin through R2,2 pin of U1,4 pin ground connection; Power supply 12V through luminous tube D1 ~ D9's and be attached to 10 ~ 18 pin of U1,1 pin of U1 connects 2 pin of photoelectrical coupler U2; Power supply 12V is connected with 1 pin of photoelectrical coupler U2,3 pin respectively through resistance R5, R4, and 4 pin of U2 connect 2 pin of integrated package U3,6 pin.
Described delay circuit by integrated package U3, potentiometer RW2, resistance R6, electric capacity C2, C3, diode D10 forms, and 2,6 pin of U3 are input, and 3 pin are output; 2 pin of integrated package U3,6 pin connect 4 pin of photoelectrical coupler U2; 4 pin, the 8 foot meridian capacitor C2 of U3 are connected with 2 pin, 6 pin; Power supply 12V connects 4 pin, 8 pin of U3; Diode D10 and potentiometer RW2 are in parallel to be connected with 2 pin of integrated package U3,6 pin again, other end ground connection; 5 pin of U3 connect ground connection after electric capacity C3, and 3 pin of U3 connect 1 pin, 2 pin of integrated package U4, the 1 pin ground connection of U3 through resistance R6,7 pin are empty.
The beneficial effects of the utility model are: this device Embedded access decoder power supply circuits, and this circuit of only single power-off restarting, extremely resets pointed to receiver, effect of accuracy, can not have an impact to other circuit function of complete machine; Overcome and recover crash and again will turn off the defect of restarting power supply, can avoid because crashing too much, frequent switching on and shutting down bring unnecessary electron injury to receiver; This device circuit is compact to design, and structure is simple.
Accompanying drawing explanation
Below in conjunction with accompanying drawing, the utility model is described in further detail.
Fig. 1 is the theory diagram of the utility model satellite receiver reset circuit.
Fig. 2 is circuit theory diagrams.
In FIG: label 5V, 12V are power supply, A-in is audio input interface, and 3.3v-in is section end in decoder supply line, and 3.3v-out is section end under decoder supply line.
In fig. 2: resistance R1 ~ R10; Electric capacity C1 ~ C4; Integrated package U1, U3, U4; Photoelectrical coupler U2, U5; Diode D10; Luminous tube D1 ~ D9, D12; Voltage stabilizing didoe D11; Potentiometer RW1 ~ RW3; Interrupteur SW; Relay J S.
Embodiment
As shown in Figure 1, in the utility model device, 3.3v-in is connected on the upper section end of the decoder supply line disconnected, and 3.3v-out is connected on lower section end; A-in connects satellite receiver audio output; Power supply 5V, 12V can directly draw from the power module of controlled receiver.
As shown in Figure 2, audio detection circuit is by integrated package U1 (model LM3915) and resistance R1 ~ R5, potentiometer RW1, electric capacity C1, light-emitting diode D1 ~ D9, form with photoelectrical coupler U2 (PC817), LM3915 is LED ten drive integrated circult, is inside provided with ten alternating current-direct current comparison amplifiers.Audio input interface A-in arrives 5 pin of integrated package U1 after connecting potentiometer RW1,5 pin are through R3 ground connection; Power supply 12V through 3,9 pin of U1 to electric capacity C1 ground connection; 6 pin of U1,7 pin are through resistance R2, R1 ground connection; 8 pin of integrated package U1 are through R1 ground connection, and 6 pin, 7 pin of U1 are connected with 8 pin through R2,2 pin of U1,4 pin ground connection; Power supply 12V through luminous tube D1 ~ D9's and be attached to 10 ~ 18 pin of U1,1 pin of U1 connects 2 pin of photoelectrical coupler U2; Power supply 12V is connected with 1 pin of photoelectrical coupler U2,3 pin respectively through resistance R5, R4, and 4 pin of U2 connect 2 pin of integrated package U3,6 pin.Audio signal adjusts through potentiometer RW1, delivers to 5 pin of integrated package U1, like this at 1 pin and 10 ~ 18 pin of U1, just has and exports by the level of audio voltage height change.1 pin of this level as control signal from U1 is drawn, delivers to delay circuit through photoelectrical coupler U2; The state that in circuit, diode D1 ~ D9 exports in order to show audio frequency.
Delay circuit: by integrated package U3 (model NE555), potentiometer RW2, resistance R6, electric capacity C2, C3, diode D10 (model IN4148) forms.2,6 pin of U3 are inputs, and 3 pin are output; 2 pin of integrated package U3,6 pin connect 4 pin of U2; 4 pin, the 8 foot meridian capacitor C2 of U3 are connected with 2 pin, 6 pin; Power supply 12V connects 4 pin, 8 pin of U3; Diode D10 and RW2 is in parallel to be connected with 2 pin of integrated package U3,6 pin again, other end ground connection; 5 pin of U3 connect after electric capacity C3 to ground; 3 pin of U3 connect 1 pin, 2 pin of integrated package U4 through resistance R6.The 1 pin ground connection of U3,7 pin are empty.In setting-up time, if input constantly has the input of height/end level, 3 pin of U3 just remain that low level is constant, do not export.Namely can not in the interval of the normal hesitations of audio frequency and sound and misoperation.Potentiometer RW2 is used for regulating time of time delay, generally adjustable at 20 ~ 30 seconds.
Power-off restarting circuit: 2,3 unit (2A, 2B, 2Y, 3A, 3B, 3Y) and resistance R8 of the inner NAND gate of this electric routing integrated block U4 (model 74F00), electric capacity C4, potentiometer RW3 form single-shot trigger circuit; Photoelectrical coupler U5 (model PC817), relay J S and resistance R9, R10, LED D12 forms its load, and Unit 1 (1A, 1B, 1Y) of NAND gate and voltage stabilizing didoe D11 are its input interfaces.Resistance R6 through 1,2 pin of integrated package U4 to voltage stabilizing didoe D11 ground connection; 3 pin of U4 connect 4 pin of U4,5 pin to 8 pin of U4 to 2 pin of integrated package U3,1 pin, resistance R7 meet power supply 5V; Power supply 12V through 9 pin of 6 foot meridian capacitor C4, U4 of resistance R8, integrated package U4 to potentiometer RW3 ground connection; 10 pin of integrated package U4 are to interrupteur SW ground connection; Power supply 12V connects 3 pin of U3, the 4 pin ground connection of U3 through 4,5 pin of resistance R9, relay J S; 1 pin of section end 3.3v-in contact relay JS in decoder supply line, 2 pin of section end 3.3v-out contact relay JS under decoder supply line, 3 pin of JS are through luminous tube D12 to resistance R10 ground connection.
The course of work of power-off restarting circuit: time static, i.e. signal normal condition, 4 pin of integrated package U4,5 pin are high level, 6 pin low levels, and 8 pin of U4 export high level.Time dynamic, when abnormal signal, 4 pin of integrated package U4 just have low level to input, 6 pin of U4 are high level, the positive terminal voltage of electric capacity C4 is suddenly by 0 volt of+5 volt that rise, again because the both end voltage of C4 can not kick, so just there is a positive voltage to be added to 9 pin of integrated package U4, at this moment 8 pin of U4 also have by high level to low level saltus step, along with electric capacity C4 is from power supply to resistance R8, electric capacity C4, the charging process of potentiometer RW3, the 9 pin voltages of U4 slowly decline, when dropping to threshold voltage, it is again high level that 8 pin of U4 export, a negative-going pulse is just had to be formed at 8 pin of integrated package like this.At load end, this negative-going pulse of connection through photoelectrical coupler U5 connects relay J S and ground, and 1 pin of relay J S and 2 pin disconnect and connect 3 pin, recovers again afterwards to connect with 2 pin at once, make a round trip action instantaneously, namely completes decoder and to power power-off restarting process.In circuit, potentiometer RW3 is used for regulating the width of negative sense pulsewidth, generally can be adjusted to 0.7 ~ 0.5 second and is advisable.D12 is that device circuit work display is used.Interrupteur SW be down circuitry restart forbid end, when SW close, circuit does not work.
Claims (3)
1. a satellite receiver system-halted reset device, comprises audio detection circuit, delay circuit and power-off restarting element circuit, it is characterized in that: control signal is from audio frequency, and the output of this delay circuit controls the supply line be directly connected in series to decoder; Audio signal adjusts through potentiometer RW1, delivers to 5 pin of integrated package U1, at 1 pin and 10 ~ 18 pin of U1, just has and exports by the level of audio voltage height change, drawn by 1 pin of this level as control signal from U1, deliver to delay circuit through photoelectrical coupler U2; 2,3 unit 2A, 2B, 2Y, 3A, 3B, 3Y and resistance R8, electric capacity C4, the potentiometer RW3 of the described inner NAND gate of power-off restarting electricity routing integrated block U4 form single-shot trigger circuit; Resistance R6 through 1,2 pin of integrated package U4 to voltage stabilizing didoe D11 ground connection; 3 pin of U4 connect 4 pin of U4,5 pin to 8 pin of U4 to 2 pin of integrated package U3,1 pin, resistance R7 meet power supply 5V; Power supply 12V through 9 pin of 6 foot meridian capacitor C4, U4 of resistance R8, integrated package U4 to potentiometer RW3 ground connection; 10 pin of integrated package U4 are to interrupteur SW ground connection; Power supply 12V connects 3 pin of U3, the 4 pin ground connection of U3 through 4,5 pin of resistance R9, relay J S; 1 pin of section end 3.3v-in contact relay JS in decoder supply line, 2 pin of section end 3.3v-out contact relay JS under decoder supply line, 3 pin of JS are through luminous tube D12 to resistance R10 ground connection.
2. according to satellite receiver system-halted reset device according to claim 1, it is characterized in that: the audio input interface A-in in described audio detection circuit connects 5 pin of potentiometer RW1 to integrated package U1 through R3 ground connection; Power supply 12V through 3,9 pin of U1 to electric capacity C1 ground connection; 6 pin of integrated package U1,7 pin are through resistance R2, R1 ground connection, and 8 pin of integrated package U1 are through R1 ground connection, and 6 pin, 7 pin of U1 are connected with 8 pin through R2,2 pin of U1,4 pin ground connection; Power supply 12V through luminous tube D1 ~ D9's and be attached to 10 ~ 18 pin of U1,1 pin of U1 connects 2 pin of photoelectrical coupler U2; Power supply 12V is connected with 1 pin of photoelectrical coupler U2,3 pin respectively through resistance R5, R4, and 4 pin of U2 connect 2 pin of integrated package U3,6 pin.
3. satellite receiver system-halted reset device according to claim 1, is characterized in that: described delay circuit by integrated package U3, potentiometer RW2, resistance R6, electric capacity C2, C3, diode D10 forms, and 2,6 pin of U3 are input, and 3 pin are output; 2 pin of integrated package U3,6 pin connect 4 pin of photoelectrical coupler U2; 4 pin, the 8 foot meridian capacitor C2 of U3 are connected with 2 pin, 6 pin; Power supply 12V connects 4 pin, 8 pin of U3; Diode D10 and potentiometer RW2 are in parallel to be connected with 2 pin of integrated package U3,6 pin again, other end ground connection; 5 pin of U3 connect ground connection after electric capacity C3, and 3 pin of U3 connect 1 pin, 2 pin of integrated package U4, the 1 pin ground connection of U3 through resistance R6,7 pin are empty.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520056692.1U CN204376884U (en) | 2015-01-21 | 2015-01-21 | Satellite receiver system-halted reset device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520056692.1U CN204376884U (en) | 2015-01-21 | 2015-01-21 | Satellite receiver system-halted reset device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204376884U true CN204376884U (en) | 2015-06-03 |
Family
ID=53333060
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520056692.1U Expired - Fee Related CN204376884U (en) | 2015-01-21 | 2015-01-21 | Satellite receiver system-halted reset device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204376884U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106330221A (en) * | 2016-08-30 | 2017-01-11 | 成都云之声科技有限公司 | Crash recovery system for audio frequency receiver |
| CN106330222A (en) * | 2016-08-30 | 2017-01-11 | 成都云之声科技有限公司 | System capable of controlling audio frequency receiver to rapidly recover after crash |
| CN106330227A (en) * | 2016-08-30 | 2017-01-11 | 成都云之声科技有限公司 | Cruising equipment for disconnecting signal during audio frequency receiving |
| CN106357284A (en) * | 2016-08-30 | 2017-01-25 | 成都云之声科技有限公司 | Device capable of guaranteeing smooth receiving of audio signals |
-
2015
- 2015-01-21 CN CN201520056692.1U patent/CN204376884U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106330221A (en) * | 2016-08-30 | 2017-01-11 | 成都云之声科技有限公司 | Crash recovery system for audio frequency receiver |
| CN106330222A (en) * | 2016-08-30 | 2017-01-11 | 成都云之声科技有限公司 | System capable of controlling audio frequency receiver to rapidly recover after crash |
| CN106330227A (en) * | 2016-08-30 | 2017-01-11 | 成都云之声科技有限公司 | Cruising equipment for disconnecting signal during audio frequency receiving |
| CN106357284A (en) * | 2016-08-30 | 2017-01-25 | 成都云之声科技有限公司 | Device capable of guaranteeing smooth receiving of audio signals |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN204376884U (en) | Satellite receiver system-halted reset device | |
| CN203537358U (en) | One-key switching circuit | |
| CN102063172B (en) | Forced power off circuit | |
| CN201514611U (en) | Switching circuit of handheld device | |
| CN101431256A (en) | Power-off protection apparatus | |
| CN205453082U (en) | Anti latch circuit based on current detection | |
| CN103885563A (en) | Management circuit for self-powered microprocessor protection device microprocessor | |
| CN203166462U (en) | Protective device for preventing dropping of power supply voltage of microcontroller in electronic cigarette | |
| CN205229961U (en) | Anti breech lock power -off reset circuit of CMOS singlechip | |
| CN203746007U (en) | Microprocessor management circuit for self-powered microprocessor protection device | |
| CN106209050A (en) | A kind of electronic switching circuit of low cost low-power consumption | |
| CN204858521U (en) | Cross undervoltage protection switch from double entry | |
| CN104914966A (en) | Single-chip microcomputer self-outage restarting circuit | |
| CN203536944U (en) | A cell phone waterproof protection circuit | |
| CN203965830U (en) | A kind of controlling hard switch machine system | |
| CN206099334U (en) | Prevent reverse -connection protective circuit with cross brown -out detection | |
| CN206559505U (en) | Television set USB power source management system | |
| CN202633902U (en) | Power failure protecting circuit for television set | |
| CN206962424U (en) | USB interface protection circuit | |
| CN203397430U (en) | Circuit breaker for prepaid electricity meter | |
| CN202887168U (en) | Watchdog circuit suitable for unattended operation device | |
| CN206611397U (en) | A kind of delayed management circuit | |
| CN210745101U (en) | Power supply control circuit | |
| CN207937526U (en) | Power-fail detection circuit on charging pile | |
| CN111641406A (en) | Power-off restart automatic control circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150603 Termination date: 20160121 |
|
| EXPY | Termination of patent right or utility model |