CN101330077B - 层叠半导体封装及其制造方法 - Google Patents

层叠半导体封装及其制造方法 Download PDF

Info

Publication number
CN101330077B
CN101330077B CN2007101802071A CN200710180207A CN101330077B CN 101330077 B CN101330077 B CN 101330077B CN 2007101802071 A CN2007101802071 A CN 2007101802071A CN 200710180207 A CN200710180207 A CN 200710180207A CN 101330077 B CN101330077 B CN 101330077B
Authority
CN
China
Prior art keywords
semiconductor chip
hole
conductive
semiconductor
growth layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2007101802071A
Other languages
English (en)
Other versions
CN101330077A (zh
Inventor
金圣敏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of CN101330077A publication Critical patent/CN101330077A/zh
Application granted granted Critical
Publication of CN101330077B publication Critical patent/CN101330077B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05551—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13009—Bump connector integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/9202—Forming additional connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01076—Osmium [Os]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

本发明公开了一种层叠半导体封装及其制造方法。该制造层叠半导体封装的方法包括：准备形成有金属种子层的基板；将具有相互对准的通孔的半导体芯片层压在该金属种子层上，以形成半导体芯片模块；以及利用金属种子层在通孔的内部生长导电层，以在通孔的内部形成导电生长层。

Description

层叠半导体封装及其制造方法
技术领域
本发明涉及一种层叠半导体封装及其制造方法。
背景技术
近年来，半导体器件的发展使其可以储存大量的数据，并且可以在很短的时间内处理所存储的数据。
通常，半导体封装是通过半导体芯片制造工艺来制造的，其中例如晶体管、电阻器、电容器等的半导体器件集成在形成于晶片上的半导体芯片上。然后进行封装工艺，其中半导体芯片与晶片上分离，电连接到外部电路板，并被封装以保护极易碎的半导体芯片不受外部施加的冲击和振动的影响。
近年来，由于封装工艺的技术发展，已经发展出一种芯片级封装(chipscale package)，其尺寸不超过半导体芯片尺寸的100％到105％；以及一种层叠半导体封装，其中层叠了多个半导体芯片，从而增强了数据存储容量和数据处理速度。
这些封装中，层叠半导体封装具有一种结构，其中层叠的半导体芯片通过导体相互连接，这些导体是用于该多个层叠半导体芯片之间的信号输入/输出。
常规的层叠半导体封装中，为了将层叠的半导体芯片互连，形成有半导体芯片的每个半导体芯片或晶片均形成有通孔(via hole)，且通孔中填充导电材料，从而形成连通上、下半导体芯片的导体。
带有填充导体的通孔的半导体芯片或晶片被层叠，从而制成层叠半导体封装，其中半导体芯片的导体相互电连接。
然而，为了制造上述的常规层叠半导体封装，每一个半导体芯片或晶片内都应形成该导体，这就引入了复杂的制造工艺。
此外，常规的层叠半导体封装经常遭受层叠半导体芯片之间不良电连接的问题。
发明内容
本发明的实施例涉及一种层叠半导体封装，其简化了制造工艺，并且防止连接上、下半导体芯片的导体之间出现不良电连接。
进一步地，本发明的实施例涉及一种制造层叠半导体封装的方法，其简化了制造工艺，并且防止连接上、下半导体芯片的导体之间出现不良电连接。
在一个实施例中，层叠半导体封装可以包括：半导体芯片模块，具有形成有相互对准的通孔的层叠半导体芯片；以及导电生长层，置于对准的通孔内部并沿着通孔生长。
一对相邻的半导体芯片之间具有用以粘附半导体芯片的粘附组件(attachment member)。
导电生长层是电镀层。
每一个半导体芯片包含：凹槽部(recess part)，形成于与通孔对应的位置上；以及导电焊垫，形成于该凹槽部的底面上，其中该通孔的尺寸小于该导电焊垫的尺寸。导电生长层与该凹槽部对应的侧表面包括扩展部，该扩展部生长到该凹槽部并与该导电焊垫相连。
导电生长层凸出到半导体芯片模块的上表面。
层叠半导体封装可以进一步包括其上安装有半导体芯片模块的基板主体、置于基板主体上并与半导体芯片模块电连接的连接焊垫、和置于基板主体上并与导体电连接的球形焊盘。
层叠半导体封装可以进一步包括用来覆盖半导体芯片模块的模制组件。
导电生长层与连接焊垫电连接，并且连接焊垫置于与导电生长层相同的位置。
在另一个实施例中，一种制造层叠半导体封装的方法可以包括：准备形成有金属种子层的基板；将具有相互对准的通孔的半导体芯片层压在金属种子层上以形成半导体芯片模块；以及利用金属种子层在通孔内生长导电层，从而形成通孔内的导电生长层。
形成半导体芯片模块的步骤包括：将具有第一通孔的第一半导体芯片置于金属种子层上；以及将具有与第一通孔对准的第二通孔的第二半导体芯片粘附在第一半导体芯片上。
将第一半导体芯片置于金属种子层上的步骤包括：在第一半导体芯片的表面上形成预通孔(preliminary via hole)，其深度小于第一半导体芯片的厚度；将第一半导体芯片置于金属种子层上，使得预通孔与金属种子层相对；以及减少第一半导体芯片的厚度以形成露出金属种子层的第一通孔。
减少第一半导体芯片的厚度的步骤中，通过抛光工艺减少第一半导体芯片的厚度。
形成半导体芯片模块的步骤可以进一步包括：在将第一半导体芯片置于金属种子层上的步骤之前，在第一半导体芯片的对应于预通孔的表面部分内形成凹槽部；并且在凹槽部的底面上形成焊垫。
将第二半导体芯片置于第一半导体芯片上的步骤包括：在第二半导体芯片表面上形成预通孔，其深度小于第一半导体芯片的厚度；将第二半导体芯片置于第一半导体芯片上，使得第二半导体芯片的表面与第一通孔相对；以及减少第二半导体芯片的厚度以形成露出第一通孔的第二通孔。
在减少第二半导体芯片的厚度的步骤中，可以通过抛光工艺或刻蚀工艺中的任何一种来减少第二半导体芯片的厚度。
形成半导体芯片模块的步骤可以进一步包括：在将具有第二通孔的第二半导体芯片置于第一半导体芯片上的步骤之前，在第二半导体芯片的对应于预通孔的表面部分内形成凹槽部；以及在凹槽部的底面上形成焊垫。
在形成导电生长层的步骤中，导电生长层通过电镀来生长。
在形成导电生长层的步骤中，导电生长层凸出到半导体芯片模块的上部。
该方法可以进一步包括：在形成导电生长层的步骤之后，将基板与半导体芯片模块分离；将半导体芯片模块安装在具有连接焊垫的电路基板上；以及用模制组件来模制半导体芯片模块。
附图说明
图1为示出了依据本发明的实施例的层叠半导体封装的剖面图。
图2是图1中“A”部分的放大视图。
图3至12是示出依据本发明的一个实施例的用于制造层叠半导体封装的方法的工艺步骤的剖面图。
图13为示出依据本发明的另一个实施例的层叠半导体封装的剖面图。
图14至17是示出依据本发明的另一个实施例的用于制造层叠半导体封装的方法的工艺步骤的剖面图。
具体实施方式
图1为示出依据本发明的实施例的层叠半导体封装的剖面图。图2是图1中“A”部分的放大视图。
参照图1，层叠半导体封装100包括半导体芯片模块200和导电生长层300。此外，层叠半导体封装100可以进一步包括基础基板(base substrate)400和模制组件500。
基础基板400支撑着半导体芯片模块200。基础基板400包括基板主体410、连接焊垫420、球形焊盘430和焊球440。
举例来说，基板主体410具有矩形板的形状。基板主体410具有其上安装有半导体芯片模块200的第一表面412，以及与第一表面412相对的第二表面414。基板主体410可以具有包括多个层的电路图案，以及用于将置于不同层内的电路图案相互电连接的通路。
连接焊垫420置于基板主体410的第一表面412上。
球形焊盘430通过电路图案和通路和置于基板主体410的第一表面412上的连接焊垫420电连接。
焊球440电连接到球形焊盘430，且焊球440也电连接到外部电路板的连接端子。
半导体芯片模块200置于基础基板400的基板主体410的第一表面412上。
半导体芯片模块200包括多个半导体芯片。在本发明的实施例中，例如，半导体芯片模块200包括第一半导体芯片210、第二半导体芯片220、第三半导体芯片230和第四半导体芯片240。尽管在图1中只描述和图示出四个半导体芯片210、220、230和240，半导体芯片模块200可以与此不同，包括至少两个半导体芯片。
设于半导体芯片模块200中的第一至第四半导体芯片210、220、230和240的每一个包含至少一个通孔。
在下文中，形成于第一半导体芯片210内的通孔称为第一通孔215，形成于第二半导体芯片220内的通孔称为第二通孔225，形成于第三半导体芯片230内的通孔称为第三通孔235，形成于第四半导体芯片240内的通孔称为第四通孔245。
在本发明的实施例中，形成于第一到第四半导体芯片210、220、230和240内的第一到第四通孔215、225、235和245分别相互对准，因而第一到第四通孔215、225、235和245相互连通。
参照图2，分别具有第一到第四通孔215、225、235和245的第一到第四半导体芯片210、220、230和240通过粘附组件250相互粘合。
例如，粘附组件250分别夹置于第一和第二半导体芯片210和220之间、第二和第三半导体芯片220和230之间、以及第三和第四半导体芯片230和240之间。
再参照图1，导电生长层300置于相互连通的第一到第四通孔215、225、235和245的内部。
在本发明的实施例中，导电生长层300沿着相互连通的第一到第四通孔生长，因而一层导电生长层300置于第一到第四通孔215、225、235和245的内部。
对于在第一到第四通孔215、225、235和245的内部形成一层导电生长层300的情况，由于不需要在第一到第四半导体芯片210、220、230和240内分别形成导体，显著地简化了制造工艺。
进一步地说，对于在第一到第四通孔215、225、235和245的内部形成一层导电生长层300的情况，第一到第四通孔215、225、235和245通过该一层导电生长层300而电连接，因此不会出现第一到第四半导体芯片210、220、230和240之间的不良电连接。
置于第一到第四通孔215、225、235和245内的导电生长层300的端部可以从半导体芯片模块200中的半导体芯片240凸出一定高度，该半导体芯片模块200由第一到第四半导体芯片210、220、230和240组成。从第四半导体芯片240凸出的导电生长层300的端部作为连接端子。
模制组件500覆盖置于基础基板400的第一表面412上的半导体芯片模块200。模制组件500防止外部撞击和/或震动对半导体芯片模块200造成损害。可以用作模制组件500的示例材料包括环氧树脂。
图3至12是示出依据本发明的实施例的用于制造层叠半导体封装的方法的工艺步骤的剖面图。
参照图3，为了制造层叠半导体封装，先准备形成有金属种子层265的基板260。基板260的尺寸优选地至少大于层叠半导体封装的尺寸。基板260可以由金属或非金属材料制成。
金属种子层265形成于基板260的表面上。金属种子层265可以通过溅射工艺、化学气相沉积工艺、电镀工艺或化学镀工艺等形成于基板260的表面上。例如，若基板260由金属制成，金属种子层265可以通过溅射工艺或电镀工艺形成。相反，如果基板260由非金属材料制成，金属种子层265可以通过溅射工艺或化学镀工艺制备。可以用作金属种子层265的金属的示例包括：钛、镍、钒、铜、铝、铝合金、钨、钨合金、铬、铬合金、银、金等。
参照图4，半导体芯片模块200形成于基板260的金属种子层265上。
为了制造半导体芯片模块200，具有第一通孔215的第一半导体芯片210置于金属种子层265上。然后，具有第二通孔225的第二半导体芯片220置于第一半导体芯片210上。
接下来，具有第三通孔235的第三半导体芯片230置于第二半导体芯片220上。然后，具有第四通孔245的第四半导体芯片240置于第三半导体芯片230上。
第一到第四通孔215、225、235和245相互对准，且因此金属种子层265由于第一到第四通孔215、225、235和245而露出。
下文参照图3及图5至10，描述用于在金属种子层上形成半导体芯片模块200的方法。
参照图5，准备第一半导体芯片210，用于形成半导体芯片模块200。
参照图6，在第一半导体芯片210的表面上形成预通孔213。预通孔213可以用钻孔、激光钻孔、刻蚀工艺等从第一半导体芯片210的表面形成。预通孔213的深度小于第一半导体芯片210的厚度。
参照图7，具有预通孔213的第一半导体芯片的一个表面相对放置在图3所示的基板260的金属种子层265上，且第一半导体芯片210的这个表面固定在金属种子层265上。例如，金属种子层265和预通孔213可以用粘附组件相互粘附。
参照图8，在具有预通孔213的第一半导体芯片210固定到金属种子层265上以后，实施减少第一半导体芯片210的厚度以形成第一通孔215的工艺。
在本发明的实施例中，为了减少第一半导体芯片210的厚度以形成第一通孔215，可以实施抛光工艺，其中通过化学机械抛光(CMP)工艺抛光与第一半导体芯片210这个表面相对的另一表面。备选地，为了减少第一半导体芯片210的厚度以形成第一通孔215，可以实施刻蚀工艺，其中使用刻蚀剂来蚀刻第一半导体芯片210的另一表面。
参照图9，具有预通孔223的第二半导体芯片220再次置于具有第一通孔215的第一半导体芯片210上。第二半导体芯片220上的预通孔223的深度小于第二半导体芯片220的厚度。
形成有预通孔223的第二半导体芯片220的表面固定到第一半导体芯片210上。第二半导体芯片220和第一半导体芯片210可以通过粘附组件相互粘附。
第二半导体芯片220固定到第一半导体芯片210上时，第一半导体芯片210的第一通孔215和第二半导体芯片220的预通孔223相互精确对准。
参考图10，第一通孔215和预通孔223对齐后，第二半导体芯片220具有预通孔223的相对表面被抛光或蚀刻，直至预通孔223暴露出来，且因此第二通孔225形成于第二半导体芯片220内。
重复从图5到图10所示的工艺，从而如图4所示在金属种子层265上形成分别具有第一到第四通孔215、225、235和245的第一到第四半导体芯片210、220、230和240。此时，第一到第四通孔215、225、235和245相互对准，且半导体芯片模块200形成于金属种子层265上。
参照图11，半导体芯片模块200形成于金属种子层265上之后，利用金属种子层265，导电生长层300形成于第一到第四通孔215、225、235和245内。导电生长层300可以通过例如电镀形成于第一到第四通孔215、225、235和245的内部。
导电生长层300从金属种子层265连续地生长在第一到第四通孔215、225、235和245的内部，并且填充第一到第四通孔215、225、235和245。此外，导电生长层300生长，使得其端部凸出到第四通孔245的外部。
由于一层导电生长层300生长在第一到第四通孔215、225、235和245的内部，制造工艺显著简化。
进一步地说，对于一层导电生长层300生长于第一到第四通孔215、225、235和245的内部的情况，第一到第四通孔215、225、235和245通过这一层导电生长层300相互连接，因此不会出现第一块到第四半导体芯片210、220、230和240之间的不良电连接。
参照图12，在导电生长层300生长于第一到第四通孔215、225、235和245的内部从而填充第一到第四通孔215、225、235和245之后，金属种子层265和基板260从半导体芯片模块200分离。
随后，从形成于半导体芯片模块200的第四半导体芯片240内的第四通孔245凸出的导电生长层300电连接到形成于基础基板400的第一表面412上的连接焊垫420。球形焊盘430形成于与第一表面412相对的第二表面414上，且焊球440形成于球形焊盘430上。
随后，如图1所示，用模制组件500覆盖半导体芯片模块200和基础基板400，从而制成层叠半导体封装100。
图13为示出依据本发明的另一个实施例的层叠半导体封装的剖面图。
参照图13，层叠半导体封装600包括半导体芯片模块700和导电生长层800。此外，层叠半导体封装600可进一步包括基础基板400和模制组件500。
半导体芯片模块600支撑在基础基板400上。
基板主体410基本上具有矩形板的形状。基板主体410具有第一表面412和第二表面414，并且第一表面412和第二表面彼此相对。基板主体410可以包含电路图案和将电路图案相互电连接的通孔。电路图案可以由通过通路相互连接的多个层组成。
连接焊垫420置于基板主体410的第一表面412上，而且球形焊盘430通过电路图案和通孔导通而电连接到置于基板主体410的第一表面412上的连接焊垫420。
焊球440电连接到球形焊盘430，且焊球440也电连接到外部电路板的连接端子。
半导体芯片模块700置于基础基板400的基板主体410的第一表面412上。
半导体芯片模块700包括多个半导体芯片。在本发明的另一个实施例中，半导体芯片模块700包括第一半导体芯片710、第二半导体芯片720、第三半导体芯片730和第四半导体芯片740。
设于半导体芯片模块700中的第一到第四半导体芯片710、720、730和740的每一个包括至少一个通孔。在下文中，形成于第一半导体芯片710内的通孔称为第一通孔715，形成于第二半导体芯片720内的通孔称为第二通孔725，形成于第三半导体芯片730内的通孔称为第三通孔735，且形成于第四半导体芯片740内的通孔称为第四通孔745。
在本发明的另一个实施例中，分别形成于第一到第四半导体芯片710、720、730和740内的第一到第四通孔715、725、735和745相互对准，且因而第一到第四通孔715、725、735和745相互连通。
分别具有第一到第四通孔715、725、735和745的第一到第四半导体芯片710、720、730和740通过粘附组件(未示出)相互粘合。例如，粘附组件分别夹置于第一和第二半导体芯片710和720之间、第二和第三半导体芯片720和730之间、以及第三和第四半导体芯片730和740之间。
同时，在第一到第四半导体芯片710、720、730和740上分别形成第一到第四通孔715、725、735和745的各个位置形成第一到第四凹槽部717、727、737和747。
第一到第四凹槽部717、727、737和747形成为尺寸大于第一到第四通孔715、725、735和745的尺寸。第一到第四焊垫719、729、739和749分别形成于第一到第四凹槽部717、727、737和747上。
穿过第一到第四焊垫719、729、739和749的第一到第四通孔715、725、735和745形成于第一到第四凹槽部717、727、737和747上及第一到第四凹槽部717、727、737和747的中心。
导电生长层800置于相互连通的第一到第四通孔715、725、735和745的内部。此外，导电生长层800生长到由第一到第四凹槽部717、727、737和747形成的空间中，且因此扩展部716、726、736和746置于由第一到第四凹槽部717、727、737和747形成的空间中。
在本发明的另一个实施例中，导电生长层800沿着相互连通的第一到第四通孔生长，且因此一层导电生长层800置于第一到第四通孔715、725、735和745的内部。
对于在第一到第四通孔715、725、735和745的内部形成一层导电生长层800的情况，由于不需要分别在第一到第四半导体芯片710、720、730和740内形成导体，显著地简化了制造工艺。
进一步地说，对于在第一到第四通孔715、725、735和745的内部形成一层导电生长层800的情况，第一到第四通孔715、725、735和745通过这一层导电生长层800而电连接，且因此不会出现第一到第四半导体芯片710、720、730和740之间的不良电连接。
置于第一到第四通孔715、725、735和745内的导电生长层800的端部可以从半导体芯片模块600的第四半导体芯片740凸出，该半导体芯片模块600由第一到第四半导体芯片710、720、730和740组成。从第四半导体芯片740凸出的导电生长层800的端部作为连接端子。
模制组件500覆盖置于基础基板400的第一表面412上的半导体芯片模块600。模制组件500防止外部撞击和/或震动对半导体芯片模块600造成损害。可以用作模制组件500的示例材料包括环氧树脂。
图3以及图14至17是示出依据本发明的另一实施例的用于制造层叠半导体封装的方法的工艺步骤的剖面图。
参照图14，为了制造层叠半导体封装，准备如图3所示的形成有金属种子层265的基板260。基板260的尺寸优选地至少大于层叠半导体封装的尺寸。基板260可以由金属或非金属材料制成。
金属种子层265形成于基板260的表面上。金属种子层265可以通过溅射工艺、电镀工艺或化学镀工艺等形成于基板260的表面上。例如，对于基板260由金属制成的情况，金属种子层265可以通过溅射工艺或电镀工艺形成。相反，对于基板260由非金属材料制成的情况，金属种子层265可以通过溅射工艺或化学镀工艺形成。可以用作金属种子层265的材料示例包括钛、镍、钒、铜、铝、铝合金、钨、钨合金、铬、铬合金、银、金等。
参照图14，为了在金属种子层265上形成半导体芯片模块700，准备第一半导体芯片710。
参照图15，在第一半导体芯片710上将要形成稍后描述的第一通孔的部分形成凹槽部717。凹槽部717可以通过光刻工艺形成。形成凹槽部717后，与第一半导体芯片710相连接的第一焊垫719形成于凹槽部717的底面上。
参照图16，第一通孔715形成于第一半导体芯片710的表面上。第一通孔715可以通过钻孔或激光钻孔工艺形成。
参照图17，基本上和第一半导体芯片710具有相同结构的第二半导体芯片720、第三半导体芯片730和第四半导体芯片740相继置于金属种子层265上。在本发明的另一实施例中，由第二凹槽部727在第一半导体芯片710和第二半导体芯片720之间形成一空间。此外，由第三凹槽部737在第二半导体芯片720和第三半导体芯片730之间也形成一空间，且由第四凹槽部747在第三半导体芯片730和第四半导体芯片740之间也形成一空间。
再次参考图13，在半导体芯片模块700形成于金属种子层265上之后，利用金属种子层265，导电生长层800形成于第一到第四通孔715、725、735和745内。导电生长层800可以通过例如电镀形成于第一到第四通孔715、725、735和745的内部。
导电生长层800从金属种子层265连续地生长于第一到第四通孔715、725、735和745的内部，并填充第一到第四通孔715、725、735和745。此外，导电生长层800生长使得其端部凸出到第四通孔745的外部。
对于在第一到第四通孔715、725、735和745的内部生长一层导电生长层800的情况，由于不需要在第一到第四半导体芯片710、720、730和740内分别形成导体，显著简化了制造工艺。
进一步地说，对于在第一到第四通孔715、725、735和745的内部生长一层导电生长层800的情况，第一到第四通孔715、725、735和745通过这一层导电生长层800而相互连接，且因此不会出现第一到第四半导体芯片710、720、730和740之间的不良电连接。
在导电生长层800生长于第一到第四通孔715、725、735和745的内部以填充第一到第四通孔715、725、735和745之后，金属种子层265和基板260从半导体芯片模块700分离。
随后，从半导体芯片模块700中的第四半导体芯片740内形成的第四通孔745凸出的导电生长层800电连接到形成于基础基板400的第一表面412上的连接焊垫420。球形焊盘430形成于与第一表面412相对的第二表面414上，焊球440形成于球形焊盘430上。
随后，用模制组件500覆盖半导体芯片模块700和基础基板400，从而制成层叠半导体封装600。
从上文描述显见，在本发明的实施例中，用于制造层叠半导体封装的工艺得到显著地简化，同时能够解决构成层叠半导体封装的半导体芯片之间的不良电连接。
尽管为了举例说明描述了本发明的具体实施例，本领域技术员将会理解，在不背离在权利要求书中披露的本发明的范围和精神的情况下可以进行各种修正、添加和替换。
本申请主张于2007年6月21目提交的韩国专利申请No.10-2007-0061246的优先权，其全部内容引用结合于此。

Claims (17)

1.一种层叠半导体封装，包括：
半导体芯片模块，具有形成有相互对准的通孔的多个层叠半导体芯片；以及
导电生长层，置于该对准的通孔的内部并且沿着该通孔生长；
其中每一个半导体芯片包括：形成于该通孔所对应的部分的凹槽部以及形成于该凹槽部的底面上的导电焊垫，并且其中该通孔的尺寸小于该导电焊垫的尺寸。
2.根据权利要求1的层叠半导体体封装，其中在一对相邻的半导体芯片之间具有用以粘附该对半导体芯片的粘附组件。
3.根据权利要求1的层叠半导体封装，其中该导电生长层是电镀层。
4.根据权利要求1的层叠半导体封装，其中与该凹槽部对应的该导电生长层的侧表面包括一扩展部，该扩展部生长到该凹槽部并与该导电焊垫连接。
5.根据权利要求1的层叠半导体封装，其中该导电生长层凸出到该半导体芯片模块的上表面。
6.根据权利要求1的层叠半导体封装，还包括：
基板主体，其上安装有该半导体芯片模块；
连接焊垫，置于该基板主体上并与该半导体芯片模块电连接；以及
球形焊盘，置于该基板主体上并与焊球电连接。
7.根据权利要求6的层叠半导体封装，还包括用于覆盖该半导体芯片模块的模制组件。
8.根据权利要求6的层叠半导体封装，其中该导电生长层与该连接焊垫电连接。
9.根据权利要求8的层叠半导体封装，其中该连接焊垫置于和该导电生长层相同的位置。
10.一种制造层叠半导体封装的方法，包括步骤：
准备形成有金属种子层的基板；
将具有相互对准的通孔的半导体芯片层压在该金属种子层上，以形成半导体芯片模块；以及
利用该金属种子层在该通孔的内部生长导电层，以在该通孔的内部形成导电生长层；
其中形成每一个半导体芯片包括：于该通孔所对应的部分形成凹槽部，以及于该凹槽部的底面上形成导电焊垫，并且其中该通孔的尺寸小于该导电焊垫的尺寸。
11.根据权利要求10的方法，其中形成该半导体芯片模块的步骤包括步骤：
将具有第一通孔的第一半导体芯片置于该金属种子层上；以及
将具有与该第一通孔对准的第二通孔的第二半导体芯片粘附在该第一半导体芯片上。
12.根据权利要求11的方法，其中将该第一半导体芯片置于该金属种子层上的步骤包括步骤：
在该第一半导体芯片的表面上形成预通孔，其深度小于该第一半导体芯片的厚度；
将该第一半导体芯片置于该金属种子层上，使得该预通孔与该金属种子层相对；以及
减少该第一半导体芯片的厚度，以形成露出该金属种子层的第一通孔。
13.根据权利要求11的方法，其中将该第二半导体芯片置于该第一半导体芯片上的步骤包括步骤：
在该第二半导体芯片的表面上形成预通孔，其深度小于该第二半导体芯片的厚度；
将该第二半导体芯片置于该第一半导体芯片上，使得该第二半导体芯片的该预通孔与该第一通孔相对；以及
减少该第二半导体芯片的厚度，以形成露出该第一通孔的第二通孔。
14.根据权利要求13的方法，其中在减少该第二半导体芯片的厚度的步骤中，该第二半导体芯片的厚度通过抛光工艺或刻蚀工艺中的任何一种来减少。
15.根据权利要求10的方法，其中在形成该导电生长层的步骤中，该导电生长层通过电镀来生长。
16.根据权利要求10的方法，其中在形成该导电生长层的步骤中，该导电生长层凸出到该半导体芯片模块的上部。
17.根据权利要求10的方法，进一步包括，在形成该导电生长层的步骤之后的下述步骤：
将该基板从该半导体芯片模块分离；
将该半导体芯片模块安装到具有连接焊垫的电路基板上；以及
用模制组件来模制该半导体芯片模块。
CN2007101802071A 2007-06-21 2007-10-11 层叠半导体封装及其制造方法 Expired - Fee Related CN101330077B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020070061246A KR100920039B1 (ko) 2007-06-21 2007-06-21 적층형 반도체 패키지 및 이의 제조 방법
KR61246/07 2007-06-21

Publications (2)

Publication Number Publication Date
CN101330077A CN101330077A (zh) 2008-12-24
CN101330077B true CN101330077B (zh) 2010-06-16

Family

ID=40135620

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2007101802071A Expired - Fee Related CN101330077B (zh) 2007-06-21 2007-10-11 层叠半导体封装及其制造方法

Country Status (3)

Country Link
US (2) US7858439B2 (zh)
KR (1) KR100920039B1 (zh)
CN (1) CN101330077B (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090115042A1 (en) * 2004-06-04 2009-05-07 Zycube Co., Ltd. Semiconductor device having three-dimensional stacked structure and method of fabricating the same
KR100907896B1 (ko) * 2007-06-22 2009-07-14 주식회사 동부하이텍 시스템 인 패키지의 금속 전극 형성방법
KR100959606B1 (ko) * 2008-03-12 2010-05-27 주식회사 하이닉스반도체 스택 패키지 및 그의 제조 방법
US8900921B2 (en) * 2008-12-11 2014-12-02 Stats Chippac, Ltd. Semiconductor device and method of forming topside and bottom-side interconnect structures around core die with TSV
CN101872757B (zh) * 2009-04-24 2012-05-23 南茂科技股份有限公司 凹穴芯片封装结构及使用其的层叠封装结构
JP2012221998A (ja) * 2011-04-04 2012-11-12 Toshiba Corp 半導体装置ならびにその製造方法
US8970046B2 (en) 2011-07-18 2015-03-03 Samsung Electronics Co., Ltd. Semiconductor packages and methods of forming the same
US9214435B2 (en) * 2012-05-21 2015-12-15 Globalfoundries Inc. Via structure for three-dimensional circuit integration
US10235686B2 (en) 2014-10-30 2019-03-19 Microsoft Technology Licensing, Llc System forecasting and improvement using mean field

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5481133A (en) * 1994-03-21 1996-01-02 United Microelectronics Corporation Three-dimensional multichip package
US6577013B1 (en) * 2000-09-05 2003-06-10 Amkor Technology, Inc. Chip size semiconductor packages with stacked dies
CN1553490A (zh) * 2003-05-29 2004-12-08 ���ŷ��˹�ҵ�����о�Ժ 三维堆叠的电子封装件及其组装方法
CN1655333A (zh) * 2004-02-13 2005-08-17 旺宏电子股份有限公司 多芯片封装结构
CN1744315A (zh) * 2004-08-31 2006-03-08 精工爱普生株式会社 半导体装置的制造方法及半导体装置

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4897708A (en) * 1986-07-17 1990-01-30 Laser Dynamics, Inc. Semiconductor wafer array
KR100271639B1 (ko) * 1997-12-23 2000-11-15 김영환 적층형 반도체패키지 및 그 제조방법 및 그 적층방법
KR100364635B1 (ko) * 2001-02-09 2002-12-16 삼성전자 주식회사 칩-레벨에 형성된 칩 선택용 패드를 포함하는 칩-레벨3차원 멀티-칩 패키지 및 그 제조 방법
KR100435813B1 (ko) * 2001-12-06 2004-06-12 삼성전자주식회사 금속 바를 이용하는 멀티 칩 패키지와 그 제조 방법
KR20030050665A (ko) * 2001-12-19 2003-06-25 삼성전자주식회사 적층 칩 패키지와 그 제조 방법
JP4248928B2 (ja) * 2003-05-13 2009-04-02 ローム株式会社 半導体チップの製造方法、半導体装置の製造方法、半導体チップ、および半導体装置
US7232754B2 (en) * 2004-06-29 2007-06-19 Micron Technology, Inc. Microelectronic devices and methods for forming interconnects in microelectronic devices
US7217995B2 (en) * 2004-11-12 2007-05-15 Macronix International Co., Ltd. Apparatus for stacking electrical components using insulated and interconnecting via
US7462925B2 (en) * 2004-11-12 2008-12-09 Macronix International Co., Ltd. Method and apparatus for stacking electrical components using via to provide interconnection
KR20060068201A (ko) * 2004-12-16 2006-06-21 주식회사 하이닉스반도체 웨이퍼 레벨 패키지의 제조방법
JP4551321B2 (ja) * 2005-07-21 2010-09-29 新光電気工業株式会社 電子部品実装構造及びその製造方法
US7446018B2 (en) * 2005-08-22 2008-11-04 Icemos Technology Corporation Bonded-wafer superjunction semiconductor device
JP4753725B2 (ja) * 2006-01-20 2011-08-24 エルピーダメモリ株式会社 積層型半導体装置
KR100845006B1 (ko) * 2007-03-19 2008-07-09 삼성전자주식회사 적층 칩 패키지 및 그 제조 방법
TWI362102B (en) * 2007-07-11 2012-04-11 Ind Tech Res Inst Three-dimensional dice-stacking package structure and method for manufactruing the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5481133A (en) * 1994-03-21 1996-01-02 United Microelectronics Corporation Three-dimensional multichip package
US6577013B1 (en) * 2000-09-05 2003-06-10 Amkor Technology, Inc. Chip size semiconductor packages with stacked dies
CN1553490A (zh) * 2003-05-29 2004-12-08 ���ŷ��˹�ҵ�����о�Ժ 三维堆叠的电子封装件及其组装方法
CN1655333A (zh) * 2004-02-13 2005-08-17 旺宏电子股份有限公司 多芯片封装结构
CN1744315A (zh) * 2004-08-31 2006-03-08 精工爱普生株式会社 半导体装置的制造方法及半导体装置

Also Published As

Publication number Publication date
KR20080112627A (ko) 2008-12-26
US8067839B2 (en) 2011-11-29
US7858439B2 (en) 2010-12-28
US20080315395A1 (en) 2008-12-25
CN101330077A (zh) 2008-12-24
KR100920039B1 (ko) 2009-10-07
US20110024893A1 (en) 2011-02-03

Similar Documents

Publication Publication Date Title
CN101330077B (zh) 层叠半导体封装及其制造方法
US9685400B2 (en) Semiconductor package and method of forming the same
US9899298B2 (en) Microelectronic packages having mold-embedded traces and methods for the production thereof
US9070691B2 (en) Semiconductor package and stacked semiconductor package having the same
US8022555B2 (en) Semiconductor package and method of forming the same
US7205646B2 (en) Electronic device and chip package
US9331029B2 (en) Microelectronic packages having mold-embedded traces and methods for the production thereof
US7446424B2 (en) Interconnect structure for semiconductor package
JP4580671B2 (ja) 半導体装置
US20080318361A1 (en) Method for manufacturing semiconductor package
US20070246837A1 (en) IC chip package with minimized packaged-volume
CN110034106A (zh) 封装结构及其制造方法
EP3104410B1 (en) Multi-chip module, on-board computer, sensor interface substrate, and multi-chip module manufacturing method
US8361857B2 (en) Semiconductor device having a simplified stack and method for manufacturing thereof
US7067907B2 (en) Semiconductor package having angulated interconnect surfaces
KR101013560B1 (ko) 적층 반도체 패키지 및 이의 제조 방법
CN102126697B (zh) 具有微机电元件的封装结构及其制造方法
JP4801133B2 (ja) 半導体装置
US9966364B2 (en) Semiconductor package and method for fabricating the same

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20100616

Termination date: 20131011