CN101321119B - System and method for implementing data bit exchange - Google Patents
System and method for implementing data bit exchange Download PDFInfo
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Abstract
The invention discloses a system of realizing data bit exchange, comprising a communicated processor (CPU) and a programmable logic device (FRGA); wherein, CPU is used for configuring FPGA; FPGA is used for obtaining the input data and outputting the input data after bit exchange according to the configuration of CPU. The invention further discloses a method of realizing the data bit exchange. Adopting the system and method in the invention tessellates to exchange the data according to bit and realizes the function of executing non-blocking exchange according to the bit in time slot; the invention is able to output any input bit on the appointed position of all needed outputting channel, which not only improves the flexibility of the data exchange, but also decreases the cost and has high cost performance.
Description
Technical field
The present invention relates to the Data Interchange Technology in the communication system, relate in particular to a kind of system and method for realizing the data bit exchange.
Background technology
In gsm communication system, along with increasing rapidly of user, brought the rapid expanding of communication network scale, if things go on like this, will certainly cause the not smooth problem of communication network; Simultaneously, in the process that enlarges the communication network scale, follow investment, certainly will relate to the problem of saving cost of investment communication network.For addressing the above problem, the existing communication network using half-rate speech communication technology not only can effectively solve the communication network obstruction that the bursts of traffic amount causes, and promotes increasing by on a year-on-year basis of telephone traffic and professional income; And can save the cost of investment of radio carrier frequency, improve resource utilization.The described half-rate speech communication technology comprises two kinds of implementations: a kind of is complete half rate mode, and another kind is dynamic half rate mode.Owing to adopt complete half rate mode can bring some negative effects, speech quality descends to some extent during as conversation, therefore, adopts dynamic half rate mode usually.
So-called dynamically half rate mode refers to: the traffic load according to the sub-district dynamically determines to distribute full speed channel or half-rate channel, that is: in the complete half rate mode only by single time gas exchange or fixedly time slot split data conditions and improve, be improved to: can will import data and dateout exchanges between different passages, time slot and bit according to configuration.Specific implementation in dynamic half rate mode in the gsm communication system is an example, angle from the realization of bottom circuit, dynamically the half rate mode remains unchanged full rate (FR, full rate) data directly to deliver to output port earlier in configurable mode, when the FR channel resource that takies surpasses pre-configured ratio, FR data with remaining split into half rate (HR, halfrate) data, and, the HR data that split are delivered in the time slot of required output port with the order that continues of FR data.
In the previous patent document, realize that the technology of exchanges data all exchanges according to time slot.For example: the Chinese invention patent application number is 200410026307.5, denomination of invention is in the file of " circuit module of realizing the high speed time-division switching ", disclosed for 1 tunnel input-output, the method that exchanges according to time slot, if expand to the multichannel input-output according to the method, because this method based on a kind of specific selection that is input to output, is not considered the influence between the multichannel input-output, therefore, this method can exist and can not carry out the shortcoming broadcasted on time and the space to data.
Chinese invention patent number is 02148368.x, denomination of invention is in the file of " the semipermanent method of attachment of time division multiplexing time slot between a kind of digital cross connect equipment spare ", it is multiplexing and in conjunction with the method for private exchange chip to disclose a kind of employing high-speed synchronous serial data stream (HW) bus, realizes the semifixed connection of time slot.But the realization of this method is subjected to self function of private exchange chip to be limit, and therefore, the shortcoming that this method exists is: can only finish the basic function by the time slot exchange, and cost is higher.
China Patent No. is 98812747.4, and denomination of invention is in the file of " method and apparatus of swap data between the bit stream of time-division multiplexing network ", and the method for time division multiplex network by the time slot exchange is provided.This method need be used maximum three caching frames, and data are uncertain from the time-delay that is input to output, because the restriction of storage mode design, therefore, the shortcoming that this method exists is: specific input time slot data can't exchange to a plurality of output time solts simultaneously.
Summary of the invention
In view of this, main purpose of the present invention is to provide a kind of system that realizes the data bit exchange, has not only improved the flexibility of exchanges data, and has reduced cost, and cost performance is higher.
Another purpose of the present invention is to provide a kind of method that realizes the data bit exchange, can realize clog-free function of exchange, and the bit of any one input is exported on the dedicated tunnel position.
For achieving the above object, technical scheme of the present invention is achieved in that
A kind of system that realizes the data bit exchange, this system comprises: processor CPU and coupled programmable logic device FPGA; Wherein, CPU is used to dispose described FPGA, and the input data that dispose described FPGA are carried out the corresponding relation of bit exchange to dateout;
FPGA is used to obtain the input data, and according to the configuration of described CPU, will import data and carry out exporting after the bit exchange;
Described FPGA comprises: cpu i/f unit, control unit, input data processing unit, contiguous unit, dateout processing unit.
Wherein, the cpu i/f unit links to each other with CPU, is used for finishing data interaction between FPGA and CPU, and preserves the configuration of described CPU to FPGA;
Control unit is used to finish the sequencing control of described FPGA inside, produces and control the required timing control signal in other each unit among the described FPGA; Wherein, timing control signal comprises: synchronizing clock signals, read-write enable signal and read/write address signal;
The input data processing unit links to each other with described cpu i/f unit, is used for according to described timing control signal, realizes reception and buffer memory to described input data, simultaneously, should import data and send to the cpu i/f unit;
Contiguous unit, link to each other with described input data processing unit, described cpu i/f unit, described dateout processing unit, be used for obtaining the described CPU that stores described cpu i/f unit configuration to FPGA, and according to deploy content and mode of operation, reception sends to the dateout processing unit after the data of input data processing unit output;
The dateout processing unit is used for according to described timing control signal, to the data from contiguous unit output receive, buffer memory and output.
Wherein, described cpu i/f unit comprises: data are deposited module, control and are deposited module and continue and deposit module;
Data are deposited module, link to each other with described input data processing unit, are used to receive and store the input data that described input data processing unit sends to described cpu i/f unit;
Module is deposited in control, links to each other with described input data processing unit, is used for the configuration to described FPGA according to described CPU, and when carrying out bit exchange in FPGA, the mode of operation of control FPGA is switched;
Continue and deposit module, link to each other, be used to store described CPU, and the corresponding relation that the input data that disposed are carried out bit exchange to dateout sends to described contiguous unit the FPGA configured corresponding relation with described contiguous unit.
Wherein, described synchronizing clock signals comprises: the synchronization frame clock signal; Described read-write enable signal is specially: the enable signal of read/write dual port random access memory DPRAM; Described read/write address signal is specially: the address signal of read/write DPRAM.
Wherein, under normal mode of operation, contiguous unit receives from the data of described input data processing unit output with continuation method, and sends to the dateout processing unit; Under the self check mode of operation, contiguous unit sends to the dateout processing unit with message mode with the described message digit of depositing in the module's address that continues.
Wherein, described cpu i/f unit under described self check mode of operation, is used to also judge whether described FPGA correctly carries out bit exchange.
A kind of method that realizes the data bit exchange, this method may further comprise the steps:
A, FPGA receive the input data, and CPU disposes FPGA, and will import the corresponding relation that data carry out bit exchange to dateout and dispose to FPGA; Described FPGA is made up of cpu i/f unit, control unit, input data processing unit, dateout processing unit and contiguous unit;
B, FPGA will import data and carry out exporting after the bit exchange according to configured corresponding relation.
Wherein, steps A is specially:
The timing control signal that A1, input data processing unit provide according to control unit to described input Data Receiving and buffer memory, should be imported data forwarding simultaneously and give described cpu i/f unit;
A2, cpu i/f unit dispose described corresponding relation to contiguous unit;
Accordingly, step B is specially:
B1, described contiguous unit receive after the data of described input data processing unit output according to described configured corresponding relation, send to the dateout processing unit;
The described timing control signal that B2, dateout processing unit provide according to described control unit, to the data from contiguous unit output receive, buffer memory and output.
Wherein, described cpu i/f unit is deposited module, control by data and is deposited module and continue and deposit module and form;
Then steps A 1 further is:
A11, described input data processing unit will be imported data forwarding and deposit module to data;
Accordingly, steps A 2 is specially:
A21, continue and deposit module described corresponding relation is disposed to contiguous unit.
Wherein, before steps A 11, also comprise:
Step X, according to the configuration of described CPU to described FPGA, the mode of operation that module controls FPGA is deposited in control is switched.
Wherein, FPGA is in normal mode of operation, and when the read-write operation mode that the input data processing unit adopts was the ping-pong operation mode, steps A 11 was specially:
A111, described input data processing unit adopt the described input data of dual port random access memory DPRAM buffer memory;
And,, first frame of described input data is write the low memory of DPRAM according to the first frame timing control signal that described control unit provides; According to the second frame timing control signal that described control unit provides, second frame of input data is write the high memory block of DPRAM;
A112, when obtaining the described second frame timing control signal, according to described configured corresponding relation, the data of described low memory first frame are read;
Transmission sequence frame by frame, circulation execution in step A111～A112 flow process is until the read-write operation of finishing at the input data processing unit described all frames of input data.
Wherein, among the step B2, described dateout processing unit adopts the DPRAM storage, and the read-write operation mode that the dateout processing unit is adopted is the ping-pong operation mode.
Wherein, deposit in the module described continuing, it is the working mode selection position that arbitrary bit is set.
Wherein, when FPGA switches under the self check mode of operation, then also comprise after the step B2:
B3, the data that the dateout processing unit receives, buffer memory is exported from described contiguous unit according to the Loopback Mode of output, input data, will send to described input data processing unit from the data of dateout processing unit output; Between described CPU and described FPGA, adopt message mode, the data of checking input FPGA are carried out the correctness of bit exchange to output FPGA data.
Wherein, adopt message mode among the step B3, carry out the bit exchange verification of correctness and be specially:
B31, described CPU continue via described cpu i/f unit and deposit module and first via dateout corresponding address space is set to: message mode, and the lowest bit position of described address is write the message of appointment; Other dateout corresponding address spaces, road are set to be undertaken by the configuration corresponding relation continuation method of bit exchange;
B32, contiguous unit send to the dateout processing unit with the described described specify message of depositing message digit in the described address of module that continues;
B33, described CPU read the content that data in the cpu i/f unit are deposited module stores, deposit module and compare with described continuing via the message that contiguous unit sent, if identical, judge that then that these road input data are carried out the bit exchange function exported after the bit exchange is correct; Continue circulation execution in step B31～B33, until each road that has traveled through described dateout.
The system and method for realization data bit exchange provided by the present invention compared with prior art has the following advantages:
(1) owing to CPU programmable logic device (FPGA) is configured, and the content that is disposed is the corresponding relation of input data and dateout.When n * n bar HW imports FPGA, according to described configured corresponding relation, FPGA can be with the content exchange on the appointment bit among the input HW to the designated bit position of exporting among the HW, therefore, the inventive method has realized carrying out according to the bit in the time slot function of clog-free exchange, and can allow the bit of any one input need the designated bit position on the output channel to export at all.
(2) system of the present invention possesses self-checking function, by the configuration effort pattern, finishes the self check of bit exchange function according to the indication of system clock.
(3) system of the present invention adopts message mode, can be used to diagnose the correctness of peripheral circuit or passage.
(4) because FPGA is programmable, so, mode of operation in conjunction with the CPU configuration realizes method of the present invention, can make the user design needs according to self, the software module on the customization FPGA, realize the exchange of 1 bit or many bits easily, therefore, with the main body of FPGA, compare the system that adopts the private exchange chip and data are exchanged according to time slot as system of the present invention, improve the flexibility of exchanges data, had high cost performance.
Description of drawings
Fig. 1 is a composition structural representation of system of the present invention;
Fig. 2 is another composition structural representation of system of the present invention;
Fig. 3 is a realization flow figure of the inventive method;
Fig. 4 realizes the schematic diagram of bit exchange function for the present invention;
Fig. 5 is under the normal mode of operation, one of the inventive method embodiment based on system form structural representation;
Fig. 6 is under the self check mode of operation, two of the inventive method embodiment based on system form structural representation;
Fig. 7 is the system principle schematic diagram that sends message with message mode.
Embodiment
Core concept of the present invention is: the data of CPU configuration input FPGA are to the corresponding relation of the bit exchange that data carry out of output FPGA, and FPGA carries out the data of input FPGA to export FPGA after the bit exchange according to the CPU configured corresponding relation.Because FPGA is programmable, the user can design needs according to self, software module on the customization FPGA, realize bit exchange in conjunction with the CPU configured corresponding relation, therefore, can carry out easily exporting after the exchange of 1 bit or many bits with importing data according to concrete customization, improve the flexibility of exchanges data, had high cost performance.
Be described in further detail below in conjunction with the enforcement of accompanying drawing technical scheme.
As shown in Figure 1, system of the present invention comprises: the CPU1 of interconnection and FPGA2.Wherein, CPU1 is used to dispose FPGA2, and the input data dateout that is further used for disposing FPGA2 is carried out the corresponding relation of bit exchange; FPGA2 is used to obtain the input data, and according to CPU1 institute configured corresponding relation, will import data and carry out exporting after the bit exchange.
FPGA2 further comprises: cpu i/f unit 21, control unit 22, input data processing unit 23, contiguous unit 24, dateout processing unit 25.
Wherein, cpu i/f unit 21 links to each other with CPU1, is used for finishing data interaction between FPGA2 and CPU1, and preserves the configuration of CPU1 to FPGA2.Wherein, data interaction is specially: cpu i/f unit 21 among the FPGA2 and the data interaction between the CPU1.
Control unit 22 is used to finish the sequencing control of FPGA2 inside, produces and control the required timing control signal in other each unit among the FPGA2.Here, said other each unit comprise: cpu i/f unit 21, input data processing unit 23, contiguous unit 24, dateout processing unit 25.Empty frame table shown in Fig. 1 shows: control unit 22 is controlled input data processing unit 23, contiguous unit 24 and dateout processing unit 25 respectively, and produces the required separately timing control signal in each unit.
Here, timing control signal comprises: synchronizing clock signals, read-write enable signal and read/write address signal.Wherein, described synchronizing clock signals comprises: the synchronization frame clock signal; Described read-write enable signal is specially: the enable signal of read/write dual port random access memory (DPRAM, Double Port Random Memory); Described read/write address signal is specially: the address signal of read/write DPRAM.
Input data processing unit 23 links to each other with cpu i/f unit 21, is used for according to described timing control signal, realizes simultaneously, should importing data and sending to cpu i/f unit 21 reception and the buffer memory of input data.And, need the input data that receive buffer memory two frames at least owing to realize clog-free exchange, therefore, the constant time lag of exchanges data is two frames.The constant time lag of two frames refers to: data enter the time delay of FPGA to output FPGA.
Above-mentioned input data processing unit 23 and dateout processing unit 25 all adopt DPRAM as memory module, and be data cached.
As shown in Figure 2, cpu i/f unit 21 comprises: data are deposited module 211, control is deposited module 212 and continued and deposit module 213, and the data interaction between then described cpu i/f unit 21 and the CPU1 is specially: data are deposited module 211, control and are deposited module 212 and continue and deposit data interaction between module 213 and the CPU1.
Data are deposited module 211, control and are deposited module 212 and continue that to deposit module 213 separate, are all: according to sheet choosing and the read-write enable signal of CPU1, by carrying out read-write operation between data wire, address wire and the CPU1.And CPU1 specifically is stored in control in the cpu i/f unit 21 to the configuration of FPGA2 and deposits module 212 and continue and deposit in the module 213.
In cpu i/f unit 21, data are deposited module 211 and are linked to each other with input data processing unit 23, are used to receive and store the input data that input data processing unit 23 sends to cpu i/f unit 21.
Control is deposited module 212 and is linked to each other with input data processing unit 23, is used to store the control information of CPU1 to the FPGA2 configuration, and according to the configuration of CPU1 to FPGA2, when carrying out bit exchange in FPGA2, the mode of operation of control FPGA2 is switched.
Continue and deposit module 213 and link to each other, be used to store CPU1 to the FPGA2 configured corresponding relation, and the corresponding relation that the input data that disposed are carried out bit exchange to dateout sends to contiguous unit 24 with contiguous unit 24.
Because input data processing unit 23 and dateout processing unit 25 all adopt DPRAM as memory module, and be data cached, therefore, as shown in Figure 2, further comprise the DPRAM231 that imports data in the input data processing unit 23; The DPRAM251 that further comprises dateout in the dateout processing unit 25.
The mode of operation of system shown in Figure 2 comprises: normal mode of operation and self check mode of operation.In normal mode of operation, can realize the data of input FPGA2 are carried out the operation of exporting after the bit exchange by continuation method.In normal mode of operation or self check mode of operation, all can carry out verification of correctness to the operation that the data of input FPGA2 carry out exporting after the bit exchange by the detection of message mode realization to FPGA2.
And then under described self check mode of operation, the mode of module 211 values is deposited to read in data in cpu i/f unit 21, can also judge whether FPGA2 correctly carries out bit exchange.
Based on the structure of Fig. 1, method of the present invention may further comprise the steps:
Step 101, behind system of the present invention electrifying startup, FPGA2 receives the input data, CPU1 is by cpu i/f unit 21 configuration FPGA2, and will import the corresponding relation that data carry out bit exchange to dateout and dispose to FPGA2.
Step 102, FPGA2 will import data and carry out exporting after the bit exchange according to configured corresponding relation.
As shown in Figure 3, step 101 is specially:
The timing control signal that step 1011, input data processing unit 23 provide according to control unit 22 to described input Data Receiving and buffer memory, should be imported data forwarding simultaneously and give cpu i/f unit 21.
Step 102 is specially:
The described timing control signal that step 1022, dateout processing unit 25 provide according to control unit 22, to the data from contiguous unit 24 output receive, buffer memory and output.
From the data of dateout processing unit 25 outputs is exactly through the dateout after the bit exchange.Here, bit exchange is meant: will import certain bit exchange of certain road input in the data certain bit to certain road output.
Based on the structure of Fig. 2, step 1011 further is:
Step 10111, input data processing unit 23 will be imported data forwarding and deposit module 211 to data.Here, because the input data processing unit 23 described input data forwarding that will receive is deposited module 211 to data, therefore, the content of importing memory module buffer memory in the data processing unit 23 is identical with the content that data are deposited module 211.
Accordingly, step 1012 is specially:
Step 10121, continue and deposit module 213 described corresponding relation is disposed to contiguous unit 24.
Wherein, before step 10111, also comprise:
Step a, control are deposited module 212 according to the configuration of CPU1 to FPGA2, and the mode of operation of control FPGA2 is switched.
In normal mode of operation, and the read-write operation mode that input data processing unit 23 is adopted is that step 10111 is specially under the situation of ping-pong operation mode:
Step 10111a, input data processing unit 25 adopt DPRAM as memory module, the described input data of buffer memory, here, memory module is the DPRAM231 of input data, the described input data that enter input data processing unit 25 are written to the DPRAM231 of input data earlier through after string and the conversion.
And input data processing unit 25 writes first frame of described input data the low memory of DPRAM231 according to the first frame timing control signal that control unit 22 provides; According to the second frame timing control signal that control unit 22 provides, second frame of input data is write the high memory block of DPRAM231.
Step 10111b, when obtaining the described second frame timing control signal, according to configured corresponding relation, the data of described low memory first frame are read.
Transmission sequence frame by frame, above-mentioned read-write operation is carried out in circulation, that is: the 3rd frame that will import data writes the low memory of DPRAM231, simultaneously, the data of the high memory block of DPRAM231 second frame is read; The 4th frame of input data is write the high memory block of DPRAM231, simultaneously, the data of DPRAM231 low memory the 3rd frame are read, the rest may be inferred, behind the read-write operation of finishing at input data processing unit 23 described all frames of input data, finish current handling process.
Under normal mode of operation, in the step 1022, dateout processing unit 25 also adopts DPRAM as memory module, and here, memory module is the DPRAM251 of dateout.And the read-write operation mode that dateout processing unit 25 is adopted is the ping-pong operation mode, finish to the data from contiguous unit 24 outputs receive, buffer memory and output.Wherein, the data from DPRAM251 output need output after also string is changed.
Deposit that arbitrary bit is set in the module 213 is the working mode selection position continuing.Wherein, working method comprises: continuation method and message mode, this bit are 1 o'clock, select message mode; Be 0 o'clock, select continuation method.Continue and deposit the variable of corresponding one 16 bit in module 213 each address.Such as, the 15th bit is set to the working mode selection position, and the bit that also can select other for use is the working mode selection position.
Adopt the ping-pong operation mode in the realization flow of the invention described above method, realized carrying out the function of clog-free exchange, and can allow any one input bit need the assigned address on the output channel to export at all according to the bit in the time slot.Shown in Figure 4ly embodied the present invention intuitively and realized importing the function of bit exchange between data and the dateout, and embodied between n road input data and the n road dateout, from being input to the clog-free function of exchange of output.Wherein, clog-free function of exchange refers to: will specify in the input data content exchange on the bit base to the bit base of specifying in the dateout.
When switching under the self check mode of operation, then also comprise after the step 1022:
The data that step 1023, dateout processing unit 25 receive, buffer memory is exported from described contiguous unit 24 according to the Loopback Mode of output, input data, will send to input data processing unit 23 from the data of dateout processing unit 25 outputs; Between described CPU and described FPGA, adopt message mode, the data of checking input FPGA2 are carried out the correctness of bit exchange to output FPGA2 data.
Because described input data input to input data processing unit 23 at first need be through string and conversion, accordingly, dateout processing unit 25 is before dateout, need process and string conversion, therefore, between input data processing unit 23 and dateout processing unit 25, handled data are specially: parallel multichannel data.So, described Loopback Mode is specially:
Here, finishing many bit exchange is the data that walk abreast, if 1 bit exchange is exactly the data of serial.
Adopt message mode in the step 1023, carry out the bit exchange verification of correctness and be specially:
Step 1023a, CPU1 are via cpu i/f unit 21, to continue and deposit module 213 and all be defined as: message mode with first via dateout corresponding address space, and the lowest bit position of described address write the message of appointment, this lowest bit position is the message digit in the described address; Other dateout corresponding address spaces, road are set to: the continuation method that carries out bit exchange according to described configured corresponding relation;
Step 1023b, the contiguous unit 24 described specify message of depositing module 213 message digits that will continue sends to dateout processing unit 25;
Step 1023c, CPU1 are via cpu i/f unit 21, read data in the cpu i/f unit 21 and deposit the content of module 211 storages, deposit the message that module 213 is sent via connecting module 24 with continuing, that is: the described specify message of message digit compares, if identical, judge that then that these road input data are carried out the bit exchange function exported after the bit exchange is correct; Continue circulation execution in step 1023a～1023c, behind each road that traveled through described dateout, finish current handling process.
In brief, so-called self check mode of operation is meant: FPGA2 is under the situation by external path not, adopt message mode, send out test data at any bit base of specifying dateout, and finish in FPGA2 inside data all passages from loopback, data of sending by message mode relatively and receive whether correctly data are whether identical detects the realization of bit exchange function.
With four * four the tunnel, speed is that 1 bit exchange of 8.196MHz input data is an example, respectively under normal mode of operation and self check mode of operation, describes the realization flow of the inventive method.In this example, the clock signal of system-frame transmission is 8K, every frame 1024 bits, the memory module of input data is one 4 * 2048 DPRAM, continuing and depositing module is 1 16 * 4096 DPRAM, the memory module of dateout is four 1 * 2048 DPRAM, continue each address of depositing module is corresponding with 1 bit of one tunnel output, it is identical that data are deposited in the memory module of module and input data the content of institute's buffer memory, be used in the self check mode of operation correctness of test bit function of exchange.
Method embodiment one:
Present embodiment is for being under the normal mode of operation, Fig. 5 be one of method embodiment based on system configuration, based on the structure of Fig. 5, the realization flow of method may further comprise the steps in the present embodiment:
Step 201, control are deposited module 212 according to the configuration of CPU1 to FPGA2, and the mode of operation of control FPGA2 is switched.
Here, deposit in the module 213 continuing, it is the working mode selection position that the 15th bit is set.This bit is made as 0, and representative adopts the continuation method realization data of input FPGA2 to be carried out the operation of exporting after the bit exchange in normal mode of operation.
Step 202, four road 8.196MHz input data are input among the FPGA2, the timing control signal that input data processing unit 23 provides according to control unit 22, to described input Data Receiving and buffer memory, and will import the DPRAM2311 of storage in 4 * 2048 input data; Simultaneously, should import data forwarding and deposit module 211 to data.
Wherein, the read-write operation mode that input data processing unit 23 is adopted is the ping-pong operation mode, is specially:
Input data processing unit 25 writes first frame of described input data the low memory of DPRAM2311 according to the first frame timing control signal that control unit 22 provides; According to the second frame timing control signal that control unit 22 provides, second frame of input data is write the high memory block of DPRAM2311;
When obtaining the described second frame timing control signal,, the data of DPRAM2311 low memory first frame are read according to configured corresponding relation;
Transmission sequence frame by frame, above-mentioned read-write operation is carried out in circulation, until the read-write operation of finishing at input data processing unit 23 described all frames of input data.
Step 203, continue and deposit module 213 and will import the corresponding relation that data carry out bit exchange to dateout and dispose to contiguous unit 24.
Step 204, contiguous unit 24 receive after the data of input data processing unit 23 outputs according to configured corresponding relation, send to dateout processing unit 25.
Step 205, dateout processing unit 25 also adopt DPRAM as memory module, here, memory module is four DPRAM that are designated 2511,2512,2513 and 2514 1 * 2048 dateout respectively, and, the read-write operation mode that dateout processing unit 25 is adopted be the ping-pong operation mode also, finish to the data of exporting from contiguous unit 24 receive, buffer memory and output.Wherein, in order to guarantee two frame time delays, require each the switching to align with frame head.
Above-mentioned handling process is carried out in circulation, after the bit exchange of finishing all frames of four road 8.196MHz input data, finishes above-mentioned handling process, output be the dateout of four road 8.196MHz after bit exchange.
Method embodiment two:
Present embodiment is for being under the self check mode of operation, Fig. 6 be two of method embodiment based on system form structural representation.
In the present embodiment, the principle of step 301～305 and method embodiment one and operate basic identical, different is: the value of depositing the 15th bit in the module 213 that will continue in the step 301 of present embodiment is made as 1, representative is in the self check mode of operation, adopt the detection of message mode realization, verification of correctness is carried out in the operation that the data of input FPGA2 carry out exporting after the bit exchange FPGA2.
So, when FPGA2 entered the self check mode of operation, based on the structure of Fig. 6, the realization flow of method was further comprising the steps of in the present embodiment:
Four tunnel dateouts that step 306, dateout processing unit 25 receive, buffer memory is exported from described contiguous unit 24, according to the Loopback Mode of output, input data, will send to input data processing unit 23 from the data of dateout processing unit 25 outputs.
Briefly, Loopback Mode is exactly i road output loopback and receives the input of i+1 road, here, does not need outside data flow and inputs to input data processing unit 23.
Concerning present embodiment, first via dateout is connected to the second tunnel input data, according to described Loopback Mode, and the like, the four tunnel dateout is connected to first via input data, forms the loopback of inputoutput data.
Step 307, CPU1 be via cpu i/f unit 21, will continue to deposit module 213 and all be defined as with first via dateout corresponding address space: message mode, and the lowest bit position of described address is write the message of appointment; Other three tunnel dateouts corresponding address definition spaces are: the continuation method that carries out bit exchange according to described configured corresponding relation.
Step 308, the contiguous unit 24 described specify message of depositing module 213 message digits that will continue sends to dateout processing unit 25.
Step 309, CPU1 are via cpu i/f unit 21, read data in the cpu i/f unit 21 and deposit the content of module 211 storages, deposit the message that module 213 is sent via connecting module 24 with continuing, that is: the described specify message of message digit compares, if identical, judge that then that these road input data are carried out the bit exchange function exported after the bit exchange is correct.
Continue circulation and carry out above-mentioned handling process, behind the every road that traveled through described four tunnel dateouts, finish above-mentioned handling process.Under the self check mode of operation, between CPU1 and FPGA2, adopt message mode, the data of checking input FPGA2 are carried out the correctness of bit exchange to output FPGA2 data.
Fig. 7 is the system principle schematic diagram that sends message with message mode, based on the structure of Fig. 7, draws together following steps with the message mode transmission packet:
Continue in step e1, the CPU1 configuration cpu i/f module 21 and deposit module 213, the 15th bit of the 0th bit address is set to 1 in the corresponding first via dateout, promptly specifies the 0th bit of first via dateout to send the message 0 of being stored in this address lowest order the 0th bit;
The message 0 of being stored in step e2, the 0th bit with address described in the step e1 in contiguous unit 24 sends to the 0th bit of first via dateout, thereby has finished the transmission of message.
The foregoing description is all: 1 bit exchange, if need to realize many bit exchange, only add deserializer before the DPRAM of need input data in input data processing unit 23, and adduction string transducer gets final product behind the DPRAM of the dateout in dateout processing unit 25.At the bit exchange of different ways, then need to adjust the DPRAM of input, dateout and the size of the DPRAM that deposits module 213 of continuing accordingly, can finish function corresponding.
The above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.
Claims (15)
1. a system that realizes the data bit exchange is characterized in that this system comprises: processor CPU and coupled programmable logic device FPGA; Wherein, CPU is used to dispose described FPGA, and the input data that dispose described FPGA are carried out the corresponding relation of bit exchange to dateout;
FPGA is used to obtain the input data, and according to the configuration of described CPU, will import data and carry out exporting after the bit exchange;
Described FPGA comprises: cpu i/f unit, control unit, input data processing unit, contiguous unit, dateout processing unit.
2. system according to claim 1 is characterized in that,
The cpu i/f unit links to each other with CPU, is used for finishing data interaction between FPGA and CPU, and preserves the configuration of described CPU to FPGA;
Control unit is used to finish the sequencing control of described FPGA inside, produces and control the required timing control signal in other each unit among the described FPGA; Wherein, timing control signal comprises: synchronizing clock signals, read-write enable signal and read/write address signal;
The input data processing unit links to each other with described cpu i/f unit, is used for according to described timing control signal, realizes reception and buffer memory to described input data, simultaneously, should import data and send to the cpu i/f unit;
Contiguous unit, link to each other with described input data processing unit, described cpu i/f unit, described dateout processing unit, be used for obtaining the described CPU that stores described cpu i/f unit configuration to FPGA, and according to deploy content and mode of operation, reception sends to the dateout processing unit after the data of input data processing unit output;
The dateout processing unit is used for according to described timing control signal, to the data from contiguous unit output receive, buffer memory and output.
3. system according to claim 2 is characterized in that, described cpu i/f unit comprises: data are deposited module, control is deposited module and continued and deposit module;
Data are deposited module, link to each other with described input data processing unit, are used to receive and store the input data that described input data processing unit sends to described cpu i/f unit;
Module is deposited in control, links to each other with described input data processing unit, is used for the configuration to described FPGA according to described CPU, and when carrying out bit exchange in FPGA, the mode of operation of control FPGA is switched;
Continue and deposit module, link to each other, be used to store described CPU, and the corresponding relation that the input data that disposed are carried out bit exchange to dateout sends to described contiguous unit the FPGA configured corresponding relation with described contiguous unit.
4. system according to claim 2 is characterized in that, described synchronizing clock signals comprises: the synchronization frame clock signal; Described read-write enable signal is specially: the enable signal of read/write dual port random access memory DPRAM; Described read/write address signal is specially: the address signal of read/write DPRAM.
5. system according to claim 3 is characterized in that, under normal mode of operation, contiguous unit receives from the data of described input data processing unit output with continuation method, and sends to the dateout processing unit; Under the self check mode of operation, contiguous unit sends to the dateout processing unit with message mode with the described message digit of depositing in the module's address that continues.
6. system according to claim 5 is characterized in that, described cpu i/f unit under described self check mode of operation, is used to also judge whether described FPGA correctly carries out bit exchange.
7. method that realizes data bit exchange is characterized in that this method may further comprise the steps:
A, FPGA receive the input data, and CPU disposes FPGA, and will import the corresponding relation that data carry out bit exchange to dateout and dispose to FPGA; Described FPGA is made up of cpu i/f unit, control unit, input data processing unit, dateout processing unit and contiguous unit;
B, FPGA will import data and carry out exporting after the bit exchange according to configured corresponding relation.
8. method according to claim 7 is characterized in that steps A is specially:
The timing control signal that A1, input data processing unit provide according to control unit to described input Data Receiving and buffer memory, should be imported data forwarding simultaneously and give described cpu i/f unit;
A2, cpu i/f unit dispose described corresponding relation to contiguous unit;
Accordingly, step B is specially:
B1, described contiguous unit receive after the data of described input data processing unit output according to described configured corresponding relation, send to the dateout processing unit;
The described timing control signal that B2, dateout processing unit provide according to described control unit, to the data from contiguous unit output receive, buffer memory and output.
9. method according to claim 8 is characterized in that, described cpu i/f unit by data deposit module, control is deposited module and is continued and deposits module and form;
Then steps A 1 further is:
A11, described input data processing unit will be imported data forwarding and deposit module to data;
Accordingly, steps A 2 is specially:
A21, continue and deposit module described corresponding relation is disposed to contiguous unit.
10. method according to claim 9 is characterized in that, also comprises before steps A 11:
Step X, according to the configuration of described CPU to described FPGA, the mode of operation that module controls FPGA is deposited in control is switched.
11., it is characterized in that FPGA is in normal mode of operation according to claim 9 or 10 described methods, and when the read-write operation mode that the input data processing unit adopts was the ping-pong operation mode, steps A 11 was specially:
A111, described input data processing unit adopt the described input data of dual port random access memory DPRAM buffer memory;
And,, first frame of described input data is write the low memory of DPRAM according to the first frame timing control signal that described control unit provides; According to the second frame timing control signal that described control unit provides, second frame of input data is write the high memory block of DPRAM;
A112, when obtaining the described second frame timing control signal, according to described configured corresponding relation, the data of described low memory first frame are read;
Transmission sequence frame by frame, circulation execution in step A111～A112 flow process is until the read-write operation of finishing at the input data processing unit described all frames of input data.
12. method according to claim 11 is characterized in that, among the step B2, described dateout processing unit adopts the DPRAM storage, and the read-write operation mode that the dateout processing unit is adopted is the ping-pong operation mode.
13. method according to claim 12 is characterized in that, deposits in the module described continuing, it is the working mode selection position that arbitrary bit is set.
14. method according to claim 13 is characterized in that, when FPGA switches under the self check mode of operation, then also comprises after the step B2:
B3, the data that the dateout processing unit receives, buffer memory is exported from described contiguous unit according to the Loopback Mode of output, input data, will send to described input data processing unit from the data of dateout processing unit output; Between described CPU and described FPGA, adopt message mode, the data of checking input FPGA are carried out the correctness of bit exchange to output FPGA data.
15. method according to claim 14 is characterized in that, adopts message mode among the step B3, carries out the bit exchange verification of correctness and is specially:
B31, described CPU continue via described cpu i/f unit and deposit module and first via dateout corresponding address space is set to: message mode, and the lowest bit position of described address is write the message of appointment; Other dateout corresponding address spaces, road are set to be undertaken by the configuration corresponding relation continuation method of bit exchange;
B32, contiguous unit send to the dateout processing unit with the described described specify message of depositing message digit in the described address of module that continues;
B33, described CPU read the content that data in the cpu i/f unit are deposited module stores, deposit module and compare with described continuing via the message that contiguous unit sent, if identical, judge that then that these road input data are carried out the bit exchange function exported after the bit exchange is correct; Continue circulation execution in step B31～B33, until each road that has traveled through described dateout.
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| CN104244119B (en) * | 2013-12-26 | 2018-05-08 | 邦彦技术股份有限公司 | Time slot exchange device and method based on FPGA |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6473403B1 (en) * | 1998-05-04 | 2002-10-29 | Hewlett-Packard Company | Identify negotiation switch protocols |
| CN1428976A (en) * | 2001-12-27 | 2003-07-09 | 阿尔卡塔尔加拿大公司 | User priority mapping in bridge VLAN |
| CN1622652A (en) * | 2003-11-28 | 2005-06-01 | 华为技术有限公司 | A method for implementing roam charging of mobile station data service |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6473403B1 (en) * | 1998-05-04 | 2002-10-29 | Hewlett-Packard Company | Identify negotiation switch protocols |
| CN1428976A (en) * | 2001-12-27 | 2003-07-09 | 阿尔卡塔尔加拿大公司 | User priority mapping in bridge VLAN |
| CN1622652A (en) * | 2003-11-28 | 2005-06-01 | 华为技术有限公司 | A method for implementing roam charging of mobile station data service |
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