CN111143260B

CN111143260B - RAID path switching device in SSD master control

Info

Publication number: CN111143260B
Application number: CN201911406936.3A
Authority: CN
Inventors: 王运哲
Original assignee: Shandong Sinochip Semiconductors Co Ltd
Current assignee: Shandong Sinochip Semiconductors Co Ltd
Priority date: 2019-12-31
Filing date: 2019-12-31
Publication date: 2023-08-04
Anticipated expiration: 2039-12-31
Also published as: CN111143260A

Abstract

The invention discloses a RAID path switching device in SSD master control, which comprises an ARBITER module, a DMA module and an IMA module, wherein the ARBITER module is responsible for opening a specified data path according to configuration requirements, and the DMA module is responsible for controlling data interaction between the ARBITER module and an AXI master port, sending a read-write command to the AXI master port and converting an AXI data form into an internal data format; the IMA is responsible for controlling the data interaction between the ARBITER module and the AXI slave port, analyzing the command from the AXI slave port and converting the AXI data form into an internal data format. The RAID is realized in the SSD main control chip, and different paths can be selected in different working modes according to the system condition, so that the SSD main control chip has high flexibility.

Description

RAID path switching device in SSD master control

Technical Field

The invention relates to a RAID access switching device, in particular to a RAID access switching device in SSD master control.

Background

During the reading and writing of SSD, when data is read from Flash grains, if ECC error correction fails and operations such as read re-try cannot read correct data, how to recover the data is considered. The RAID technology can fully play the array advantages of the storage chips, provide fault tolerance function to ensure data security, and still can continue to work under the condition that a certain storage unit has a problem.

The conventional RAID is generally realized outside an SSD main control chip. Although the patent 'a RAID active acceleration device in SSD master control' and 'a RAID passive acceleration device in SSD master control' disclose a method for realizing RAID in SSD master control chip, the two are both single hardware path designs, corresponding paths are not selected according to application requirements, and flexibility is poor.

Disclosure of Invention

The technical problem to be solved by the invention is to provide the RAID path switching device in the SSD main control, RAID is realized in the SSD main control chip, and different paths can be selected in different working modes according to the system condition, so that the flexibility is strong.

In order to solve the technical problems, the invention adopts the following technical scheme: a RAID path switching device in SSD master control comprises an ARBITER module, a DMA module and an IMA module, wherein the ARBITER module is responsible for opening a specified data path according to configuration requirements, namely selecting one from three data input interfaces to a core calculation control module, selecting one from two data output interfaces to output the space data, and the DMA is responsible for controlling the data interaction between the ARBITER module and an AXI master port, sending a read-write command to the AXI master port and converting an AXI data form into an internal data format; the IMA is responsible for controlling the data interaction between the ARBITER module and the AXI slave port, analyzing the command from the AXI slave port and converting the AXI data form into an internal data format.

Further, the ARBITER module comprises a state machine, a plurality of multiplexers, three groups of last delays, n enabling registers of the core computing control modules and n enabling registers of the SRAM;

the command state machine divides each task into two phases, wherein the first phase is the source data inflow and the second phase is the parity data outflow;

the multiple multiplexers are gated by path signals and are responsible for gating three paths of source data for one path to be output and gating two paths of read parity addresses for one path to be output;

the enabling registers of the n core computing control modules are used for respectively connecting the data converted by the multiplexer with the n core computing control modules according to the id information, and gating one path of ack signals fed back by the n core computing modules to feed back to the corresponding modules;

n paths of SRAM are sequentially selected by enabling registers of n SRAMs, and the data are read back from the n paths of SRAM;

the three groups of last delays are respectively responsible for delaying last signals of the private interface, the AXI master port and the AXI slave port by two beats, and then one path of enabling register for clearing the core calculation control module is selected through the multiplexer according to path signals.

Further, the DMA module comprises a command state machine, a data state machine, a frequency counter, a write address conversion, a read address conversion, a write counter, a read counter and a response counter;

the command state machine comprises IDLE, LOAD, STORE states and sends corresponding commands to an AXI mster bus;

the data state machine comprises IDLE, HDSHK, LOAD, WAIT, STORE, DELY six states, is linked with the core operation control module, and is communicated with data interaction of the AXI MATER and the SRAM;

the frequency counter is responsible for accumulating the number of stripes of the inflow data;

the write address conversion is responsible for converting the write count value into a write data block id;

the read address conversion is responsible for converting the read count value into a read data block id;

the write counter is responsible for writing the number of source data into the core operation control module in the LOAD state of the accumulated data state machine;

the read counter is responsible for reading the parity number from the SRAM in the state of the accumulated data state machine STORE;

the response counter is responsible for accumulating response information of the axi_mst and determining whether the transmission of the parity is ended.

Further, the IMA module comprises a writing state machine, a reading state machine, reading address conversion, writing address conversion, a frequency counter, a writing counter and a reading counter;

the write state machine comprises WIDLE, WWAIT, WCPOP, HDSHK, DPOP states, is linked with the core operation control module, and controls source data to flow into the SRAM from an AXI SLAVE port;

the read state machine comprises RIDLE, RWAIT, RCPOP, RCGET, BRDEN, DPUSH five states, and feeds the parity read from the SRAM back to an AXI SLAVE interface;

the write counter is responsible for accumulating the number of source data written into the core operation control module in the DPOP state;

the read counter is responsible for reading the parity number from the SRAM in the accumulated DPUSH state.

Further, the internal data format is the same as the data format of the private interface, and is the req/ack, first/last, data/data_vld and id signal group.

Further, the data input interface of the RAID path includes a private interface, an aximaster port and an axislave port, the data output interface of the RAID path includes an aximaster port and an axislave port, and the number of the RAID paths is 6, which are respectively: the private interface is to an axislave port, the private interface is to an aximaster port, an aximaster port is to an axislave port, an axislave port is to an axislave port, and an axislave port is to an aximaster port.

The invention has the beneficial effects that: and the data from the AXI bus is converted into a data format unified with the private interface through the DMA module and the IMA module, so that the core calculation control module can process the data conveniently.

The data format is concise, the multi-module state machine is executed in parallel, each data is controlled accurately, the data flow is continuous, and the calculation efficiency is fully exerted.

The whole process is divided into two stages of number inlet and number outlet, so that six data paths can be freely combined between 3 number inlet interfaces and 2 number outlet interfaces.

Drawings

FIG. 1 is a schematic diagram of an ARBITER module;

FIG. 2 is a schematic diagram of a DMA module;

FIG. 3 is a schematic diagram of an IMA module;

fig. 4 is a diagram of an internal data format.

Detailed Description

The invention will be further described with reference to the drawings and the specific examples.

Example 1

The embodiment discloses a RAID path switching device in SSD main control, which is realized by selecting one of six paths to flow into and flow out of a RAID accelerator in one task, wherein the inflow is source data, and the outflow is parity data.

The data input interface of the RAID path comprises a private interface (private interface), an AXI master port and an AXI slave port, and the data output interface of the RAID path comprises an AXI master port and an AXI slave port.

The RAID paths have 6 paths, which are respectively: private interface to axislave port (p 2 s), private interface to aximaster port (p 2 m), aximaster port to aximaster port (m 2 m), aximaster port to axislave port (m 2 s), axislave port to axislave port (s 2 s), and axislave port to aximaster port (s 2 m).

The RAID path switching device in this embodiment includes three modules including an ARBITER, a DMA and an IMA. The ARB is responsible for opening a specified data path according to configuration requirements, namely the following two tasks: one is selected from three data input sources and is given to the core calculation control module, and the other is selected from two output ends and is used for outputting the parity data.

The DMA is responsible for controlling the data interaction between the ARBITER and the AXI master, sending read-write commands to the AXI master, and converting the AXI data form into an internal data format. The IMA is responsible for controlling the data interaction between the ARBITER and the AXI slave port, analyzing the command from the AXI slave port and converting the AXI data form into an internal data format.

The internal data format is the same as the data format of the private interface, and is a req/ack, first/last, data/data_vld and id signal group, so that the processing of the core calculation control module is facilitated.

In one task, ARBITER, DMA (m 2 x), IMA (s 2 x), a core calculation control module and SRAM are linked to realize the pipeline data exclusive OR processing, namely, the generation of the parity is completed when the data inflow is completed, and then the parity is fed back to the AXI bus through DMA (x 2 m) or IMA (x 2 s) according to the requirement. Wherein x represents m or s.

As shown in fig. 1, 2, and 3, the schematic structures of the ARBITER module, the DMA module, and the IMA module are shown, in the figure, the signal with c_as the prefix represents the interaction signal between the RBITER and the core computing control module, the signal with p_as the prefix represents the interaction signal between the RBITER and the NFC private interface, the signal with m_as the prefix represents the interaction signal between the RBITER and the DMA, the signal with s_as the prefix represents the interaction signal between the RBITER and the SRAM, the signal with buf_as the prefix represents the interaction signal between the RBITER and the SRAM, and the signal with n as the suffix represents the interaction signal between the ARBITER and the n core computing control modules or the interaction signal between the ARBITER and the n SRAMs (buffers).

As shown in FIG. 1, the ARBITER module includes a state machine, nine multiplexers (MUX 0-MUX 9), three sets of last delays (D1D 2, D3D4, D5D 6), n core computation control module enable registers (STEP1_CH_EN [ n ]), and n SRAM enable registers (STEP2_CH_EN [ n ]).

As shown in fig. 2, the DMA module includes a command state machine, a data state machine, a read address translation, a write address translation, a count counter, a read counter, and a write counter.

As shown in fig. 3, the IMA module includes a write state machine, a read address translation, a write address translation, a count counter, a read counter, and a write counter.

The functions of each component in the ARBITER module are respectively as follows:

the command state machine divides each task into two phases, the first phase is the source data in-flow and the second phase is the parity data out-flow.

The multiplexers gated by the path are responsible for turning the three-way source data into one way (including signals in the internal data format) and the two-way read parity address into one way (buf_addr).

STEP1_CH_EN [ n ] respectively connects the data (each signal in the internal data format) converted by the multiplexer with n paths of core operation control modules according to id information, and one path of ack signals fed back by the n paths of core operation modules is gated and fed back to the corresponding module (p/m/s).

STEP2_CH_EN [ n ] will sequentially select n-way SRAM (buf_data [ n ]), from which the parity data is read back.

The three-way last delayer (p/m/s) is responsible for delaying each way last signal by two beats (because the intermediate calculation result in the core calculation module is that the two beats are delayed and enter the SRAM), and then a way is selected according to the path through the multiplexer to clear STEP1_CH_EN [ n ].

The DMA module is used for processing the task with path type m2x or x2m, and the functions of each component are as follows:

the command state machine comprises three states (C_is prefix) of IDLE IDLE, LOAD command LOAD, STORE command STORE, and corresponding command is sent to AXI mster bus.

The data state machine comprises six states (D_is a prefix) of IDLE IDLE, handshake HDSHK, LOAD source data LOAD, WAIT for WAIT, STORE parity data STORE and delay DELY, and is linked with the core operation control module to communicate data interaction of AXI MATER and SRAM.

The counter is responsible for accumulating the number of stripes of the incoming data.

The write address translation is responsible for translating the write count value into a write data block id.

The read address translation is responsible for translating the read count value into a read data block id.

The write counter is responsible for writing the number of source data to the core operation control module in the accumulated D_LOAD state.

The read counter is responsible for accumulating the number of parity reads from the SRAM in the d_store state.

The response counter is responsible for accumulating response information of axi_mst to determine whether the transmission of the parity is ended.

The IMA module is used for processing tasks with path type s2x or x2s, and the functions of each component are as follows:

the write state machine comprises five states of idle WIDLE, a waiting write command WWAIT, a write command popup WCPOP, a handshake HDSHK and a source data popup DPOP, and is linked with the core operation control module to control the source data to flow into the SRAM from an AXI SLAVE port.

The read state machine comprises five states of idle RIDLE, waiting for a read command RWAIT, popping up a read command RCPOP, analyzing a read command RCGET, BUF read enabling BRDEN, and pressing the data of the property into a DPUSH, and feeding the property read from the SRAM back to an AXI SLAVE interface.

The write counter is responsible for accumulating the number of source data written into the core operation control module in the DPOP state.

The following describes the operation of the present RAID path switching device using P2S and M2M as examples.

The working process when in the P2S working mode is as follows:

1. after start, the arbiter goes from IDLE to STEP1 state and the ima's read state machine goes from RIDLE to RWAIT state.

2. The data on the P port sequentially and circularly enter n core operation control modules through multipath selection in the arbiter, and the n core operation control modules sequentially feed back a c_finish signal to the arbiter after the number entering and operation are completed.

3. And after the Arbiter takes all the c_finish, generating an s1_finish signal output and entering into a STEP2 state. After the external NFC takes the s1_finish, a read command is sent to the axi_slave interface through the AXI bus.

4. The read state machine of Ima sequentially enters a DPUSH state through RCPOP, RCGET, BRDEN state after detecting a read command, gives a read address in the state, converts the read address into id to an arbiter through read address conversion, links with STEP2_CH_EN and n SRAMs in the arbiter, opens channels from the n SRAMs to AXI_RDATA, and feeds back the parity to an AXI bus.

5. After completion of the read count in Ima, an s_finish signal is generated to the arbiter and returns to the RIDLE state, and the arbiter also returns to the IDLE state. The task of this time p2s ends.

The working process when in the M2M working mode is as follows:

1. after start, the bit goes from IDLE to STEP1, the command state machine of dma goes from C_IDLE to C_LOAD, and the data state machine goes from D_IDLE to D_HDSHK.

2. The dma sends a read command to the AXI bus in the c_load state. After the data of the bus comes, the dma and the arbiter, and the N core operation control modules link to open the data channels from the bus to the N SRAMs, and the data state machine enters the cycle of D_LOAD and D_HDSHK. And in the D_LOAD state, connecting the bus data with an arbiter, connecting the bus data with a corresponding core operation control module according to the current m_wr_id by a multiplexer of the current m_wr_id, and writing an intermediate operation result into a corresponding SRAM. And (3) sending m_req to the next core operation control module in the D_HDSHK state, and completing handshake after obtaining ack, wherein m_wr_id changes correspondingly. The time_cnt count in the dma is finished, the data state machine enters a D_WAIT state, and the n core operation control modules sequentially feed back a c_finish signal to the arbiter after finishing counting.

3. And after the Arbiter takes all the c_finish, generating an s1_finish signal output and entering into a STEP2 state. After the dma has taken the s1_finish, the command state machine of the dma enters the C_STORE state and sends a write command to the AXI bus.

4. The dma and the arbiter link to open the data channels from n SRAMs to the bus, and the data state machine of the dma enters the cycle of the two states of D_STORE and D_DELY. Dmas switch read addresses in the D_DELY state while converting them into ids by read address translation to the arbiters. And generating STEP2_CH_EN by the arbiter in the D_STORE state according to m_rd_id, gating a corresponding SRAM, and feeding the read parity data back to the bus read data channel through dma.

5. After the count of resp_cnt in dma is finished (the slave where the identifier des_addr is located has taken the parity data), an m_finish signal is generated to the arbiter and returns to the D_IDLE state, and the arbiter also returns to the IDLE state. The task ends.

As shown in fig. 4, is a data format in a single data transmission (recovery) process.

The invention converts the data from the AXI bus into a data format unified with the private interface through the DMA module and the IMA module, and is convenient for a core calculation control module (see the last patent) to process the data.

The foregoing description is only of the basic principles and preferred embodiments of the present invention, and modifications and alternatives thereto will occur to those skilled in the art to which the present invention pertains, as defined by the appended claims.

Claims

1. A RAID path switching device in SSD master control is characterized in that: the device comprises an ARBITER module, a DMA module and an IMA module, wherein the ARBITER module is responsible for opening a specified data path according to configuration requirements, namely selecting one from three data input interfaces to be given to a core calculation control module, and selecting one from two data output interfaces to output the parity data; the data input interface of the RAID path comprises a private interface, an AXI master port and an AXI slave port, the data output interface of the RAID path comprises an AXI master port and an AXI slave port, and the number of the RAID data paths is 6, and the number of the RAID data paths is respectively as follows: the private interface is connected to an AXI slave port, the private interface is connected to an AXI master port, an AXI master port is connected to an AXI slave port, an AXI slave port is connected to an AXI slave port, and an AXI slave port is connected to an AXI master port;

the DMA is responsible for controlling the data interaction between the ARBITER module and the AXI master port, sending a read-write command to the AXI master port, and converting an AXI data form into an internal data format; the internal data format is the same as the data format of the private interface and is a req/ack, first/last, data/data_vld and id signal group;

the IMA is responsible for controlling the data interaction between the ARBITER module and the AXI slave port, analyzing the command from the AXI slave port and converting the AXI data form into an internal data format.

2. The RAID path switching device in SSD master of claim 1, wherein: the ARBITER module comprises a state machine, a plurality of multiplexers, three groups of last delays, n enabling registers of the core computing control modules and n enabling registers of SRAM;

the command state machine divides each task into two phases, wherein the first phase is the source data inflow and the second phase is the parity data outflow; the multiple multiplexers are gated by path signals and are responsible for gating three paths of source data into one path and gating two paths of read parity addresses into one path;

3. The RAID path switching device in SSD master of claim 1, wherein: the DMA module comprises a command state machine, a data state machine, a frequency counter, a write address conversion, a read address conversion, a write counter, a read counter and a response counter;

4. The RAID path switching device in SSD master of claim 1, wherein: the IMA module comprises a writing state machine, a reading state machine, reading address conversion, writing address conversion, a frequency counter, a writing counter and a reading counter;