CN111143260A

CN111143260A - RAID (redundant array of independent disks) access switching device in SSD (solid State disk) master control

Info

Publication number: CN111143260A
Application number: CN201911406936.3A
Authority: CN
Inventors: 王运哲
Original assignee: Xian Unilc Semiconductors Co Ltd
Current assignee: Xian Unilc Semiconductors Co Ltd
Priority date: 2019-12-31
Filing date: 2019-12-31
Publication date: 2020-05-12
Anticipated expiration: 2039-12-31
Also published as: CN111143260B

Abstract

The invention discloses a RAID channel switching device in SSD master control, which comprises an ARBITER module, a DMA module and an IMA module, wherein the ARBITER module is responsible for completing a specified data channel according to configuration requirements, and the DMA module is responsible for controlling the data interaction of the ARBITER module and an AXI master port, sending a read-write command to the AXI master port and converting an AXI data form into an internal data format; the IMA is responsible for controlling data interaction between the ARBITER module and the AXI slave port, analyzing commands from the AXI slave port and converting the AXI data form into an internal data format. The invention realizes RAID in the SSD main control chip, and can select different paths in different working modes according to the system condition, thereby having strong flexibility.

Description

RAID (redundant array of independent disks) access switching device in SSD (solid State disk) master control

Technical Field

The invention relates to a RAID (redundant array of independent disks) access switching device, in particular to a RAID access switching device in SSD master control.

Background

In reading and writing the SSD, when data is read from the Flash granule, if ECC error correction fails and the read re-try operation fails to read correct data, how to recover the data needs to be considered. RAID technology can fully exploit the array advantages of storage chips, provide fault tolerance to ensure data security, and continue to operate when a problem occurs in a storage unit.

Today's RAID is typically implemented off the SSD host chip. Although the patent "an active acceleration device of RAID in SSD main control" and "a passive acceleration device of RAID in SSD main control" disclose a method for implementing RAID inside an SSD main control chip, both of them are single hardware path designs, and a corresponding path cannot be selected according to application requirements, and the flexibility is poor.

Disclosure of Invention

The technical problem to be solved by the invention is to provide a RAID path switching device in SSD main control, which realizes RAID inside an SSD main control chip, and can select different paths in different working modes according to system conditions, and has strong flexibility.

In order to solve the technical problem, the technical scheme adopted by the invention is as follows: a RAID access switching device in SSD master control comprises an ARBITER module, a DMA module and an IMA module, wherein the ARBITER module is responsible for getting through a designated data access according to configuration requirements, namely one of three data input interfaces is selected to be sent to a core computing control module, one of two data output interfaces is selected to output parity data, the DMA module is responsible for controlling data interaction of the ARBITER module and an AXI master interface, sending a read-write command to the AXI master interface and converting an AXI data form into an internal data format; the IMA is responsible for controlling data interaction between the ARBITER module and the AXI slave port, analyzing commands from the AXI slave port and converting the AXI data form into an internal data format.

Furthermore, the ARBITER module comprises a state machine, a plurality of multiplexers, three groups of last delayers, n enabling registers of the core calculation control module and n enabling registers of the SRAM;

the command state machine divides each task into two stages, wherein the first stage is source data inflow, and the second stage is parity data outflow;

the multiple multiplexers are gated by path signals and are responsible for gating three paths of source data for one path of output and gating two paths of read parity addresses for one path of output;

enabling registers of the n core calculation control modules are used for respectively communicating the data converted by the multi-path selector with the n core calculation control modules according to id information, and gating one path of ack signals fed back by the n core calculation control modules to be fed back to the corresponding modules;

sequentially selecting n paths of SRAMs by the enabling registers of the n SRAMs, and reading back parity data from the SRAMs;

the three sets of last delayers are respectively responsible for delaying the last signals of the private interface, the AXI master port and the AXI slave port by two beats, and then one path of the last delayers is gated to clear the enabling register of the core computation control module through the multi-path selector according to the path signal.

Further, the DMA module comprises a command state machine, a data state machine, a frequency counter, a write address conversion, a read address conversion, a write counter, a read counter and a response counter;

the command state machine comprises three states of IDLE, LOAD and STORE, and sends a corresponding command to the AXI mster bus;

the data state machine comprises six states of IDLE, HDSHK, LOAD, WAIT, STORE and DELY, is linked with the core operation control module and is communicated with the data interaction of AXI MATER and SRAM;

the frequency counter is responsible for accumulating the number of the strips of the inflow data;

the write address conversion is responsible for converting the write count value into a write data block id;

the read address conversion is responsible for converting the read count value into a read data block id;

the write counter is responsible for accumulating the number of source data written into the core operation control module under the LOAD state of the data state machine;

the reading counter is responsible for reading out the parity number from the SRAM in the state of accumulated data state machine STORE;

the response counter is responsible for accumulating response information of AXI _ MST and determining whether the transmission of parity is finished.

Further, the IMA module comprises a writing state machine, a reading state machine, reading address conversion, writing address conversion, a frequency counter, a writing counter and a reading counter;

the writing state machine comprises five states of WIDLE, WWAIT, WCPOP, HDSHK and DPOP, is linked with the core operation control module and controls the source data to flow into the SRAM from the AXI SLAVE port;

the read state machine comprises five states of RIDLE, RWAIT, RCPOP, RCGET, BRDEN and DPUSH, and feeds back parity read from the SRAM to the AXI SLAVE interface;

the write counter is responsible for accumulating the number of source data written into the core operation control module in the DPOP state;

the reading counter is responsible for reading out the parity number from the SRAM in the accumulated DPUSH state.

Further, the internal data format is the same as that of the private interface, namely req/ack, first/last, data/data _ vld and id signal group.

Further, the data input interface of the RAID access includes a private interface, an AXI master port and an AXI slave port, the data output interface of the RAID access includes the AXI master port and the AXI slave port, there are 6 RAID accesses, and these are respectively: private interface to AXI slave port, private interface to AXI master port, AXI master port to AXI master port, AXImmaster port to AXI slave port, AXI slave port to AXI master port.

The invention has the beneficial effects that: the data from the AXI bus is converted into a data format unified with a private interface through the DMA module and the IMA module, so that the core computation control module can process the data conveniently.

The data format is simple, the multi-module state machines execute in parallel, each data is controlled accurately, the data flow is continuous, and the calculation efficiency is fully exerted.

The whole process is divided into an input stage and an output stage, so that six data paths can be freely combined between 3 input interfaces and 2 output interfaces.

Drawings

FIG. 1 is a schematic diagram of an ARBITER module;

FIG. 2 is a schematic diagram of a DMA module;

FIG. 3 is a schematic diagram of an IMA module;

fig. 4 is a diagram of an internal data format.

Detailed Description

The invention is further described with reference to the following figures and specific embodiments.

Example 1

The embodiment discloses a RAID path switching device in SSD master control, which realizes that one of six paths can be selected to flow into and out of a RAID accelerator in one task, the inflow is source data, and the outflow is parity data.

The data input interface of the RAID channel comprises a private interface (private interface), an AXI master interface and an AXIslay interface, and the data output interface of the RAID channel comprises an AXI master interface and an AXI slave interface.

There are 6 RAID paths, which are: private interface to AXI slave port (p2s), private interface to AXI master port (p2m), AXI master port to AXI master port (m2m), AXI master port to AXI slave port (m2s), AXIslave port to AXI slave port (s2s), AXI slave port to AXI master port (s2 m).

The RAID path switching apparatus in this embodiment includes three modules, which are ARBITER, DMA, and IMA. The ARB is responsible for opening a specified data path according to configuration requirements, namely the following two tasks: one is selected from three data input sources and is given to the core calculation control module, and the other is selected from two output ends and is used for outputting the parity data.

The DMA is responsible for controlling data interaction between the ARBITER and the AXI master port, sending a read-write command to the AXI master port and converting the AXI data form into an internal data format. The IMA is responsible for controlling data interaction between the ARBITER and the AXI slave port, analyzing commands from the AXI slave port and converting the AXI data form into an internal data format.

The internal data format is the same as that of the private interface, and is a req/ack, first/last, data/data _ vld and id signal group, so that the processing of the core calculation control module is facilitated.

In one task, the ARBITER, the DMA (m2 x), the IMA (s2 x), the core computation control module and the SRAM are linked to realize the pipelined XOR processing of data, when the data flow is completed, the parity generation is completed, and then the parity is fed back to the AXI bus through the DMA (x 2m) or the IMA (x2s) according to the requirement. Wherein x represents m or s.

As shown in fig. 1, 2, and 3, which are schematic structural diagrams of the ARBITER module, the DMA module, and the IMA module, respectively, in the diagrams, a signal prefixed by c _ represents an interaction signal between the RBITER and the core computation control module, a signal prefixed by p _ represents an interaction signal between the RBITER and the NFC private interface, a signal prefixed by m _ represents an interaction signal between the RBITER and the DMA, a signal prefixed by s _ represents an interaction signal between the RBITER and the IMA, a signal prefixed by buf _ represents an interaction signal between the RBITER and the SRAM, and a signal prefixed by [ n ] represents an interaction signal between the ARBITER and n core computation control modules or an interaction signal between the ARBITER and n (buffers).

As shown in FIG. 1, the ARBITER module comprises a state machine, nine multiplexers (MUX 0-MUX 9), three sets of last delayers (D1D 2, D3D4, D5D 6), n enable registers of the core computation control module (STEP 1_ CH _ EN [ n ]) and n enable registers of the SRAM (STEP 2_ CH _ EN [ n ]).

As shown in FIG. 2, the DMA module includes a command state machine, a data state machine, read address translations, write address translations, a count counter, a read counter, and a write counter.

As shown in fig. 3, the IMA module includes a write state machine, a read address translation, a write address translation, a number counter, a read counter, and a write counter.

The effect of each component in the ARBITER module is as follows:

the command state machine divides each task into two phases, the first phase is source data streaming in, and the second phase is parity data streaming out.

The path-gated multiplexers are responsible for converting three paths of source data into one path (including signals in the internal data format) and converting two paths of read parity addresses into one path (buf _ addr).

STEP1_ CH _ EN [ n ] connects the data converted by the multiplexer (each signal of the internal data format) with the n-way core operation control module according to the id information, and gates one way of ack signal fed back by the n-way core operation module to feed back to the corresponding module (p/m/s).

STEP2_ CH _ EN [ n ] will in turn select n ways of SRAMs (buf _ data [ n ]), from which parity data is read back.

The three-way last delayer (p/m/s) is responsible for delaying each way of last signals for two beats (because the intermediate calculation result in the core calculation module is that two beats are delayed to enter the SRAM), and then one way is selected by the multi-way selector according to the path to clear STEP1_ CH _ EN [ n ].

The DMA module is used for processing tasks with path types of m2x or x2m, and the functions of the components are as follows:

the command state machine comprises three states (C _ is a prefix) of IDLE IDLE, LOAD command LOAD sending and STORE command STORE sending corresponding commands to AXI mster bus.

The data state machine comprises six states (D _ is a prefix) of IDLE IDLE, handshake HDSHK, loading source data LOAD, waiting WAIT, storing parity data STORE and delaying DELY, and is linked with the core operation control module to communicate the data interaction of AXI MATER and SRAM.

The number counter is responsible for accumulating the number of stripes of the incoming data.

Write address translation is responsible for converting the write count value to the write data block id.

The read address translation is responsible for translating the read count value into a read data block id.

And the write counter is responsible for accumulating the number of the source data written into the core operation control module under the D _ LOAD state.

The read counter is responsible for reading out the parity number from the SRAM in the D _ STORE state.

The response counter is responsible for accumulating response information of AXI _ MST to determine whether the transmission of parity is finished.

The IMA module is used for processing tasks with path types of s2x or x2s, and the functions of the components are as follows:

the write state machine comprises five states of idle WIDLE, waiting for a write command WWAIT, a write command popup WCPOP, a handshake HDSHK and a source data popup DPOP, is linked with the core operation control module and controls the source data to flow into the SRAM from the AXI SLAVE port.

The read state machine comprises five states of idle RIDLE, waiting read command RWAIT, read command popping RCPOP, read command parsing RCGET, BUF read enable BRDEN and parity data pressing DPUSH, and the parity read from the SRAM is fed back to the AXI SLAVE interface.

And the write counter is responsible for accumulating the number of source data written into the core operation control module in the DPOP state.

The following describes the operation of the RAID path switching apparatus with P2S and M2M as examples.

The working process in the P2S working mode is as follows:

1. after start, arbiters enter STEP1 state from IDLE and ima's read state machine enters RWAIT state from RIDLE.

2. And the data on the P port sequentially and circularly enters the n core operation control modules through the multipath selection in the arbiter, and the n core operation control modules sequentially feed back c _ finish signals to the arbiter after the data is counted and operated.

3. Arbiter takes all c _ finish and generates the s1_ finish signal output and enters the STEP2 state. And after the external NFC is brought to s1_ finish, a read command is sent to an AXI _ slave interface through an AXI bus.

4. After detecting a read command, the read state machine of Ima enters a DPUSH state through RCPOP, RCGET and BRDEN states in sequence, gives a read address in the state, converts the read address into id through read address conversion and gives the id to the arbiter, and the id is linked with STEP2_ CH _ EN and n SRAMs in the arbiter to open a channel from the n SRAMs to AXI _ RDATA and feed back parity to an AXI bus.

5. After completion of the read count in Ima, an s _ finish signal is generated to arbiters and back to the RIDLE state, and arbiters also return to the IDLE state. This p2s task ends.

The working process in the M2M working mode is as follows:

1. after start, arbiters enter the STEP1 state from IDLE, dma's command state machine enters the C LOAD state from C IDLE, and data state machine enters the D HDSHK state from D IDLE.

2. dma sends a read command to the AXI bus in the C LOAD state. After the data of the bus comes, dma and the arbiter, N core operation control modules are linked to open the data channels from the bus to the N SRAMs, and at the moment, the data state machine enters the circulation of D _ LOAD and D _ HDSHK. And communicating the bus data with the arbiter in the D _ LOAD state, communicating the bus data with the corresponding core operation control module according to the current m _ wr _ id multiplexer, and writing the intermediate operation result into the corresponding SRAM. And sending m _ req to the next core operation control module in the D _ HDSHK state, completing handshaking after ack is obtained, and correspondingly changing m _ wr _ id. And circulating the above steps until the time _ cnt counting in the dma is finished, enabling the data state machine to enter a D _ WAIT state, and simultaneously feeding back c _ finish signals to the arbiter in sequence after the n core operation control modules complete counting.

3. Arbiter takes all c _ finish and generates the s1_ finish signal output and enters the STEP2 state. When dma gets to s1 finish, the dma's command state machine enters the C _ STORE state, sending a write command to the AXI bus.

4. dma and arbiters are linked to open a data channel from the n SRAMs to the bus, and the data state machine of dma enters a cycle of two states, D _ STORE and D _ DELY. Dma switches the read address in the D _ DELY state while converting it to id to the arbiter by read address translation. In the D _ STORE state, the arbiter generates STEP2_ CH _ EN according to m _ rd _ id to gate a corresponding SRAM, and feeds back read parity data to a bus read data channel through dma.

5. After the end of the resp _ cnt count in dma (slave with the des _ addr has taken the parity data), an m _ finish signal is generated to arbiter and goes back to D _ IDLE state, and arbiter also goes back to IDLE state. And ending the task.

As shown in fig. 4, the data format is a data transmission (recovery) process.

The invention converts the data from AXI bus into the data format unified with the private interface through the DMA module and the IMA module, which is convenient for the core computing control module (see the above patent) to process the data.

The foregoing description is only for the basic principle and the preferred embodiments of the present invention, and modifications and substitutions by those skilled in the art are included in the scope of the present invention.

Claims

1. A RAID path switching device in SSD master control is characterized in that: the system comprises an ARBITER module, a DMA module and an IMA module, wherein the ARBITER module is responsible for getting through a specified data channel according to configuration requirements, namely one of three data input interfaces is selected to be sent to a core computing control module, one of two data output interfaces is selected to output parity data, the DMA module is responsible for controlling data interaction between the ARBITER module and an AXI master port, sending a read-write command to the AXI master port and converting an AXI data form into an internal data format; the IMA is responsible for controlling data interaction between the ARBITER module and the AXI slave port, analyzing commands from the AXI slave port and converting the AXI data form into an internal data format.

2. The apparatus for switching RAID lanes in SSD master control of claim 1, wherein: the ARBITER module comprises a state machine, a plurality of multiplexers, three groups of last delayers, enabling registers of n core calculation control modules and enabling registers of n SRAMs;

the multiple multiplexers are gated by path signals and are responsible for gating one path of the three paths of source data and one path of the two paths of read parity addresses;

3. The apparatus for switching RAID lanes in SSD master control of claim 1, wherein: the DMA module comprises a command state machine, a data state machine, a frequency counter, write address conversion, read address conversion, a write counter, a read counter and a response counter;

4. The apparatus for switching RAID lanes in SSD master control of claim 1, wherein: the IMA module comprises a writing state machine, a reading state machine, reading address conversion, writing address conversion, a frequency counter, a writing counter and a reading counter;

5. The apparatus for switching RAID lanes in SSD master control of claim 1, wherein: the internal data format is the same as that of the private interface, namely req/ack, first/last, data/data _ vld and id signal groups.

6. The apparatus for switching RAID lanes in SSD master control of claim 1, wherein: the data input interface of the RAID access comprises a private interface, an AXI master port and an AXI slave port, the data output interface of the RAID access comprises an AXI master port and an AXI slave port, the number of the RAID access is 6, and the number of the RAID access is respectively as follows: private interface to AXI slave port, private interface to AXI master port, AXI master port to AXI slave port, AXI slave port to AXI master port.