CN101317186B - 应答机及其制造方法 - Google Patents
应答机及其制造方法 Download PDFInfo
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Abstract
在制造应答机(T1,T2,T3)的方法中,提供了基板(1,91)。基板(1,91)包括第一区域(2)、与第一区域(2)毗邻的第二区域(3)、和与第二区域(3)毗邻的第一电触点(8,98)。在第一区域(2)上或第一区域(2)中布置电器件(50,80),优选地不接触第一电触点(8,98)。随后,在第二区域(3)上和第一电触点(8,98)上涂敷导电胶(12),以便导电胶(12)对第一电触点(8,98)和电器件(50,80)进行电耦接。
Description
技术领域
本发明涉及一种应答机(transponder)及其制造方法。
背景技术
美国专利6,867,983B2公开了一种应答机形式的电路,它被称为射频识别(RFID)应答机,该应答机被用作RFID标识或标记。该标识或标记包括器件基板(其上形成了具有两个终端的天线)和带状基板。在制造标识或标记时,首先在器件基板上形成天线,随后在天线终端上放置导电粘合剂。通过FSA工艺将微结构元件放置在带状基板的凹进部中,并且在带状基板上镀上引线。最后,以带状基板的引线与天线终端接触的形式将带状基板安装在器件基板上,从而将天线与微结构耦接起来。
发明内容
本发明的目的是提供一种制造应答机的方法,该方法能以简单方式将应答机的电器件附着至基板上。
根据本发明,该目的由一种制造应答机的方法所实现,所述方法包括以下步骤:提供基板,该基板包括第一区域、与第一区域毗邻的第二区域、和附着在基板上并与第二区域毗邻的第一电触点;在第一区域上或第一区域中布置电器件;以及在第二区域上和/或第一电触点上涂敷导电胶,以便导电胶将第一电触点和电器件电耦接起来。根据现有技术,一般用以下步骤制造应答机:首先将导电胶涂敷在基板上,随后将电器件放置在基板上。那么,该电器件很容易浮在导电胶上,从而在导电胶固化期间需要特殊装置将该电器件按压在基板上。而根据本发明,首先将电器件(它可能是集成电路)放置在第一区域内或其上,随后再将导电胶涂敷在第二区域和第一电触点上。因此,该电器件不大可能浮在导电胶上,并且可以在不需要特殊器件将该电器件按压在基板上的情况下进行固化。可通过在基板上形成第一电触点来将第一电触点附着在基板上。可通过多种合适的方法中的任意一种来形成第一电触点,例如印制导电油墨、电镀、或者选择性金属淀积的其它方法。
根据优选替换例,在不与第一电触点接触的情况下,将电器件放置在第一区域上或第一区域中。这样处理之后,避免了或者至少减少了触点和电器件之间不希望的杂散电容。但是,所述电器件可能也会覆盖所述第二区域,甚至至少部分地覆盖第一电触点。
在将电器件放置在基板上之前,对基板进行调整,从而使得第一区域具有第一浸润性,并且第二区域具有强于第一浸润性的第二浸润性。第一区域优选地被调整成它甚至排斥导电胶,而第二区域优选地被调整成吸附导电胶。适当地构建基板,可获得基板的不同程度的浸润性。在基板的制造过程中,可通过适当的表面处理(诸如等离子或电晕处理)、压印技术(诸如纳米压印)、通过其它材料层的合成、溅射工艺、气相沉积工艺、或在各个区域上印制具有各种浸润性的层、或者涂敷硅层来获得基板的第一和第二区域。基板的合适材料包括聚碳酸酯、聚氯乙烯、聚对苯二甲酸乙二醇酯(PET)或者甚至是陶瓷或者纸。特别地,如果基板是由具有相对较强的浸润性的材料(诸如PET)制成的,那么只需要利用例如上述技术中的一种技术来处理第一区域,以便第一区域具有第一浸润性。由于第一电触点优选地由金属材料制成,所以其相关区域可固有地具有相对较强的浸润性。否则,必须对第一电触点的表面进行适当处理。
在该发明方法的限制版本中,电器件具有下表面、上表面、以及多个侧面,该侧面中的至少一个侧面包括电触点。由于电器件的电触点位于侧面上,最好以使包括电触点的侧面朝向所述第一电触点的方式将电器件放置在第一区域内或其上。因此,没有必要让导电胶流进电器件底部,这就降低了制成的应答机的高度。电触点还可以处于电器件的上表面。
至少朝向第一电触点的侧面相对于电器件的下表面倾斜。这提高了基板上的电器件的粘结。特别地,如果导电胶部分地涂敷在电器件的上表面,则可实现形状配合(form-fit)。此外,在组装器件过程中,电器件被推向基板,这是由于作用在倾斜侧壁52、54上的导电胶的表面张力和/或重量产生了朝向基板1的分力。最后,当器件弯曲时,电器件较不容易断裂。但是,下表面也可具有与上表面相同的尺寸,或者小于上表面的尺寸。
在该发明方法的另一限制版本中,基板包括与所述第一区域毗邻的第三区域以及附着在基板上的与第三区域毗邻的第二电触点。优选地,以第三区域具有第三浸润性,并且第一浸润性比第二浸润性和第三浸润性要弱的方式对将要布置的基板进行调整。虽然已经例举了至多只包括两个触点的实施例,但是对于本领域技术人员而言显然的是,理论上,本发明适用于具有多于两个触点的器件。
基板可具有附于其上的天线,并且天线可包括至少一个由电触点所表示的天线终端。但是,基板也可为第一基板,并且本发明的方法可包括以下附加步骤:将第一基板安装在第二基板上,具有至少一个天线终端的天线附着在第二基板上;以及将第一基板与该至少一个天线终端电耦接起来。
如果天线被附在基板上,那么通过发明方法制造出来的所发明的应答机可包括第二电触点,并且天线可具有第一和第二接触端。那么,第一接触端表示第一电触点,而第二接触端表示第二电触点。基板可具有浸润性相对较强的第二和第三区域,从而优选地使这些区域吸附导电胶。具有相对较弱的浸润性的第一区域被置于第二和第三区域之间。在所发明的应答机的这一版本中,可以以将电器件放置在天线的两个终端之间的第一区域中或其上的方式设计这些区域和天线。一方面,由于第一区域比其它部分具有更弱的浸润性,所以导电胶至少在很大程度上仅湿润了第二和第三部分以及两个电触点。另一方面,尤其是如果电器件被至少部分地放置在基板的第二和第三区域上,导电胶还将分别接触并粘附在与第一和第二天线相对的侧面。由于放置在第二和第三区域上的导电胶的表面张力(在倾斜侧面的情况下,还由于重量),导电胶将自动把电器件移至中间,或者至少一定程度上使其靠近中央。这就简化了制造所发明的应答机的工艺,这是因为在组装所发明的应答机的时候,它缓解了电器件的精确居中问题。此外,由于导电胶使电器件自动居中,或者至少一定程度上使其靠近中央,所以在导电胶的硬化或固化过程中并不需要对电器件进行外部固定。为了避免或者至少降低不希望的杂散电容,电器件优选地使得两个天线终端不重叠。
通过参考下文中描述的实施例,本发明的这些和其它方面将得到说明并变得明显。
附图说明
参考附图中所示的实施例,通过非限制性的示例,在下文将对本发明进行更加详细地描述。
图1示出了用于应答机第一示例的基板;
图2至图4图示说明了制造第一应答机的工艺;
图5和图6示出了用于图2至图4中所描绘的第一应答机的集成电路示例的不同侧面;
图7是第一应答机的侧视图;
图8是应答机第二示例的侧视图;
图9和图10示出了制造应答机第三示例的步骤。
具体实施方式
图1是用于制造应答机T1第一示例的基板1的俯视图,其制造工艺在图1至图4予以示出。图4和图7描绘了应答机T1。基板1由聚对苯二甲酸乙二醇酯(PET)制成,并且基板1的上表面具有相对较强的浸润性,以便在所示实施例中它可更好地吸附导电胶。下文中将参照导电胶。但是,可选地,可在本发明的实施例中使用焊料。对于应答机T1的制造,首先在溅射工艺期间构建基板1。在溅射工艺过程中,基板1的上表面上形成了具有相对较弱的浸润性的区域2,以使之与前述导电胶不相吸附。此外,在基板1上形成其它区域3和4。在所示的实施例中,这些区域3、4基本上是未处理过的,但是它们被沟槽5、6所限制,这些沟槽是蚀刻或者印制在示出的基板1的上表面中的。于是,区域3、4的浸润性比区域2强,并且区域3、4甚至能够吸附前述导电胶。具有相对较弱的浸润性的区域2毗邻具有相对强的浸润性的区域3、4并且处于它们之间。
如图2所示,在所构建的基板1上表面上形成了天线7。在该实施例中,天线7具有第一电接触端8和第二电接触端9,并且采用已知的电镀工艺来将天线7镀在基板1的上表面上。两个天线接触端8、9都具有区域10、11,这些区域的浸润性相对较强,以便它们能够吸附前述导电胶(通常,区域10、11与天线接触端8、9处于相同位置。但是这并不是本发明的强制特征)。此外,第一接触端8的区域10与具有相对较强的浸润性的区域3邻接,并且与具有相对较弱的浸润性的区域2远离。第二接触端9的区域11与具有相对较强的浸润性的区域4邻接,并且与具有相对较弱的浸润性的区域2远离。
在图3所示的随后的制造步骤中,电器件(在该实施例中为集成电路50)被放置在具有相对较弱的浸润性的区域2上。图5和图6对该集成电路50进行了更详细的描绘。
在该实施例中,集成电路50具有棱锥形形状并且包括上表面51、第一侧面52、第二侧面53、第三侧面54、第四侧面55、以及图中未示出的下表面。由于在该实施例中集成电路50具有棱锥形形状,所以侧面52、53、54、55相对于下表面倾斜。侧面52与侧面54相对。第一侧面52包括第一电接点56,第三侧面54包括第二电接点57,接点用于与集成电路50进行电接触。
以包括第一电接点56的第一侧面52朝向第一天线接点8,而包括第二电接点57的第三侧面54朝向第二天线接点9的方式,将集成电路50放置在具有相对较弱的浸润性的区域2上。并且,集成电路50的下表面的大小是这样设置的:其被放置在具有相对较弱的浸润性的区域2上时,与具有相对较强的浸润性的两个区域3、4部分重叠,同时不触及天线触点8、9。
如图4所示,在将集成电路放置在具有相对较弱的浸润性的区域2上并且将其部分地放置在具有相对较强的浸润性的两个区域3、4上以后,将导电胶涂敷在具有相对较强的浸润性的两个区域3、4以及天线接触端8、9上。由于基板1的区域2具有相对较弱的浸润性,而基板1的区域3、4以及两个天线接触端8、9的区域10、11具有相对较强的浸润性,所以基本上只有区域3、4、10、11被导电胶12湿润。此外,导电胶12达到了侧面52和54,覆盖了集成电路50的第一和第二电触点56、57,从而将集成电路50点耦接至天线7。图7是应答机T1的侧视图。
导电胶12具有一定的表面张力及一定的重量。因此,导电胶12在湿润时基本上将集成电路50放置在了两个天线接点8、9中间。于是,集成电路50的下表面部分地覆盖了具有相对较强的浸润性的两个区域3、4,但是并不接触天线7的两个天线接触端10、11。此外,由于导电胶12的表面张力和/或重量在倾斜侧壁52、54上起作用而产生了朝向基板1的分力,从而使集成电路50被推向基板1。
在图1至图7所示的实施例中,应答机T1的集成电路50为棱锥形形状,其中下表面大于上表面51。这种集成电路还可以是上表面大于下表面的。还可以使用其它形状的集成电路。图8示出了具有不同形状的集成电路80的应答机T2的实施例。集成电路80为矩形。
图9示出了应答机T3的实施例。应答机T3的组件中与图1至图7中的应答机T1中的相同组件具有相同的标号。
应答机T3包括插入基板(interposer substrate)91和主基板92。在所示的实施例中,两个基板91和92都由PET制成。主基板92配置有天线93,该天线是通过在主基板92上印制导电油墨来形成的。天线93具有第一接触端94和第二接触端95。
图10更加详细地示出了插入基板91,其结构类似于应答机T1的基板1。因此,插入基板91具有处于具有相对较强的浸润性的两个区域3、4之间的具有相对较弱的浸润性的区域2。如图10所示,利用公知的电镀工艺在插入基板91的上表面上形成了第一电触点98和第二电触点99。触点98、99中的每一个触点都具有浸润性相对较强的区域110、111,以便它们能吸附导电胶(通常,区域110、111与天线接触端98、99处于相同位置,但是这并不是本发明的强制特征)。此外,第一电触点98的区域110与具有相对较强的浸润性的区域3邻接,并且与具有相对较弱的浸润性的区域2远离。第二接触端99的区域111与具有相对较强的浸润性的区域4邻接,并且与具有相对较弱的浸润性的区域2远离。
在制造应答机T3时,集成电路50被放置在区域2上,并且导电胶12被涂敷在区域3、4、110、111上,以便将集成电路50电耦接至电触点98、99。包括集成电路50的插入基板91随后被安装至主基板92上,并且天线93的第一接触端94与插入基板91的第一电触点98电耦接。同样地,天线93的第二接触端95与插入基板91的第二电触点99电耦接。
应该注意的是,本发明适用于具有环形天线、偶极天线、或单极天线的应答机,也适用于具有任何其它天线的应答机。此外,本发明不仅适用于应答机,而且适用于其它附着在基板上的优选地具有两个连接头的电子器件。示例为LED(有源部分)、开关(机电部分)、电阻器、电容器、以及线圈(无源部分)。对于本领域技术人员而言,,这明显不是一个穷尽列表,而是可以很容易地找出其它替换示例。还应该注意的是,本发明还涉及具有多于一个或两个连接头的电子器件,例如放大器。
最后,应该注意的是,上述实施例说明了而不是限制了本发明,并且本领域技术人员将能在不脱离所附权利要求中限定的范围的情况下设计出多种替换实施例。在权利要求中,括号中的任何标号都不应该被解释为限制权利要求。词语“包括”及类似词语的使用并不排除除了权利要求中所陈述的元素和步骤之外其它元素和步骤的存在。单个元素的使用并不排除多个该元素的存在,反之亦然。在列举了多个装置的装置权利要求中,这些装置中的多个可通过同一种硬件实现。事实仅仅在于,在相互不同的从属权利要求中陈述的某些方法并不表示不能利用这些方法的结合来获得优势。
Claims (13)
1.一种制造应答机(T1,T2,T3)的方法,所述方法包括以下步骤:
提供基板(1,91),该基板包括第一区域(2)、与所述第一区域(2)毗邻的第二区域(3)、和附着在所述基板(1,91)上并与所述第二区域(3)毗邻的第一电触点(8,98);
对所述基板(1,91)进行调整,以便使所述第一区域(2)具有第一浸润性,并且所述第二区域(3)具有强于所述第一浸润性的第二浸润性;
在所述第一区域(2)上或所述第一区域(2)中布置电器件(50,80)以及
在所述第二区域(3)上和/或所述第一电触点(8,98)上涂敷导电胶(12),以便所述导电胶(12)对所述第一电触点(8,98)和所述电器件(50,80)进行电耦接。
2.如权利要求1所述的方法,其中将所述电器件(50,80)在不与所述第一电触点(8,98)接触的情况下布置在所述第一区域(2)中或所述第一区域(2)上。
3.如权利要求1所述的方法,其包括以下步骤:在不将所述电器件(50,80)按压在所述基板(1,91)上的情况下对所述导电胶(12)进行固化。
4.如权利要求1所述的方法,其包括以下步骤:把所述电器件(50,80)布置在所述第一区域(2)中或所述第一区域(2)上并且至少部分地处于所述第二区域(3)上。
5.如权利要求1所述的方法,其中,所述电器件(50)具有下表面、上表面(51)、以及多个侧面(52-55),这些面中的至少一个面包括电触点(56,57);所述方法包括以下步骤:以包括所述电触点(56)的所述侧面(52)朝向所述第一电触点(8,98)的方式将所述电器件(50)布置在所述第一区域(2)中或所述第一区域(2)上。
6.如权利要求5所述的方法,其中,至少朝向所述第一电触点(8,98)的所述侧面(52)相对于所述电器件(50)的下表面倾斜。
7.如权利要求1所述的方法,其包括以下步骤:将所述导电胶(12)至少部分地涂敷在所述电器件(50,80)上。
8.如权利要求1所述的方法,其中,所述基板(1,91)包括与所述第一区域(2)毗邻的第三区域(4)以及附着在所述基板(1,91)上的与所述第三区域(4)毗邻的第二电触点(9,99)。
9.如权利要求8所述的方法,其包括以下步骤:对将要提供的所述基板(1,91)进行调整,以便使所述第三区域(4)具有第三浸润性,并且所述第一浸润性比所述第二浸润性和所述第三浸润性要弱。
10.如权利要求8所述的方法,其中,所述基板(1)具有附于其上的天线(7),并且所述天线(7)包括至少一个天线终端,该终端由所述第一电触点(8)表示。
11.如权利要求1所述的方法,其中,所述基板为第一基板(91),所述方法包括以下附加步骤:
将所述第一基板(91)安装在第二基板(92)上,具有至少一个天线终端(94)的天线(93)附着在所述第二基板(92)上;以及
将所述第一电触点(98)与所述至少一个天线终端(94)进行电耦接。
12.一种应答机,包括:
基板(1,91),该基板包括第一区域(2)、与所述第一区域(2)毗邻的第二区域(3)、和附着在所述基板(1,91)上并与所述第二区域(3)毗邻的第一电触点(8,98);
所述基板(1,91)被调整为使所述第一区域(2)具有第一浸润性,并且所述第二区域(3)具有强于所述第一浸润性的第二浸润性;
所述基板(1,91)还包括与所述第一区域(2)毗邻的第三区域(4)以及附着在所述基板(1,91)上的与所述第三区域(4)毗邻的第二电触点(9,99);
所述基板(1)具有附于其上的天线(7),并且所述天线(7)包括至少一个天线终端,该天线终端由所述第一电触点(8)表示;
电器件(50,80),其布置在所述第一区域(2)上或所述第一区域(2)中;以及
导电胶(12),涂敷在所述第二区域(3)上和/或所述第一电触点(8,98)上,以便所述导电胶(12)对所述第一电触点(8,98)和所述电器件(50,80)进行电耦接。
13.一种应答机,包括:
第一基板(91),第一基板包括第一区域(2)、与所述第一区域(2)毗邻的第二区域(3)、和附着在所述第一基板(91)上并与所述第二区域(3)毗邻的第一电触点(98);
所述第一基板(91)被调整为使所述第一区域(2)具有第一浸润性,并且所述第二区域(3)具有强于所述第一浸润性的第二浸润性;
电器件(50,80),布置在所述第一区域(2)上或所述第一区域(2)中;以及
导电胶(12),涂敷在所述第二区域(3)上和/或所述第一电触点(98)上,以便所述导电胶(12)对所述第一电触点(98)和所述电器件(50,80)进行电耦接;
所述第一基板(91)安装在第二基板(92)上,具有至少一个天线终端(94)的天线(93)附着在所述第二基板(92)上;以及
所述第一电触点(98)与所述至少一个天线终端(94)电耦接。
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6091332A (en) * | 1998-06-09 | 2000-07-18 | Motorola, Inc. | Radio frequency identification tag having printed circuit interconnections |
US6107920A (en) * | 1998-06-09 | 2000-08-22 | Motorola, Inc. | Radio frequency identification tag having an article integrated antenna |
CN1340165A (zh) * | 1999-02-09 | 2002-03-13 | 马格纳斯·格兰赫德 | 无源发射应答机中的密封天线 |
US6404643B1 (en) * | 1998-10-15 | 2002-06-11 | Amerasia International Technology, Inc. | Article having an embedded electronic device, and method of making same |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5255839A (en) | 1992-01-02 | 1993-10-26 | Motorola, Inc. | Method for solder application and reflow |
US6864570B2 (en) | 1993-12-17 | 2005-03-08 | The Regents Of The University Of California | Method and apparatus for fabricating self-assembling microstructures |
IL108359A (en) | 1994-01-17 | 2001-04-30 | Shellcase Ltd | Method and device for creating integrated circular devices |
US5468999A (en) | 1994-05-26 | 1995-11-21 | Motorola, Inc. | Liquid encapsulated ball grid array semiconductor device with fine pitch wire bonding |
US5798146A (en) * | 1995-09-14 | 1998-08-25 | Tri-Star Technologies | Surface charging to improve wettability |
JP3003624B2 (ja) | 1997-05-27 | 2000-01-31 | ソニー株式会社 | 半導体装置 |
FR2769389B1 (fr) | 1997-10-07 | 2000-01-28 | Rue Cartes Et Systemes De | Carte a microcircuit combinant des plages de contact exterieur et une antenne, et procede de fabrication d'une telle carte |
EP1110243A1 (de) | 1998-07-28 | 2001-06-27 | Infineon Technologies AG | Integriertes bauelement, verbundkörper aus einem integrierten bauelement und einer leiterstruktur, chip-karte und verfahren zur herstellung des integrierten bauelementes |
US6891110B1 (en) * | 1999-03-24 | 2005-05-10 | Motorola, Inc. | Circuit chip connector and method of connecting a circuit chip |
AU2001253622A1 (en) | 2000-04-14 | 2001-10-30 | Karl Reimer | Apparatus and method for continuous surface modification of substrates |
CN1498417A (zh) | 2000-09-19 | 2004-05-19 | 纳诺皮尔斯技术公司 | 用于在无线频率识别装置中装配元件和天线的方法 |
US6867983B2 (en) | 2002-08-07 | 2005-03-15 | Avery Dennison Corporation | Radio frequency identification device and method |
JP3808030B2 (ja) | 2002-11-28 | 2006-08-09 | 沖電気工業株式会社 | 半導体装置及びその製造方法 |
FI20022107A (fi) * | 2002-11-29 | 2004-05-30 | Rafsec Oy | Menetelmä sirujen kiinnittämiseksi transponderiin |
US6940408B2 (en) * | 2002-12-31 | 2005-09-06 | Avery Dennison Corporation | RFID device and method of forming |
EP1460690A1 (en) | 2003-02-25 | 2004-09-22 | Broadcom Corporation | Optimization of routing layers and board space requirements in a BGA package (fka BGA package) |
DE10308855A1 (de) | 2003-02-27 | 2004-09-16 | Infineon Technologies Ag | Elektronisches Bauteil und Halbleiterwafer, sowie Verfahren zur Herstellung derselben |
-
2006
- 2006-11-23 DE DE602006020179T patent/DE602006020179D1/de active Active
- 2006-11-23 CN CN2006800441188A patent/CN101317186B/zh active Active
- 2006-11-23 US US12/095,147 patent/US8968510B2/en active Active
- 2006-11-23 AT AT06831913T patent/ATE498872T1/de not_active IP Right Cessation
- 2006-11-23 EP EP06831913A patent/EP1966743B1/en active Active
- 2006-11-23 WO PCT/IB2006/054408 patent/WO2007060631A1/en active Application Filing
- 2006-11-23 JP JP2008541892A patent/JP2009517730A/ja not_active Withdrawn
-
2015
- 2015-01-28 US US14/607,517 patent/US9779349B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6091332A (en) * | 1998-06-09 | 2000-07-18 | Motorola, Inc. | Radio frequency identification tag having printed circuit interconnections |
US6107920A (en) * | 1998-06-09 | 2000-08-22 | Motorola, Inc. | Radio frequency identification tag having an article integrated antenna |
US6404643B1 (en) * | 1998-10-15 | 2002-06-11 | Amerasia International Technology, Inc. | Article having an embedded electronic device, and method of making same |
CN1340165A (zh) * | 1999-02-09 | 2002-03-13 | 马格纳斯·格兰赫德 | 无源发射应答机中的密封天线 |
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EP1966743B1 (en) | 2011-02-16 |
US8968510B2 (en) | 2015-03-03 |
DE602006020179D1 (de) | 2011-03-31 |
JP2009517730A (ja) | 2009-04-30 |
US20150144704A1 (en) | 2015-05-28 |
US20080309462A1 (en) | 2008-12-18 |
US9779349B2 (en) | 2017-10-03 |
WO2007060631A1 (en) | 2007-05-31 |
EP1966743A1 (en) | 2008-09-10 |
CN101317186A (zh) | 2008-12-03 |
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