CN101305464A - 芯片组件和制造芯片组件的方法 - Google Patents

芯片组件和制造芯片组件的方法 Download PDF

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Publication number
CN101305464A
CN101305464A CNA2006800419432A CN200680041943A CN101305464A CN 101305464 A CN101305464 A CN 101305464A CN A2006800419432 A CNA2006800419432 A CN A2006800419432A CN 200680041943 A CN200680041943 A CN 200680041943A CN 101305464 A CN101305464 A CN 101305464A
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Prior art keywords
chip
assembly
side surfaces
liner
contact pad
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CN100592513C (zh
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N·J·A·范维恩
R·德克
C·C·塔克
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Koninklijke Philips NV
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Koninklijke Philips Electronics NV
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Abstract

一种第一芯片(100)和第二芯片(200)的组件，这种组件的第一芯片(100)具有柔性并在芯片(100)的相对侧面(1、2)上设有第一树脂层(12)和第二树脂层(52)，这种组件允许将第一芯片保持在压缩状态，第一侧面接触衬垫(33)和第二侧面接触衬垫(31)分别处于第一侧面(1)和第二侧面(2)上，这些第一侧面接触衬垫(33)耦接到对应的第二芯片(200)的接触衬垫(211)，且这些第二侧面接触衬垫(31)设计用于这种组件的外部连接。

Description

芯片组件和制造芯片组件的方法
技术领域
本发明涉及一种第一芯片和第二芯片的组件。
本发明还涉及制造第一芯片和第二芯片的组件的方法，这种方法包括以下步骤：
将第一晶片附接到载体，这种第一晶片具有半导体基板，这种基板带有多个这种第一芯片；
将这种半导体基板变薄：
将第二晶片附接到第一晶片的变薄的半导体基板，这种第二晶片具有半导体基板，这种基板带有多个这种第二芯片；以及
将接触衬垫打开以启动至这种组件的外部连接。
背景技术
可从US6,506,664获知这种组件和这种方法。这种已知文献的图6公开了一种特别适用于三维存储单元的实施方式。通过一种分离层(release layer)将具有半导体基板和在半导体基板上的主动和/或被动器件的经过完全处理的第一晶片附接到载体，然后用常规技术将这种第一晶片变薄，这些常规的技术如化学或机械研磨和/或抛光。之后，利用附着层将第二晶片附接到第一晶片的变薄侧面。选择一种聚合附着层用于这种附着层，这种聚合附着层如通过加热软化的BCB。然后将第二晶片变薄，以使其厚度达到5至25微米。将这种附接和变薄工艺重复以获得器件层堆叠，这些器件层与附着层相互附接并经由分离层附接到载体。将这种堆叠进一步加热到120℃的温度以烘烤这些附着层并使这些附着层对抗溶剂，如丙酮。在将载体取下之后，将这种堆叠进行烘烤以将这些附着层完全交叉联接(cross-link)。最后形成贯穿这种堆叠的所有层的凹槽，这种凹槽允许接近设计用在这种堆叠的层中的所有结合衬垫。然后，这种凹槽可设有金属喷镀，以接触这些结合衬垫。
已知组件的缺陷在于穿过凹槽的触点的提供是一种要求金属喷镀的最低分辨率的工艺。而且，这种工艺要求特定设计，以将这些结合衬垫充分地布置在单层中且可将足够的结合衬垫在单层中暴露。
发明内容
因此，本发明的一种目的在于提供一种组件，在这种组件中，组件至如一种外部载体的耦接得到改进尤其是简化，这样就无需凹槽。
由于第一芯片具有柔性并在该芯片的相对侧面设有第一树脂层和第二树脂层，这就允许将第一芯片保持在压缩状态，第一侧面接触衬垫和第二侧面接触衬垫分别处于第一侧面和第二侧面，第一侧面接触衬垫耦接到第二芯片的对应的接触衬垫，且第二侧面接触衬垫设计用于这种组件的外部连接，所以就能够实现目的。
在本发明中，通过在第一芯片的两相对侧面上均提供接触衬垫来避免凹槽的使用。这样就可从第一芯片的第二侧面接触衬垫接触这种组件。实际上，将第一芯片的这些第二侧面接触衬垫类似于单芯片的接触衬垫定位，这就意味着无需对组装工艺进行修改。
如此设计第二侧面接触衬垫以适于组件的外部连接尤其可以是适于引线接合的设计或适于焊球的提供以直接接触印刷电路板或替代载体的设计。用于引线接合的设计要求这些接触衬垫和底层结构的足够强度。用于提供焊球的设计要求可分离一个或多个层中的应力。此外，这些焊球的尺寸和间距应与印刷电路板的尺寸和间距相匹配。
第一晶片的另一种特征在于其固有的柔性。这就意味着这种芯片并不构成刚性体且能够以垂直于其第一侧面和第二侧面的方向弯曲和/或以其它方式变形。在下面也将这种芯片称为“柔性芯片”，这种芯片的使用改进热循环期间的应力松弛。倒装芯片中的应力松弛速率取决于组件的刚度和焊料的变形性能。出于第一芯片与第二芯片之间的焊接节点连接的小间距和小尺寸的原因，在本组件的许多应用中，这种焊料的变形性能会相对受限。不过，第一芯片的小的厚度及其柔性如低弹性模量有助于低组件刚度。
为了提供固有的柔性但仍允许功能性元件在无机材料制成的芯片中的存在，希望将第一芯片置于压缩应变之下。由于在这些功能性元件的两侧提供树脂层，所以可适当地实现这种压缩应变，这种树脂层如聚酰亚胺层、柔性环氧树脂层、聚丙烯酸酯层等。这些接触衬垫最适当地处于这些树脂层的顶部上，以使仅有垂直互连延伸穿过这些树脂层。事先未公开的申请EP 05101593.1(PHNL050169)描述了这种芯片的一种示例，该申请通过参考结合在本发明中。当然，通过在该树脂层中增设添加剂以减小热膨胀系数和/或增设添加剂以提高热导率，可减少第一芯片的这些树脂层以及整个第一芯片本身的热膨胀系数与第二芯片的热膨胀系数之间的合成失配(resultant mismatch)。此外，在第一芯片与第二芯片之间适当地提供未充满材料。不过，正是由于第一层具有固有的柔性，所以可发生第二芯片的变形，且可将应力分布在较大的区域并保持在可接受的限度之内。
现已注意到US6,506664和US6,027,958公开了将芯片变薄的方法，在这些方法中，将芯片嵌入薄膜网中。可将单个的网堆叠，而将电气连接设在这些薄膜网之间。这可用从集成电路的互连结构获知的薄膜技术来进行，如用垂直互连来进行。不过，对于适合于常规组装工艺的组件而言，可堆叠的薄膜网太大，并因此而太昂贵。而且，这种耦接方法并不是一种应用于产业组装工艺中的技术。此外，虽然展示出了内部触点，但在顶部侧面上无用于外部连接的接触衬垫。
在第一实施例中，这些第二侧面接触衬垫具有比第一侧面接触衬垫大的直径。因此，也可有效地减少对应于第一侧面接触衬垫的在第二芯片的接触衬垫。这有利于减小芯片的尺寸或具有足够的输入端/输出端。第二侧面触点也可适当地较大，因为第二侧面触点中的一些延伸到第一芯片中的器件，这样，第二侧面接触衬垫就有效地少于第一侧面接触衬垫。此外，第一芯片的存在允许进行互连的另外重新路由。路由是封装中一种重要问题，以不仅修改这些接触衬垫的尺寸，而且修改这些接触衬垫的位置和相互距离。因此，尽可能均匀地在第二侧面上将这些接触衬垫分割。
在前面所提及的第一引线接合实施例中，第一芯片可具有小于第二芯片的侧向尺寸，或者可具有与第二芯片相等的侧向尺寸。
在第一芯片具有与第二芯片相等的侧向尺寸的情形中，可实现晶片级组件。这可有效地降低组件成本。然后用晶片规模技术在第一芯片和第二芯片之间适当地形成电气连接，这种晶片规模技术如通过电镀或无电镀处理生长的柱形凸块的提供、各向异性导电粘合剂的使用或带有在基质中的导电微粒的其它任何技术的使用。形成一种连接的非常适合的选择是焊帽(solder cap)的使用。这种焊帽具有降低的高度，并因此而具有降低的直径，这种降低的直径大约为1至30微米。利用电镀、无电镀处理(electroless process)或另一种技术提供的金属喷镀可适当地与这种焊帽相对。最适合的是一种可通过在电镀槽中的浸渍提供的焊帽。
在第一芯片具有小于第二芯片的侧向尺寸的情形中，另外的的接触衬垫可处于第二芯片上并邻近于第一芯片下面的第二芯片。这种结构是有利的，原因有几种：首先，可在这些主动元件上面的芯片区域中将第一芯片组装到第二芯片。一般来讲，在此区域内的任何接触衬垫均灵敏，这样就对下面的主动元件带来损害。第一芯片尤其是具有固有的柔性的第一芯片允许将引线接合操作的应力进行分布，这样就避免了对第二芯片的这些主动元件的损害。若第二芯片的互连结构包括所谓的低K材料，则第二芯片的脆性可得到进一步的增强。这些材料通常是聚合物类型的材料并且有孔，且往往具有有限的粘附力并因此而形成弱的部分，这些弱的部分可由于引线接合所导致的应力而分层。在第一芯片的顶部提供第二芯片的另一种优点由高度方面的差异构成。这对于将接合线足够地引导至任何芯片载体有重要意义，以将每条接合线有效地分离：由于这种高度方面的差异的原因，降低了来自内结合衬垫的接合线往往接触来自外结合衬垫的接合线并与来自外结合衬垫的接合线形成短路的风险。另一种优点在于，对于某些连接如电源和接地而言，还可建立与第二芯片的最直接的连接，例如，这种连接通过这些另外的接触衬垫。
出于第一引线接合实施例的原因，这种组件可适当地成为还包括芯片载体的电子器件的一部分。正如熟练的技术人员会理解的那样，用适当的模片附接材料将第二芯片的底侧附接到芯片载体。这种芯片载体会具有足够的用于耦接到外部元器件的端子。例如，这种载体可以是一种叠层、一种带和一种引线框。这种芯片组件与一种引线框的结合使用是有利的；可将被动元器件和其它功能元件置于第一芯片中，这些被动元器件和其它功能元件往往结合在叠层中，从而提高叠层的价格。这就减小了这些被动元器件与第二芯片之间的距离，这种距离的减小适用于许多用途。例如，一种用途是用于RF用途如收发器、功率放大器等的电容器与一种第二芯片的结合使用。另一种用途是提供与数字集成电路结合的电阻器等。
在第二实施例中，第一芯片通常形成用于第二芯片的载体。第一芯片适当地具有等于或大于第二芯片的侧向尺寸。但并不排除第一芯片具有较小侧向尺寸的实施方式。若这些侧向尺寸相等，则显然是芯片规模封装结构。若第一芯片的侧向尺寸较大，则第一芯片可以是第二芯片的芯片载体。这样就可用任何常规方式将第二芯片附接到第一芯片：面朝上(利用以接合线、柔性带形式的电气连接，如带式自动接合(TAB)技术或其它技术)面朝下。在这两种情形中，可将一个以上的芯片组装到第一芯片。在此第二种实施方式中，第一芯片设有固有的柔性显然是一种优点。最适当的是对第一芯片的树脂进行选择，以使第一芯片的热膨胀系数基于第二芯片与印刷电路板的热膨胀系数之间。
第一芯片中的器件的类型可以不同。第二芯片通常会形成集成电路。人们通常可区别出被动器件，如解耦电容器和电阻器；这些被动器件的技术优点在于新式集成电路非常需要这些被动器件。这样就可有效地减少I/O的数量，而仍可将这些器件以成本相对较低的工艺设在低成本基板上。
第二种类由其它的主动器件形成，如存储器件、双极器件。将这些器件分离的优点在于需要用不同的技术来制造这些器件；这样，分离的芯片的组装就比在一个单一工艺中集成容易。
这些器件的第三种类由外围设备形成，如ESD防护设备、功率器件、辨识设备。高级集成电路具有非常高的密度，以有效地实现小型化。不过，为了使这些集成电路充分地发挥作用，需要几种不能够像集成电路的晶体管那样小型化的功能元件。因此，由于器件尺寸方面的差异，将这些外围设备置于分离的芯片中就更有意义。此外，将这些外围设备置于分离的芯片中从本质上来讲就有意义，因为这些外围设备可起到输入设备的作用并需要另外的技术部件，如非常好的接地、散热器等。
还在开始的段落中所提及的方法中实现这种目的。
适当的实施例的特征在于：
第一晶片设有第一侧面接触衬垫和第二侧面接触衬垫，在将半导体基板变薄之后将这些第一侧面接触衬垫暴露并在附接步骤中电气耦接到第二晶片中的结合衬垫，以及
将组件与载体分离以打开第二侧面接触衬垫，以启动外部连接。
在本发明的这种方法的实施例中，将第一晶片用作晶片级功能性插件。第一晶片和第二晶片设在该插件，且在第一晶片和第二晶片的相互之间有电气连接。因此，在这种插件中无需应用在一个表面终结的凹槽和金属喷镀。
此外，这种晶片级插件的使用具有这种插件可与高级类型的第二晶片非常良好地结合的优点。这种高级类型包括具有小于100nm的小沟道长度的晶体管和在这种晶体管上的一个或多个互连层中的对应分辨率。实际上，可从第二晶片至第一晶片将这种互连结构的一部分替代。此外，这种高级类型的半导体器件通常包括电介质材料，这种电介质材料具有低电介常数，尤其是小于2.5的相对电介常数。这种类型的电介质材料可以是所知的“低K”材料或者是一种气隙。不过，这种电介质材料的缺点在于降低的机械稳定性。这种降低的机械稳定性对组装工艺尤其是引线接合带来大的问题。通过将这些晶片堆叠，引线接合不直接应用于该第二晶片，这就极大地减少了组装问题。
在第一晶片和第二晶片的相互附接之后将这些晶片分成单个的芯片组件。这种分割可在载体取下之前或之后进行。此外，可在将载体取下之前将第二晶片附接到通常用在切割工艺中的带。
在适当的实施例中，第一晶片和第二晶片设有沟槽，用填充材料填充这些沟槽，且在变薄步骤之后，这些沟槽从这些晶片的第一侧面向第二侧面延伸，其中，通过将填充材料从这些沟槽取出并接着将组件从载体至少局部取出来将这种组件具体处理(individualize)。该实施例提供了晶片级分离方法。由于这是一种蚀刻工艺，所以与锯切或激光划线技术所需的分离通道相比，可将这些分离通道的宽度降低。也将第二晶片变薄是这种方法的一种要求。
可在第一晶片附接到载体之前或将载体取下之后利用焊接提供第二侧面接触衬垫。尤其是在若第一芯片和第二芯片的组件具有柔性时，由于这种组件的总体厚度的原因并且在无任何刚性半导体基板的情况下，在附接之前应用焊料是适当的。这样，焊帽的使用或者与柱形凸块的结合使用就是有利的。
附图说明
将参考附图对本发明的组件的这些和其它方面进行进一步描述，这些附图仅仅是示意图，且在这些图中，不同图中的相同附图标记表示类似的部分，在这些图中：
图1示出了适于用在本发明的组件中的第一芯片的截面图，以及
图2至图9示出了本发明的几个组件的截面图。
具体实施方式
图1示出了一个实施例中的第一芯片100。器件100包括第一侧面接触衬垫33和第二侧面接触衬垫31以及集成电路20。集成电路20处于第一树脂层52与第二树脂层12之间，第一树脂层52和第二树脂层12将这种电路置于压缩应变之下，以减少裂纹的形成。导电轨道32、34穿过树脂层12、52分别延伸到中间衬块21、22。在此示例中，导电轨道32、34连接到相同的中间衬块21、22，从而产生可从两个侧面1、2应用的封装。不过，这仅是一种示例，将会明白，在实践中，将导电轨道32、34相互位移。导电轨道32、34在接触衬垫31、33直立，这些接触衬垫31、33穿过钝化层35、55部分地暴露(“阻力限定衬垫”(resist defined pad))。通过凸块下金属喷镀36、56增强这些接触衬垫31、33，且这些接触衬垫31、33设有凸块37、57，在此情形中，这些凸块37、57是焊帽。钝化层55也在第一芯片100的侧向侧面3延伸，直到绝缘层11。利用常规的分离技术如锯切或切割将在第一芯片100的第二侧面2的另一个树脂层分离。
在此示例中使用一种半导体基板10，绝缘层11埋入这种半导体基板10中。埋入的层11通常是一种氧化物层，但可包括用于集成电路20的改进化学防护的氮化物层，这种氮化物层设在通常外延生长的半导体材料的表面层的内部和上面。在此情形中，基板10的半导体材料以及这种表面层是硅，但这种表面层还可以是另一种半导体材料，如GaAs或GaN。在这种工艺中，埋入的绝缘层11用作一种蚀刻终止层。或者可将一种p-n结用作一种蚀刻终止层。在另一个未示出的示例中，利用一种常规基板，这种基板上有热氧化物，这种热氧化物通常由硅局部氧化(LOCOS)制成。然后用如薄膜技术在这种氧化物上限定半导体器件。在如CMOS或BICMOS技术中，这些器件可用作这种基板中的阱(well)。然后，在蚀刻处理期间，保持半导体基板的一些部分作为台式结构。或者，第一芯片100可仅包含被动元件，如电容器、电阻器和感应器。由于无硅基板，所以就无基板的相互作用，并可制备高Q值感应器。若希望较高的电容密度，则这些电容器可以以深槽电容器的形式。虽然在本示例中将硅基板尽可能远地移开，但这种要求不必严格。还可使用带有如20微米的基板的芯片，在这种基板中有孔径，以将结合衬垫暴露。
将厚度通常为10至20μm的聚酰亚胺用于树脂层12、52。在如通过旋涂涂覆聚酰亚胺之前，已将该表面清洁，且已提供了底层，以提高附着力。在涂覆聚酰亚胺之后，将聚酰亚胺加热到125℃，然后加热到200℃。然后涂覆光致抗蚀剂，这种光致抗蚀剂暴露给适当的辐射源并曝光。这种曝光包括对聚酰亚胺层进行的构造，以产生将第一中间衬块21和第二中间衬块22暴露的接触窗口。在基板的边缘区域C也将用聚酰亚胺形成的第二树脂层12移去，基板的边缘区域C通常是6″的晶片。将在边缘区域C内的支撑层13移去对结果有着有利的影响。树脂层12、52可含有相同的材料，但也不必是这样。这些树脂层还可包括补强材料，如纤维，尤其是芳族聚酸胺纤维、碳纤维或玻璃纤维。或者，这些树脂层可包括热导纤维，如氮化铝、氧化铝、氮化硼甚至是具有氧化表面的铜微粒。
在此情形中，钝化层35、55是氮化硅并通过PECVD在约250℃的温度以约0.5至1.0微米的厚度淀积。之后形成钝化层35的图案以暴露接触衬垫31。钝化层35部分地在接触衬垫31上延伸并起到“阻力限定的”阻焊层的作用。然后通过下凸块金属喷镀36的淀积补强接触衬垫31。在此示例中，下凸块金属喷镀36包括镍并以2至3微米的厚度无电镀淀积。这种处理的优点在于无需将另外的掩膜用于下凸块金属喷镀36的提供。或者，可将铜用于下凸块金属喷镀36并通过电镀涂覆。在此情形中，可在一个步骤中涂覆下凸块金属喷镀36和电凸块37。出于其厚度的原因，下凸块金属喷镀36在钝化层35的上方延伸。
将凸块37涂覆在下凸块金属喷镀36上。在此示例中，凸块37是一种用Sn、SnBi或PbSn制成的焊帽并通过浸渍到理想组分的电镀槽中涂覆。不过，若将下凸块金属喷镀36浸渍在约250℃的温度下的纯锡电镀槽中，则可形成NiSn金属间化合物。这些金属间化合物以突出穿过这种凸块表面的针的形式形成。但这并不是一种有用结果。通过一种低熔化Sn合金的使用可避免这些金属间化合物的形成。这些合金的示例包括SnPb、SnCu和SnBixInyZnz，其中x、y和z中的至少一个大于零。优选的是采用一种无铅焊料。有利的是，这些合金成分并不干涉Sn与金属喷镀的金属尤其是Au之间的反应。
图2示出了电子器件150的第一实施例。在此实施例中，第一芯片100和第二芯片200的组件与载体300结合成一种封装。用焊球57将第一芯片100和第二芯片200相互电气耦接，这些焊球57位于第一芯片100中的这些第一侧面接触衬垫33与对应的第二芯片200中的接触衬垫211之间。用第二芯片200的底侧通过模片附着层220将第二芯片200附接到载体300。适当地用未充满材料将第一芯片100与第二芯片200之间的空间填充，但在图中未示出。第一芯片100中的这些第二侧面接触衬垫31处于第二侧面。引线接合110形成这些第二侧面接触衬垫31与载体300上的导电引线之间的连接。这种载体通常是一种本领域中熟练的技术人员公知的叠层或引线框。第二芯片200包括邻近于在第一芯片100下面的接触衬垫211的另外的接触衬垫212。在此示例中，将这些接触衬垫适当地设在第二芯片200的外围，以使这些接触衬垫并不在第二芯片200中的任何主动元件的上面，图2中并未示出这些主动元件。这些另外的接触衬垫212适当地具有较大的直径和经过补强的底层结构，以使这些接触衬垫212适用于引线接合。在这些另外的接触衬垫212与载体300上的导电引线之间设有线210。模320设在该载体上，以封装第一芯片100、第二芯片200和接合线110、210。将焊球310设在该载体的底侧上，以置于外部元器件上，尤其是印刷电路板上。
图3示出了电子器件150的第二实施例，该实施例同样也包括第一芯片100、第二芯片200和外部载体300。在此实施例中，第一芯片100和第二芯片200具有相同的侧向延伸。这就在已将带有第一芯片100的晶片和带有第二芯片200的晶片组装在一起之后可进行分离的意义上便于组装。已利用蚀刻技术在这两种晶片制备了分离通道。在将这些分离通道暂时填充之后，可利用任何适当的分离技术将这些组件单个化(singulate)，适当的技术包括蚀刻和锯切。
图4示出了组件140的另一个实施例。在此示例中无另外的载体出现。组件140设计用作芯片级封装。对这些焊球130进行选择以适于直接置于印刷电路板上。图中示出的未充满材料219位于第一芯片100与第二芯片200之间并封装焊球连接。正如将会理解的那样，第一芯片100和第二芯片200配合是特别适当的，因为与焊球57的数量相比，这样可减少焊球130的数量。因此，焊球130之间的间距可非常大，且焊球130的高度也可非常大。通常用在这些芯片级封装中的高度是最佳的。
图5示出了这种组件140的第二实施例。在此实施例中，第一芯片100具有小于第二芯片200的侧向延伸。焊球230设在该第二芯片的另外的接触衬垫212上。为了使这种组件发挥作用，这些焊球230的高度需等于第一芯片100与第二芯片200之间的焊球130、第一芯片100和焊球57的高度。因此，使用小尺寸的焊球57优选焊帽以及非常薄的第一芯片100是适当的。此外，可通过另外的金属喷镀级或较厚的下凸块金属喷镀使接触衬垫212向上。
图6示出了这种组件140的第三实施例，该实施例类似于图5中的实施例。在此实施例中，第一芯片100侧向延伸并超过第二芯片200。因此，第一芯片100就适于作为常规的芯片载体。封装129确保将组件密封以防水汽和防尘。
图7示出了这种组件140的第四实施例，该实施例是第三实施例的延伸。在此情形中，第一芯片100起到用于第二芯片200的另一种芯片250的载体的作用，用焊球257将该另一种芯片250耦接到该第一芯片。在此实施例中，将这些焊球57、257设在第一芯片100上是适当的，但并不是必需的。
图8示出了这种组件140的第五实施例，在此实施例中，用模片附件122将第二芯片200附接到第一芯片100。然后将第一芯片100弯曲，这样就在第二芯片200的相对侧面构成到这些焊球57的互连。用任何封装材料将第一芯片100与第二芯片200之间的任何空间填充。现已观察到这种组件概念150也可有其它变体，尤其是在希望第二芯片200包括与印刷电路板成大于0°的角的用途中。因此，在将第一芯片100弯曲之前将第二芯片200组装到第一芯片100。在另一个步骤中，以所希望的角度将该第一芯片弯曲，以重新定向第二芯片200。最后提供巩固第二芯片200的重新定向的模塑材料。因此，用于外部连接的接触衬垫处于并未弯曲的区域内，但这并不是必需的。
图9公开了这种组件140的第六实施例。在此实施例中，第一芯片与第二芯片200之间的电气连接由引线接合121构成。这种组件140的优点在于这种组件非常类似于常规的球门阵列封装，而仍包括第一芯片100和第二芯片200。
简而言之，一种第一芯片100和第二芯片200的组件，这种组件的第一芯片100具有柔性并在芯片100的相对侧面1，2上设有第一树脂层12和第二树脂层52，这种组件允许将第一芯片保持在压缩状态，第一侧面接触衬垫33和第二侧面接触衬垫31分别处于第一侧面1和第二侧面2上，这些第一侧面接触衬垫33耦接到对应的第二芯片200的接触衬垫211，且这些第二侧面接触衬垫31设计用于这种组件的外部连接。

Claims (14)

1.一种第一芯片和第二芯片的组件，所述第一芯片具有柔性并在所述芯片的相对侧面上设有第一树脂层和第二树脂层，以允许将所述第一芯片保持在压缩状态，第一侧面接触衬垫和第二侧面接触衬垫分别处于所述第一侧面和第二侧面上，所述第一侧面接触衬垫耦接到对应的所述第二芯片的接触衬垫，且所述第二侧面接触衬垫设计用于所述组件的外部连接。
2.如权利要求1所述的组件，其特征在于：所述第一侧面接触衬垫具有大于所述第二侧面接触衬垫的直径。
3.如权利要求1或2所述的组件，其特征在于：所述第一侧面接触衬垫和第二侧面接触衬垫分别处于所述第一树脂层和第二树脂层上，所述接触衬垫电气耦接到所述芯片中的电气元件，且垂直互连穿过所述树脂层。
4.如权利要求1所述的组件，其特征在于：所述第一侧面接触衬垫和所述对应的所述第二芯片的接触衬垫相互朝向彼此。
5.如权利要求1或4中的任一项所述的组件，其特征在于：所述第二芯片侧向延伸超过所述第一芯片。
6.如权利要求5所述的组件，其特征在于：所述第二芯片具有邻近于耦接到所述第一芯片的所述第一侧面接触衬垫的另外的接触衬垫，这些另外的接触衬垫设计用于所述组件的外部连接。
7.如权利要求1或4中的任一项所述的组件，其特征在于：所述第一芯片和所述第二芯片具有相同的侧向尺寸。
8.一种电气器件，所述电气器件包括如权利要求5、6或7所述的组件以及载体，所述第二芯片在底侧上附接到所述载体，所述底侧背向所述第一芯片，所述载体设有终端，在所述第二芯片的另外的接触衬垫存在时，用柔性连接尤其是引线接合将所述第一芯片的第二侧面接触衬垫和所述第二芯片的另外的接触衬垫耦接到这些终端。
9.如权利要求1、2或3所述的组件，其特征在于：所述第一芯片起到用于所述第二芯片的载体的作用。
10.如权利要求1或2所述的组件，其特征在于：相对于所述第一侧面接触衬垫对所述第二侧面接触衬垫重新进行路由。
11.如权利要求1所述的组件，其特征在于：所述第一芯片包括用于防护所述第二芯片不受静电放电影响的防护电路。
12.如权利要求1所述的组件，其特征在于：所述第一芯片包括被动元器件网。
13.一种制造第一芯片和第二芯片的组件的方法，所述方法包括以下步骤：
将第一晶片附接到载体，所述第一晶片具有半导体基板，所述半导体基板带有多个所述第一芯片；
将所述半导体基板变薄：
将第二晶片附接到所述第一晶片的所述变薄的半导体基板，所述第二晶片具有半导体基板，所述半导体基板带有多个所述第二芯片；以及
将接触衬垫打开以启动至所述组件的外部连接，其特征在于：
所述第一晶片设有第一侧面接触衬垫和第二侧面触点，在所述半导体基板变薄之后将所述第一侧面触点暴露并在所述附接步骤中电气耦接到所述第二晶片中的结合衬垫，以及
将所述组件与所述载体分离以打开所述顶侧接触衬垫，以启动外部连接。
14.如权利要求14所述的方法，其特征在于：所述第一晶片和第二晶片设有沟槽，用填充材料填充所述这些沟槽，且在所述变薄步骤之后，所述这些沟槽从所述这些晶片的所述第一侧面向所述第二侧面延伸，其中，通过将所述填充材料从所述这些沟槽取出并接着将所述组件从所述载体至少局部取出以将所述组件具体处理。
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