CN101305415A - Liquid crystal device, and drive method thereof - Google Patents
Liquid crystal device, and drive method thereof Download PDFInfo
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- CN101305415A CN101305415A CNA2006800422280A CN200680042228A CN101305415A CN 101305415 A CN101305415 A CN 101305415A CN A2006800422280 A CNA2006800422280 A CN A2006800422280A CN 200680042228 A CN200680042228 A CN 200680042228A CN 101305415 A CN101305415 A CN 101305415A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0294—Details of sampling or holding circuits arranged for use in a driver for data electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/04—Partial updating of the display screen
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
- G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
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- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The present invention discloses a liquid crystal display device and drive method thereof. A data signal line drive circuit (13) includes a first sampling unit (23), and a second sampling unit (24) operating at a lower speed than that of the former. By the action of a select circuit (22), the first sampling unit (23) operates in an ordinary display mode, and the second sampling unit (24) operates in a partial display mode. In order to warrant the correct sampling operation, a one-line time and a sampling period are made longer for a display period in the partial display mode than that in the ordinary display mode. In the ordinary display mode, both the first sampling unit (23) and the second sampling unit (24) may operate. As a result, the power consumption of a liquid crystal display device is reduced for the partial display.
Description
Technical field
The present invention relates to liquid crystal indicator and driving method thereof, particularly have the liquid crystal indicator and the driving method thereof of partial display function.
Background technology
In liquid crystal indicator, what have has a function that a part to picture shows (showing hereinafter referred to as part).Part shows use information time the such as the accepting state of electric wave and time when being presented at as the mobile phone standby with a part of picture (with reference to Figure 10).When carrying out the part demonstration, the display element in the indication range of setting is write picture signal, but the display element in the non-indication range is not write picture signal.Show by such part, can reduce the driving frequency of display element and the power consumption of reduction liquid crystal indicator.The example that shows about part has disclosed in patent documentation 1 and 2.
Figure 11 is the formation synoptic diagram of the liquid crystal indicator that has partial display function in the past.In Figure 11, pel array 84 comprises (m * n) individual display element P, n bar scan signal line G1～Gn and m bar data signal line S1～Sm.Scan signal line drive circuit 82 optionally activates scan signal line G1～Gn in order based on the control signal (GSP, GEN, GCK1, GCK2) from display control unit 81 outputs.Data signal wire driving circuit 83 is based on control signal (SSP, SCK, SCKB) and picture signal VD from display control unit 81 outputs, driving data signal wire S1～Sm.
Carrying out when part shows, display control unit 81 is enabled signal GEN (corresponding with non-indication range during) during the non-demonstration with grid and is controlled at low level.Scan signal line drive circuit 82 when to enable signal GEN be low level, does not activate any scan signal line at grid.So grid is enabled signal GEN when being low level, picture signal VD does not write any display element P.
Figure 12 is the detailed formation synoptic diagram of data signal wire driving circuit 83.Data signal wire driving circuit 83 is corresponding respectively with data signal line S1～Sm, comprise trigger 91 and sampling portion 92.Trigger 91 is connected in series, and forms shift register.The output signal of shift register becomes sampled signal SMP1～SMPm of data signal line S1～Sm.
Patent documentation 1: Japanese patent laid-open 11-184434 communique
Patent documentation 2: the Jap.P. spy opens the 2002-99262 communique
The announcement of invention
It mainly is to carry out in the electronic equipment strict at power consumption (such as mobile phone) that aforesaid part shows.So the power consumption of liquid crystal indicator needs to reduce as much as possible.But on the other hand, the display element number that comprises of liquid crystal indicator is continuing to increase.If the number of display element increases, then can increase because of the number of (1) sampling portion; (2) sampling portion more reason such as high speed operation the power consumption of liquid crystal indicator is increased.
But when use had the liquid crystal indicator of partial display function, in general, the time of carrying out the part demonstration was more much longer than the time of carrying out the whole image demonstration.So in order to reduce the power consumption of liquid crystal indicator, the power consumption that reduces when partly showing is effectively.In addition, known in the data signal wire driving circuit of liquid crystal indicator, the electric weight that the buffer circuit that is provided with between shift register and the sampling switch (phase inverter 93 among Figure 11) consumes is more.
So, the objective of the invention is to be reduced in the power consumption that carries out the liquid crystal indicator of part when showing.
The feature of the 1st kind of situation of the present invention is, has the liquid crystal indicator of partial display function, comprising:
Be included in the configuration of line direction and column direction several display elements, with delegation configuration with public several scan signal lines that are connected of display element, same row configuration with pel arrays public several data signal lines that are connected of display element;
Optionally activate the scan signal line drive circuit of described scan signal line;
Based on the data signal wire driving circuit of the picture signal that provides, the described data signal line of driving,
Described data signal wire driving circuit comprises:
Shift register with regard to the described data signal line output of each bar sampled signal;
Have the 1st and the 2nd lead-out terminal, will from the sampled signal of described shift register output under display mode usually at least from described the 1st lead-out terminal output, under the part display mode from the selection circuit of described the 2nd lead-out terminal output;
Based on from the sampled signal of described the 1st lead-out terminal output to described picture signal sample, outside add to the 1st sampling portion of described data signal line;
Based on from the sampled signal of described the 2nd lead-out terminal output to described picture signal sample, outside add to the 2nd sampling portion of described data signal line.
The feature of the 2nd kind of situation of the present invention is, in the 1st kind of situation of the present invention,
Described the 2nd sampling portion is with the circuit than tick-over than described the 1st sampling portion.
The feature of the 3rd kind of situation of the present invention is, in the 2nd kind of situation of the present invention,
Described the 1st sampling portion comprises:
Input is from the 1st buffer part of the sampled signal of described the 1st lead-out terminal output;
Based on from the sampled signal of described the 1st buffer part output, to whether adding the 1st sampling switch that described picture signal is switched for described data signal line,
Described the 2nd sampling portion comprises:
Input is from the 2nd buffer part of the sampled signal of described the 2nd lead-out terminal output;
Based on from the sampled signal of described the 2nd buffer part output, to whether adding the 2nd sampling switch that described picture signal is switched for described data signal line,
The driving force of described the 2nd buffer part is lower than described the 1st buffer part,
The conducting resistance of described the 2nd sampling switch is bigger than described the 1st sampling switch.
The feature of the 4th kind of situation of the present invention is, in the 3rd kind of situation of the present invention,
Described the 2nd buffer part is to be made of the transistor narrower than the channel width of described the 1st buffer part,
Described the 2nd sampling switch is to be made of the transistor narrower than the channel width of described the 1st sampling switch.
The feature of the 5th kind of situation of the present invention is, in the 1st kind of situation of the present invention,
Described selection circuit will not exported from described the 2nd lead-out terminal from the sampled signal of described shift register output under common display mode, but from described the 1st lead-out terminal output.
The feature of the 6th kind of situation of the present invention is, in the 1st kind of situation of the present invention,
Described selection circuit will be exported from the described the 1st and the 2nd lead-out terminal from the sampled signal of described shift register output under common display mode.
The feature of the 7th kind of situation of the present invention is, in the 1st kind of situation of the present invention,
Described scan signal line drive circuit switches scan signal line to be activated every the 1st line time under common display mode; During the demonstration of part display mode, switch scan signal line to be activated every the 2nd line time longer than described the 1st line time,
Described shift register is worked with the 1st sampling period under common display mode; During the demonstration under the part display mode, work with the 2nd sampling period longer than described the 1st sampling period.
The feature of the 8th kind of situation of the present invention is, have several display elements of including the configuration of line direction and column direction, with driving methods delegation's configuration and liquid crystal indicators public several scan signal lines that are connected of display element, and pel arrays display element public several data signal lines that are connected configuration at same row, comprising:
Optionally activate the step of described scan signal line;
Based on the step of the picture signal that provides, the described data signal line of driving,
The step of described driving data signal wire comprises:
Generate the step of sampled signal with regard to the described data signal line of each bar;
With the sampled signal that generates under display mode usually at least as the output of the 1st sampled signal, under the part display mode as the step of the 2nd sampled signal output;
Use the 1st sampling portion, described picture signal sampled and in the step of described data signal line based on described the 1st sampled signal;
Use the 2nd sampling portion, described picture signal sampled and in the step of described data signal line based on described the 2nd sampled signal.
According to the of the present invention the 1st or the 8th kind of situation, under display mode usually, use the 1st sampling portion (perhaps the 1st and the 2nd sampling portion) to sample; Under the part display mode, use the 2nd sampling portion different to sample with the 1st sampling portion.Therefore, compare, can cut down the power consumption when carrying out the part demonstration with liquid crystal indicator in the past.
According to the 2nd kind of situation of the present invention, under common display mode, use the 1st sampling portion (perhaps the 1st and the 2nd sampling portion) to sample; Under the part display mode, use ratio the 1st sampling portion more the 2nd sampling portion of tick-over samples.Therefore, compare, can cut down the power consumption when carrying out the part demonstration with liquid crystal indicator in the past.
According to the 3rd kind of situation of the present invention, between the 1st sampling portion and the 2nd sampling portion, have difference, thereby can obtain having the liquid crystal indicator of the 2nd sampling portion of tick-over more than the 1st sampling portion by the characteristic that makes buffer part and sampling switch.
According to the 4th kind of situation of the present invention, between the 1st sampling portion and the 2nd sampling portion, by making the transistorized channel width that constitutes buffer part and sampling switch have difference, thereby can obtain having the liquid crystal indicator of the 2nd sampling portion of tick-over more than the 1st sampling portion.
According to the 5th kind of situation of the present invention, because the 1st sampling portion and the 2nd sampling portion often exclusively work, so easily liquid crystal indicator is designed and estimates.
According to the 6th kind of situation of the present invention since under common display mode 2 sampling portion parallel runnings, so can must be lower the performance design of the 1st sampling portion.
According to the 7th kind of situation of the present invention, during the demonstration of part display mode in, the time of 1 row and sampling period, the pace of change of picture signal was more following slowly than common display mode than long under the common display mode.So, under the part display mode of the 2nd sampling portion work, also can guarantee to sample and correctly carry out.
The simple declaration of accompanying drawing
Fig. 1 is the formation schematic block diagram of the liquid crystal indicator under one embodiment of the present invention.
Fig. 2 is the detailed formation synoptic diagram of the data signal wire driving circuit that comprises in as shown in Figure 1 the liquid crystal indicator.
Fig. 3 A is the circuit diagram of the 1st configuration example of the selection circuit that comprises in as shown in Figure 2 the data signal wire driving circuit.
Fig. 3 B is the synoptic diagram of the truth table of selection circuit as shown in Figure 3A.
Fig. 4 A is the circuit diagram of the 2nd configuration example of the selection circuit that comprises in as shown in Figure 2 the data signal wire driving circuit.
Fig. 4 B is the synoptic diagram of the truth table of the selection circuit shown in Fig. 4 A.
Fig. 5 A is the circuit diagram of the 3rd configuration example of the selection circuit that comprises in as shown in Figure 2 the data signal wire driving circuit.
Fig. 5 B is the synoptic diagram of the truth table of the selection circuit shown in Fig. 5 A.
Fig. 6 is the timing chart that comprises the data signal wire driving circuit of the selection circuit shown in Fig. 3 A or Fig. 4 A.
Fig. 7 is the timing chart that comprises the data signal wire driving circuit of the selection circuit shown in Fig. 5 A.
Fig. 8 is the schematic table of the 1st and the 2nd sampling portion working condition that comprises in as shown in Figure 2 the data signal wire driving circuit.
Fig. 9 is the timing chart of the output signal of the display control unit that comprises in as shown in Figure 1 the liquid crystal indicator.
The example synoptic diagram of the display frame when Figure 10 is the part demonstration.
Figure 11 is the formation schematic block diagram of liquid crystal indicator in the past.
Figure 12 is the detailed formation synoptic diagram of the data signal wire driving circuit that comprises in the past the liquid crystal indicator.
Label declaration
10 liquid crystal indicators
11 display control units
12 scan signal line drive circuits
13 data signal wire driving circuits
14 pel arrays
21 triggers
22 select circuit
23 the 1st sampling portions
24 the 2nd sampling portions
31,41 phase inverters
32,42 sampling switchs
The best mode that carries out an invention
Fig. 1 is the formation schematic block diagram of the liquid crystal indicator under one embodiment of the present invention.Liquid crystal indicator 10 shown in Figure 1 comprises: display control unit 11, scan signal line drive circuit 12, data signal wire driving circuit 13 and pel array 14.Expression is that the common display mode or the mode select signal MSEL of part display mode offer liquid crystal indicator 10.Liquid crystal indicator 10 is showing whole image, the part of display frame under the part display mode under the display mode usually.
11 pairs of scan signal line drive circuits 12 of display control unit and data signal wire driving circuit 13 output control signals are simultaneously to data signal wire driving circuit 13 output image signal VD.More particularly, 11 pairs of scan signal line drive circuits of display control unit, 12 output grid initial pulse GSP, gate clock GCK1, GCK2 and grid are enabled signal GEN, simultaneously to data signal wire driving circuit 13 output source electrode initial pulse SSP, source electrode clock SCK, SCKB (inversion signal of SCK), part display control signal PATCTL and picture signal VD.
Grid initial pulse GSP is the signal of beginning of expression 1 frame, is set at the level (hereinafter referred to as high level) of regulation in official hour with the ratio of 1 frame time 1 time.Gate clock GCK1, GCK2 are the signals of beginning of expression 1 row, and the ratio with 2 line times 1 time changes to the direction (hereinafter referred to as ascent direction) of regulation respectively.It is per 1 signal that whether shows of row of expression that grid is enabled signal GEN, is set at setting (hereinafter referred to as high level) (corresponding with indication range during) during the demonstration of display mode and part display mode usually.
The cycle that picture signal VD is changed calls " cycle (cycle) " below.Source electrode initial pulse SSP is the signal of the beginning of expression 1 row, is set at specified level (hereinafter referred to as high level) in 1 cycle (cycle) of per 1 line time.Source electrode clock SCK is the clock signal that has 2 cycles (cycle).Part display control signal PATCTL and mode select signal MSEL are same signals.The rising of picture signal VD and source electrode clock SCK and the variation synchronously that descends.
Scan signal line drive circuit 12 optionally activates scan signal line G1～Gn in order based on the control signal from display control unit 11 outputs.More particularly, scan signal line drive circuit 12 by the current potential of adding regulation for scan signal line G1, activates scan signal line G1 in 1 line time after the grid initial pulse GSP output just.Thereafter, scan signal line drive circuit 12 is whenever gate clock GCK1 or GCK2 rise, just according to G2, G3 ..., the order switching scan signal line to be activated of Gn.But, to enable signal GEN at grid and be positioned at low level the time, scan signal line drive circuit 12 does not activate any scan signal line.
Data signal wire driving circuit 13 is based on control signal and picture signal VD from display control unit 11 outputs, driving data signal wire S1～Sm.Shown in the circuit of data signal wire driving circuit 13 is constructed as follows.
Fig. 2 is the detailed formation synoptic diagram of data signal wire driving circuit 13.Data signal wire driving circuit 13 is corresponding respectively with data signal line S1～Sm, comprises trigger 21, selects circuit the 22, the 1st sampling portion 23 and the 2nd sampling portion 24.In addition, in order to simplify drawing, only described the circuit corresponding among Fig. 2 with data signal line S1～S4.
Data signal wire driving circuit 13 comprises m trigger 21 altogether.M trigger 21 is connected in series like that according to the input that the output of prime becomes the back level, forms the shift register of m level.Source electrode clock SCK, SCKB import as clock, and source electrode initial pulse signal SSP imports as serial data, offers shift register.Trigger 21 when source electrode clock SCK or SCKB change, the output signal (perhaps source electrode initial pulse SSP) of utmost point trigger 21 before the storage.
Below, the output signal of i (i is the integer below the 1 above m) trigger 21 is called sampled signal Qi.Sampled signal Q1 is set at the initial high level that continues 2 cycles (cycle) in 1 line time.Sampled signal Q2 is set at the high level that continues 2 cycles (cycle) than the late one-period of the rising of sampled signal Q1 (cycle).Similarly, sampled signal Qi is set at the high level that continues 2 cycles (cycle) than the late one-period of the rising of sampled signal Qi-1 (cycle).(with reference to Fig. 6 described later and Fig. 7)
Constitute mutually the same with selection circuit the 22, the 1st sampling portion 23 of the corresponding setting of data signal line S1～Sm and the circuit of the 2nd sampling portion 24.Below, to describing with selection circuit the 22, the 1st sampling portion 23 and the 2nd sampling portion 24 of the corresponding setting of data signal line Si.
With sampled signal Qi and part display control signal PATCTL input selection circuit 22.Part display control signal PATCTL is a low level under common display mode, is high level under the part display mode.Select circuit 22 that the 1st lead-out terminal that is connected with the 1st sampling portion 23 and the 2nd lead-out terminal that is connected with the 2nd sampling portion 24 are arranged.Select circuit 22 exporting sampled signal Qi from the 1st lead-out terminal under the display mode usually, under the part display mode, export sampled signal Qi from the 2nd lead-out terminal.Perhaps, select circuit 22 also can export sampled signal Qi jointly under the display mode usually from the 1st and the 2nd lead-out terminal.
Fig. 3 A, Fig. 4 A and Fig. 5 A are respectively the circuit diagrams of selecting the 1st～the 3rd configuration example of circuit 22.Fig. 3 B, Fig. 4 B and Fig. 5 B are respectively the synoptic diagram of the truth table of the selection circuit shown in Fig. 3 A, Fig. 4 A and Fig. 5 A.Below, will be called the 1st sampled signal SMP_Li from the sampled signal that the 1st lead-out terminal of selecting circuit 22 is exported, will be called the 2nd sampled signal SMP_Si from the sampled signal that the 2nd lead-out terminal of selecting circuit 22 is exported.
Fig. 6 is the timing chart that comprises the data signal wire driving circuit 13 of selecting circuit 22a or 22b.As shown in Figure 6, under common display mode (when part display control signal PATCTL is low level),, export the 1st sampled signal SMP_Li based on sampled signal Qi.Under the part display mode (part display control signal PATCTL be high level in),, export the 2nd sampled signal SMP_Si based on sampled signal Qi.
Fig. 7 is the timing chart that comprises the data signal wire driving circuit 13 of selecting circuit 22c.As shown in Figure 7, under common display mode,, export the 1st sampled signal SMP_Li and the 2nd sampled signal SMP_Si based on sampled signal Qi.Under the part display mode,, export the 2nd sampled signal SMP_Si based on sampled signal Qi.
The 1st sampling portion 23 samples to picture signal VD based on the 1st sampled signal SMP_Li, adds to data signal line Si outward.The 2nd sampling portion 24 samples to picture signal VD based on the 2nd sampled signal SMP_Si, adds to data signal line Si outward.
As mentioned above, select circuit 22 corresponding, the output destination of switch sampling signal Qi with part display control signal PATCTL.So corresponding with the kind and the part display control signal PATCTL that select circuit 22, the 1st sampling portion 23 and the 2nd sampling portion 24 work sometimes, do not work sometimes.
Fig. 8 is the schematic table of the working condition of the 1st sampling portion 23 and the 2nd sampling portion 24.As shown in Figure 8, use to select circuit 22a or 22b when selecting circuit 22, the 1st sampling portion 23 work when part display control signal PATCTL is low level, the 2nd sampling portion 24 work when part display control signal PATCTL is high level.In addition, use to select circuit 22c when selecting circuit 22, the 1st sampling portion 23 and 24 work of the 2nd sampling portion when part display control signal PATCTL is low level, the 2nd sampling portion 24 work when part display control signal PATCTL is high level.
Below referring again to Fig. 2, the 1st sampling portion 23 and the 2nd sampling portion 24 are elaborated.As shown in Figure 2, the 1st sampling portion 23 comprises several phase inverters 31 and sampling switch 32.Sampling switch 32 is the analog switches that are made of P type MOS transistor and N type MOS transistor.A Lead-through terminal to sampling switch 32 provides picture signal VD, and another Lead-through terminal connects data signal line Si.
Phase inverter 31 is divided into two groups, and the phase inverter 31 that belongs to every group is connected in series.The phase inverter 31 that is connected in series plays the function as buffer part.More particularly, phase inverter 31 connects from being too narrow to the wide order order of the little beginning of driving force (promptly from) according to the channel width of built-in MOS transistor.To initial phase inverter 31 inputs the 1st sampled signal SMP_Li.Provide the 1st sampled signal SMP_Li to the control terminal of sampling switch 32 by last phase inverter 31.In addition, in the 1st sampling portion 23, also can use other circuit of having pooling feature (such as, with the impact damper of input signal homophase output) as the substitute of phase inverter 31.
When the 1st sampled signal SMP_Li was high level, sampling switch 32 was a conducting state, and picture signal VD is added on the data signal line Si.In contrast, when the 1st sampled signal SMP_Li was low level, sampling switch 32 was an off state, and picture signal VD is not added on the data signal line Si.Whether sampling switch 32 is based on the sampled signal that offers control terminal (by the 1st sampled signal SMP_Li of several impact dampers 31) like this, switch adding picture signal VD for data signal line Si.
The 2nd sampling portion 24 is the same with the 1st sampling portion 23, comprises several phase inverters 41 and sampling switch 42.The type of attachment of phase inverter 41 and sampling switch 42 is identical with the situation of the 1st sampling portion 23.The phase inverter 41 that is connected in series plays the function as buffer part.Whether sampling switch 42 is based on the 2nd sampled signal SMP_Si by several phase inverters 41, switch adding picture signal VD for data signal line Si.
The 2nd sampling portion 24 is different with the 1st sampling portion 23 in the following areas: sampling switch 42 is to be made of the MOS transistor narrower than the channel width of sampling switch 32.So the conducting resistance of sampling switch 42 is bigger than sampling switch 32.In addition, phase inverter 41 is to be made of the MOS transistor narrower than the channel width of phase inverter 31.So the driving force of phase inverter 41 is lower than phase inverter 31, the driving force of the buffer circuit that phase inverter 41 constitutes is lower than the buffer circuit that phase inverter 31 constitutes.Because the formation of circuit has above difference, therefore 24 to the 1 sampling portions 23 of the 2nd sampling portion are with more tick-over.
As mentioned above, under the part display mode, the 1st sampling portion 23 does not work, and has only 24 work (with reference to Fig. 8) of the 2nd sampling portion.In order also to guarantee correct sampling work, liquid crystal indicator 10 has adopted method as follows under such part display mode, promptly during the demonstration of part display mode in 1 line time and sampling period long during than common display mode; It is short when 1 line time is than common display mode in during the non-demonstration of part display mode.
Fig. 9 is the timing chart of the output signal of display control unit 11.Under common display mode (when part display control signal PATCTL is low level), gate clock GCK1 or GCK2 rise every 1 line time (hereinafter referred to as T1).So scan signal line drive circuit 12 switches scan signal line to be activated according to per 1 line time T1.
Different therewith is, in (part display control signal PATCTL be high level and grid enable signal GEN and be high level time), gate clock GCK1 or GCK2 are every time (hereinafter referred to as the T2) rising that will grow than 1 line time T1 (display mode 1 line time down usually) during the demonstration in the part display mode.So scan signal line drive circuit 12 switches scan signal line to be activated according to the time T 2 longer than 1 line time T1.
In addition, in (part display control signal PATCTL be high level and grid to enable signal GEN be low level time), gate clock GCK1 or GCK2 rose every the time (hereinafter referred to as T3) shorter than 1 line time T1 during the non-demonstration under the part display mode.But, be low level because grid is enabled signal GEN, so scan signal line drive circuit 12 does not activate any scan signal line.
Like this, 1 line time in the liquid crystal indicator 10 is T1 under common display mode, is T2 (T2＞T1), be T3 (T3＜T1) (is T0 to call in the following text between this moment) during the non-demonstration of part display mode during the demonstration of part display mode.1 line time T0 is as source electrode initial pulse SSP, the time reference that source electrode clock SCK, SCKB and picture signal VD change.The length in 1 cycle (cycle) that the cycle that picture signal VD changes is suitable with the semiperiod of source electrode clock SCK is determined by 1 line time T0.
Therefore, during the demonstration under the part display mode in, the length in 1 cycle (cycle) is than long under the common display mode.So speed low (T1/T2 speed doubly) that the shift register that trigger 21 constitutes is worked during the common display mode of internal ratio during the demonstration of part display mode.In other words, this trigger with the work of the 1st sampling period, is worked with the 2nd sampling period longer than the 1st sampling period under the part display mode under common display mode.In addition, in during the demonstration of picture signal VD under the part display mode with than common display mode the time low speed (T1/T2 speed doubly) change.
In addition, as mentioned above, even the length variations of 1 line time the time, the length of 1 frame time but is to keep certain.So as in the indication range that comprises the capable display element of a, following formula (1) is set up.
T1×n＝T2×a+T3×(n-a)...(1)
In addition, during the non-demonstration of part display mode, be low level because grid is enabled signal GEN, so picture signal VD can not write in any display element P.So during the non-demonstration of part display mode,, can not show to exert an influence to picture even if 1 line time T3 is shorter than 1 line time T1 under the common display mode yet.
The following describes the effect of the liquid crystal indicator 10 under the relevant present embodiment.In liquid crystal indicator (with reference to Figure 11 and Figure 12) in the past, data signal wire driving circuit 83 is identical with the work under the part display mode under common display mode.So the power consumption of data signal wire driving circuit 83 under common display mode with the part display mode under all the same.
Different therewith is, in liquid crystal indicator 10 (with reference to Fig. 1 and Fig. 2), and the 1st sampling portion 23 (perhaps the 1st sampling portion 23 and the 2nd sampling portion 24) work under the display mode usually, and the 2nd sampling portion 24 work under the part display mode.In the 1st sampling portion 23, sampling switch 32 consumes electric power hardly, has only phase inverter 31 along with the variation of sampled signal Qi consumes electric power.In addition, in the 2nd sampling portion 24, sampling switch 42 consumes electric power hardly, has only phase inverter 41 along with the variation of sampled signal Qi consumes electric power.
But because phase inverter 41 is by constituting than the narrow MOS transistor of phase inverter 31 channel widths, so the power consumption of phase inverter 41 is littler than phase inverter 31.So the power consumption of the 2nd sampling portion 24 is littler than the 1st sampling portion 23.
In such liquid crystal indicator 10, what the part display mode was worked down is the 2nd sampling portion 24 littler than the power consumption of the 1st sampling portion 23.So liquid crystal indicator 10 is compared with liquid crystal indicator in the past, can reduce the power consumption when carrying out the part demonstration.
In addition, liquid crystal indicator 10 during the demonstration of part display mode in, 1 line time and sampling period are long during than common display mode, picture signal VD is low velocity variations with than common display mode the time also.So, even under the part display mode that has only 24 work of the 2nd sampling portion, also can guarantee correctly carrying out of sampling work.
Particularly; if use at display mode down-sampled signal Qi usually not to 24 outputs of the 2nd sampling portion but to the selection circuit 22 of the 1st sampling portion 23 outputs; as select circuit 22a, the 22b; then, therefore be easy to liquid crystal indicator 10 is designed and evaluation etc. because the 1st sampling portion 23 and the 2nd sampling portion 24 exclusively work through regular meeting.
In addition, if use at display mode down-sampled signal Qi usually during to the selection circuit 22 of the 1st sampling portion 23 and the 24 common outputs of the 2nd sampling portion, as select the circuit 22c, then because common following 2 sampling portion parallel runnings of display mode, therefore can must be lower with the performance design of the 1st sampling portion 23.
In addition, by display control unit 11 is suitably designed, can also constitute liquid crystal indicator as described below.First kind, liquid crystal indicator also can be littler than the frame rate under the common display mode (frame number that the unit interval shows) under the part display mode.Second kind, liquid crystal indicator also can be under the part display mode, according to the rules time interval writes picture signal in display element in indication range, writes picture signal according to the time interval that will grow by comparison in display element in non-indication range.The third, liquid crystal indicator also can be based on the display frame of multivalue image signal under common display mode, under the part display mode based on the display frame of bianry image signal.At this moment, liquid crystal indicator also can use operational amplifier when generating many-valued picture signal, use the switch that connects 2 kinds of supply voltages when generating the bianry image signal.By these liquid crystal indicators, can more be reduced in the power consumption when carrying out the part demonstration.
As mentioned above, the liquid crystal indicator in the present embodiment uses the 1st sampling portion (perhaps the 1st and the 2nd sampling portion) to sample under common display mode, uses the 2nd sampling portion different with the 1st sampling portion to sample under the part display mode.So, compare with liquid crystal indicator in the past by the liquid crystal indicator that present embodiment obtains, can reduce the power consumption when partly showing.
Industrial practicality
Liquid crystal indicator of the present invention is owing to have the effect that can reduce power consumption when carrying out partial display Really, therefore can be in the demonstration of the various devices such as mobile phone, the information processing terminal, personal electric computer Use in the device.
Claims (8)
1. liquid crystal indicator, it is,
Have the liquid crystal indicator of partial display function, comprising:
Be included in the configuration of line direction and column direction several display elements, with delegation configuration with public several scan signal lines that are connected of display element, same row configuration with pel arrays public several data signal lines that are connected of display element;
Optionally activate the scan signal line drive circuit of described scan signal line;
Based on the data signal wire driving circuit of the picture signal that provides, the described data signal line of driving,
It is characterized in that,
Described data signal wire driving circuit comprises:
Shift register with regard to the described data signal line output of each bar sampled signal;
Have the 1st and the 2nd lead-out terminal, will from the sampled signal of described shift register output under display mode usually at least from described the 1st lead-out terminal output, under the part display mode from the selection circuit of described the 2nd lead-out terminal output;
Based on from the sampled signal of described the 1st lead-out terminal output to described picture signal sample, outside add to the 1st sampling portion of described data signal line;
Based on from the sampled signal of described the 2nd lead-out terminal output to described picture signal sample, outside add to the 2nd sampling portion of described data signal line.
2. liquid crystal indicator as claimed in claim 1 is characterized in that,
Described the 2nd sampling portion is by constituting with the circuit than tick-over than described the 1st sampling portion.
3. liquid crystal indicator as claimed in claim 2 is characterized in that,
Described the 1st sampling portion comprises:
Input is from the 1st buffer part of the sampled signal of described the 1st lead-out terminal output;
Based on from the sampled signal of described the 1st buffer part output, to whether adding the 1st sampling switch that described picture signal is switched for described data signal line,
Described the 2nd sampling portion comprises:
Input is from the 2nd buffer part of the sampled signal of described the 2nd lead-out terminal output;
Based on from the sampled signal of described the 2nd buffer part output, to whether adding the 2nd sampling switch that described picture signal is switched for described data signal line,
The driving force of described the 2nd buffer part is lower than described the 1st buffer part,
The conducting resistance of described the 2nd sampling switch is bigger than described the 1st sampling switch.
4. liquid crystal indicator as claimed in claim 3 is characterized in that,
Described the 2nd buffer part is to be made of the transistor narrower than the channel width of described the 1st buffer part,
Described the 2nd sampling switch is to be made of the transistor narrower than the channel width of described the 1st sampling switch.
5. liquid crystal indicator as claimed in claim 1 is characterized in that,
Described selection circuit will not exported from described the 2nd lead-out terminal from the sampled signal of described shift register output under common display mode, but from described the 1st lead-out terminal output.
6. liquid crystal indicator as claimed in claim 1 is characterized in that,
Described selection circuit will be exported from the described the 1st and the 2nd lead-out terminal from the sampled signal of described shift register output under common display mode.
7. liquid crystal indicator as claimed in claim 1 is characterized in that,
Described scan signal line drive circuit switches scan signal line to be activated every the 1st line time under common display mode; During the demonstration of part display mode, switch scan signal line to be activated every the 2nd line time longer than described the 1st line time;
Described shift register with the work of the 1st sampling period, is worked with the 2nd sampling period longer than described the 1st sampling period during the demonstration under the part display mode under common display mode.
8. the driving method of a liquid crystal indicator is characterized in that,
Be have several display elements of including the configuration of line direction and column direction, with driving methods delegation's configuration and liquid crystal indicators public several scan signal lines that are connected of display element, and pel arrays display element public several data signal lines that are connected configuration at same row, comprising:
Optionally activate the step of described scan signal line;
Based on the step of the picture signal that provides, the described data signal line of driving,
The step of described driving data signal wire comprises:
Generate the step of sampled signal with regard to the described data signal line of each bar;
With the sampled signal that generates under display mode usually at least as the output of the 1st sampled signal, under the part display mode as the step of the 2nd sampled signal output;
Use the 1st sampling portion, described picture signal sampled and in the step of described data signal line based on described the 1st sampled signal;
Use the 2nd sampling portion, described picture signal sampled and in the step of described data signal line based on described the 2nd sampled signal.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005331483 | 2005-11-16 | ||
| JP331483/2005 | 2005-11-16 | ||
| PCT/JP2006/318957 WO2007058018A1 (en) | 2005-11-16 | 2006-09-25 | Liquid crystal device, and drive method therefor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101305415A true CN101305415A (en) | 2008-11-12 |
| CN101305415B CN101305415B (en) | 2011-06-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2006800422280A Expired - Fee Related CN101305415B (en) | 2005-11-16 | 2006-09-25 | Liquid crystal device, and drive method thereof |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US20090109203A1 (en) |
| JP (1) | JP4762251B2 (en) |
| CN (1) | CN101305415B (en) |
| WO (1) | WO2007058018A1 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4999390B2 (en) * | 2005-07-29 | 2012-08-15 | 株式会社半導体エネルギー研究所 | Display device |
| WO2007013646A1 (en) | 2005-07-29 | 2007-02-01 | Semiconductor Energy Laboratory Co., Ltd. | Display device and driving method thereof |
| EP3352447A1 (en) * | 2012-06-11 | 2018-07-25 | Sony Corporation | Control device, control method, and recording medium for an imaging device |
| US8836679B2 (en) * | 2012-08-06 | 2014-09-16 | Au Optronics Corporation | Display with multiplexer feed-through compensation and methods of driving same |
| KR20150024073A (en) * | 2013-08-26 | 2015-03-06 | 삼성전자주식회사 | Apparatus and method for driving display and for providing partial display |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0575957A (en) * | 1991-09-11 | 1993-03-26 | Hitachi Ltd | Sampling and holding circuit, horizontal scanning circuit using this circuit, and matrix display device including this scanning circuit |
| JPH08331486A (en) * | 1995-06-02 | 1996-12-13 | Matsushita Electric Ind Co Ltd | Image display device |
| JPH09101764A (en) * | 1995-10-06 | 1997-04-15 | Matsushita Electron Corp | Driving method for matrix type video display device |
| JP3525763B2 (en) * | 1998-09-28 | 2004-05-10 | セイコーエプソン株式会社 | Electro-optical device driving circuit, electro-optical device driving method, electro-optical device, and electronic apparatus |
| JP2000206491A (en) * | 1999-01-11 | 2000-07-28 | Sony Corp | Liquid crystal display |
| JP2001109436A (en) * | 1999-10-08 | 2001-04-20 | Oki Electric Ind Co Ltd | Matrix type display device |
| JP3822060B2 (en) * | 2000-03-30 | 2006-09-13 | シャープ株式会社 | Display device drive circuit, display device drive method, and image display device |
| TWI282956B (en) * | 2000-05-09 | 2007-06-21 | Sharp Kk | Data signal line drive circuit, and image display device incorporating the same |
| JP2002196701A (en) * | 2000-12-22 | 2002-07-12 | Semiconductor Energy Lab Co Ltd | Circuit and method for driving display device |
| JP2002287710A (en) * | 2001-03-28 | 2002-10-04 | Sony Corp | Liquid crystal display device, camera system, and portable terminal device |
| JP3791452B2 (en) * | 2002-05-02 | 2006-06-28 | ソニー株式会社 | Display device, driving method thereof, and portable terminal device |
| JP2004029300A (en) * | 2002-06-25 | 2004-01-29 | Toshiba Corp | Display device |
| JP3783686B2 (en) * | 2003-01-31 | 2006-06-07 | セイコーエプソン株式会社 | Display driver, display device, and display driving method |
| JP4333189B2 (en) * | 2003-04-08 | 2009-09-16 | セイコーエプソン株式会社 | Electro-optical device, driving method thereof, and electronic apparatus |
| JP4105132B2 (en) * | 2003-08-22 | 2008-06-25 | シャープ株式会社 | Display device drive circuit, display device, and display device drive method |
| JP4494050B2 (en) * | 2004-03-17 | 2010-06-30 | シャープ株式会社 | Display device drive device and display device |
| JP4510530B2 (en) * | 2004-06-16 | 2010-07-28 | 株式会社 日立ディスプレイズ | Liquid crystal display device and driving method thereof |
| CN100474390C (en) * | 2004-12-09 | 2009-04-01 | 友达光电股份有限公司 | Control device and method and display using the control device |
-
2006
- 2006-09-25 JP JP2007545170A patent/JP4762251B2/en not_active Expired - Fee Related
- 2006-09-25 WO PCT/JP2006/318957 patent/WO2007058018A1/en active Application Filing
- 2006-09-25 CN CN2006800422280A patent/CN101305415B/en not_active Expired - Fee Related
- 2006-09-25 US US12/084,763 patent/US20090109203A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| WO2007058018A1 (en) | 2007-05-24 |
| CN101305415B (en) | 2011-06-22 |
| JP4762251B2 (en) | 2011-08-31 |
| JPWO2007058018A1 (en) | 2009-04-30 |
| US20090109203A1 (en) | 2009-04-30 |
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