JP2000206491A - Liquid crystal display - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device which narrows frame and reduces power consumption of a liquid crystal panel. SOLUTION: In an active matrix type liquid crystal display device of a point sequential pre-charge system, one transfer stage from among the transfer stages arranged in the horizontal direction, a transfer input pulse of, e.g. a shift register 41n is delayed by one period of a horizontal clock Hck with serially connected shift registers 41n, 44n, and is used as a timing pulse (b) for controlling a real data writing analog switch 46n of an n-th column, and is used as a timing pulse (a) for directly controlling a pre-charging analog switch 46n of the n-th column, and a point sequential pre-charge function is given to a horizontal point sequential drive circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a method of precharging by applying a pulse voltage of a predetermined amplitude to a data line in a dot-sequential manner before supplying a signal to the data line. The present invention relates to a dot-sequential precharge type active matrix liquid crystal display device.

[0002]

2. Description of the Related Art With the miniaturization of video cameras and digital cameras, liquid crystal display devices mounted on these cameras as monitors have been required to have smaller external dimensions. Among liquid crystal display devices, a so-called drive circuit integrated type liquid crystal display device in which peripheral drive circuits such as a horizontal drive system and a vertical drive system are formed on the same substrate as a pixel portion is an amorphous liquid crystal mounted with COG (chip on glass). Unlike a display device, a thin film transistor is formed using crystallized silicon on a glass substrate, so that a peripheral region of a pixel portion (hereinafter, referred to as a frame) is used.
Since the driving circuit is disposed in the frame, the size of the frame and the outer size of the liquid crystal panel are affected.

By the way, in a drive circuit integrated type liquid crystal display device, when a method of precharging a data line in a dot-sequential manner before supplying a signal to the data line is adopted, conventionally, as shown in FIG. A precharge circuit 101 for precharging data lines in a point-sequential manner is referred to as a horizontal point-sequential driving circuit 102 for writing actual data in a point-sequential manner.
3 was arranged on the opposite side. In addition,
The precharge circuit 101 is generally configured by a shift register, like the horizontal point sequential drive circuit 102.

[0004]

However, in the above-described prior art, the precharge circuit 101 and the horizontal dot sequential drive circuit 102 having basically the same circuit configuration are connected to the pixel section 1.
Since it is arranged on the opposite side across 03,
Since it is necessary to secure areas for arranging circuits of the same size on both the upper and lower sides of the pixel portion 103, it hinders reduction in frame size, increases power consumption and increases the load on the clock supply line. Demerits in the power side were also great with the increase in capacity.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a liquid crystal display device capable of narrowing a frame of a liquid crystal panel and reducing power consumption.

[0006]

A liquid crystal display device according to the present invention is arranged corresponding to a data line of a pixel portion, and a first group of switches for selectively supplying a signal to the data line; A second switch group for selectively applying a predetermined voltage to the lines prior to signal supply; and a number of transfer stages corresponding to the number of data lines, and a second switch group based on transfer pulses output from each transfer stage. And a drive circuit for sequentially operating each switch of the second switch group and sequentially operating each switch of the first switch group based on a transfer pulse output from the same transfer stage.

In the active matrix type liquid crystal display device of the dot sequential precharge system having the above-mentioned structure, each switch of the first switch group functions as a switch for writing actual data to each pixel, and each switch of the second switch group. The switch functions as a switch for precharging the data line in advance. The transfer pulse output from one of the plurality of transfer stages of the drive circuit is used as a timing pulse for writing actual data and also as a timing pulse for precharging. Thus, the drive circuit for writing the actual data in a dot-sequential manner also has a dot-sequential precharge function.

[0008]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing a basic configuration of a dot-sequential precharge type active matrix liquid crystal display device according to an embodiment of the present invention.

In FIG. 1, a liquid crystal display device 10 according to the present embodiment has a pixel portion 11 in which liquid crystal cells are arranged in a two-dimensional matrix as described later, and a pixel portion having a dot sequential precharge function. For example, it is arranged above 11 and
A horizontal point sequential drive circuit 12 for writing and precharging actual data to each pixel in a dot sequence, and a vertical drive circuit 13 arranged on, for example, the left side of the pixel unit 11 and sequentially driving each pixel in a row unit. Configuration.

FIG. 2 shows an example of the configuration of the pixel section 11.
In FIG. 1, each pixel 20 arranged in a two-dimensional matrix has a thin film transistor 21 as a switching element.
A liquid crystal cell 22 having a pixel electrode connected to a drain electrode of the thin film transistor 21;
Storage capacitor 23 in which one electrode is connected to the drain electrode of
It is composed of

In this pixel structure, the thin film transistor 21 of each pixel 20 has a gate electrode having a gate line.
4m-1, 24m, 24m + 1,..., And their source electrodes are connected to data lines (signal lines), 25n-1, 25
, 25n + 1,... The opposite electrode of the liquid crystal cell 22 is connected to a common line 26 to which a common voltage VCOM is applied.

[First Specific Example] FIG. 3 is a block diagram showing a first specific example of the horizontal dot sequential drive circuit 12 with a dot sequential precharge function.

In FIG. 3, the number of shift registers (S / R)..., 31 corresponding to the number of pixels in the pixel portion 11 in the horizontal direction is shown.
n-1, 31n, 31n + 1,... are provided. Shift registers ..., 31n-1, 31n, 31n + 1, ...
Have, for example, a clocked inverter configuration, and have two horizontal clocks Hck1 and Hc having phases opposite to each other.
The shift operation is performed in synchronization with k2. The shift registers... 31n-1, 31n, 31n + 1,... Are connected so as to be able to scan in both the right and left directions in FIG. .

That is, the output terminal of the shift register 31n-1 is connected to the input terminal of the shift register 31n via the scan direction control switch 32n-1.
Is connected to the input terminal of the shift register 31n + 1 via the scan direction control switch 32n, and the shift register 3
1n + 1 is the scan direction control switch 32n +
1, to the output terminal of the shift register 31n + 2,.
And so on. As a result, the horizontal start pulse is shifted from the shift register... → 31n−1 → 31n → 3
Since the shift is performed in the order of 1n + 1 → 31n + 2 →..., Scanning in the right direction in the figure can be realized.

The output terminal of the shift register 31n + 2 is connected to the input terminal of the shift register 31n + 1 via the scan direction control switch 33n + 1, and is connected to the shift register 31n.
Is connected to the input terminal of the shift register 31n via the scan direction control switch 33n,
Are connected to the input terminal of the shift register 31n-1 via the scan direction control switch 33n-1 in a state of... Thereby, the horizontal start pulse is shifted from the shift register... → 31n + 2 → 31n + 1 → 31n.
Since the shift is performed in the order of → 31n−1 →..., Scanning in the left direction in the figure can be realized.

Shift registers ..., 31n-1, 31n,
31n + 1,... Are transmitted as horizontal scanning pulses to the corresponding buffers (Buf.),.
4n-1, 34n, 34n + 1,... , 34n-1, 34n, 34n + 1,... Convert the horizontal scanning pulses supplied from the shift registers, 31n-1, 31n, 31n + 1,. Analog switch ..., 35n-1, 35n, 35n +
Supply to 1, ...

Analog switches ..., 35n-1, 35
, 35n + 1,... have their output terminals connected to data lines.
4n-1, 24n, 24n + 1,..., And buffers n, 34n-1, 34n, 34n + 1,.
Are turned on by the application of two horizontal scanning pulses having phases opposite to each other, and the respective signal voltages Vsig
, 24n-1, 24n, 24n +
Supply to 1, ...

Thus, the shift registers..., 31n-
, 34n-1, 34n, 34n +
, And two horizontal scanning pulses having phases opposite to each other via analog switches..., 35n-1, 35n, 35n + 1,.
, 35n-1,
.. Perform an on / off operation in order, so that scanning is performed in the horizontal direction, and writing of actual data is executed in a dot-sequential manner.

In order to realize the dot sequential precharge function, buffers..., 34n-1, 34n, 34n +
The two horizontal scanning pulses output in opposite phases from each other are also supplied as precharge timing pulses to, for example, precharge analog switches..., 36n-1, 36n, 36n + 1,. It has become so. That is, two horizontal scanning pulses output from the buffer 34n-1 are output from the analog switch 36n + 1.
, Two horizontal scanning pulses output from the buffer 34n are supplied to the analog switch 36n + 2, and so on.

At this time, in order to cope with scanning in both the left and right directions at the time of horizontal reversal, an analog switch for precharging composed of, for example, a CMOS transistor in a certain column and two output terminals and two A scan direction control switch is interposed between the two output terminals of the buffer at the column destination. For example, for the analog switch 36n + 1 in the (n + 1) th column, two scan direction control switches 37a and 37b are interposed between the two output terminals of the buffer 34n-1 in the (n-1) th column before the second column. Two scan direction control switches (not shown) are interposed between the two output terminals of the buffer 34n + 3 in the (n + 3) th column at the column destination.

Analog switches for precharge..., 3
6n-1, 36n, 36n + 1,... Are analog switches for writing actual data.
, 24n-1, 24n, 24n + 1,... Are connected to one end of each of the data lines... 24n-1, 24n, 24n + 1,. The horizontal scanning pulse is turned on by being applied as a precharge timing pulse, and a precharge voltage Psig having a predetermined amplitude is applied to the corresponding data line..., 24n-1, 24n, 24n + 1,.
... to supply.

For example, the analog switch 36 in the (n + 1) th column
Considering n + 1, when scanning in the right direction, two horizontal scanning pulses of opposite phases are output from the buffer 34n-1 in the (n-1) th column before the second column, and the analog switch 35n-1 is turned on. When the signal voltage Vsig is supplied to the data line 25n-1 in the (n-1) th column in the state, the analog switch 36n + 1 is turned on in response to the two horizontal scanning pulses, whereby n +
Prior to the supply of the signal voltage Vsig to the data line 25n + 1 in the first column, the data line 25n + 1 is precharged by the precharge voltage Psig.

As described above, in the active matrix type liquid crystal display device 10 of the dot sequential precharge system,
A transfer pulse output from the shift register of one of the transfer stages arranged in the horizontal direction is used as a timing pulse for controlling two timings of writing the actual data in the column and precharging the next two columns, for example. By using this, the horizontal point sequential drive circuit 12 can also have a point sequential precharge function.

As a result, in FIG. 1, the horizontal dot sequential driving circuit 12 having the dot sequential precharge function is
Can be arranged only on one side (in this example, on the upper side). In particular, as is apparent from the circuit configuration of FIG. 3, since the circuit configuration of the conventional horizontal dot sequential driving circuit is used as it is and a dot sequential precharge function is added thereto, the dot sequential precharge function is employed. When configuring the horizontal point sequential drive circuit 12 with a function, the space can be reduced to the same level as the conventional horizontal point sequential drive circuit.

[Second Specific Example] FIG. 4 is a block diagram showing a second specific example of the horizontal dot sequential drive circuit 12 with a dot sequential precharge function.

In FIG. 4, the number of the first shift registers (S / R1) corresponding to the number of pixels in the horizontal direction of the pixel section 11 is shown.
, 41n-1, 41n, 41n + 1, ... are provided. First shift register ..., 41n-1, 41n, 4
1n + 1,... Have, for example, a clocked inverter configuration, and have two horizontal clocks H having phases opposite to each other.
The shift operation is performed in synchronization with ck1 and Hck2. These first shift registers ..., 41n-1, 41n, 41n +
Are connected so that scanning can be performed in both the right and left directions in the figure in order to realize horizontal reversal of the screen.

That is, the output terminal of the shift register 41n-1 is connected to the input terminal of the shift register 41n via the scan direction control switch 42n-1.
Is connected to the input terminal of the shift register 41n + 1 via the scan direction control switch 42n.
1n + 1 is the scan direction control switch 42n +
1, to the output terminal of the shift register 41n + 2,.
And so on. Thereby, the horizontal start pulse is shifted from the shift register... → 41n−1 → 41n → 4
Since the shift is performed in the order of 1n + 1 → 41n + 2 →..., Scanning in the right direction in the figure can be realized.

The output terminal of the shift register 41n + 2 is connected to the input terminal of the shift register 41n + 1 via the scan direction control switch 43n + 1, and is connected to the shift register 41n +.
Is connected to the input terminal of the shift register 41n via the scan direction control switch 43n, and is connected to the shift register 41n.
Are connected to the input terminal of the shift register 41n-1 via the scan direction control switch 43n-1 in a state of... As a result, the horizontal start pulse is shifted from the shift register to 41n + 2 to 41n + 1 to 41n.
Since the shift is performed in the order of → 41n−1 →..., The scan in the left direction in the figure can be realized.

First shift registers..., 41n-1, 41
, 41n + 1,... corresponding to the second shift registers,.
44n-1, 44n, 44n + 1,... Are provided. These second shift registers ..., 44n-1, 44
, 41n + 1,..., 41n
.., 41n + 1, 41n + 1,..., For example, has a clocked inverter configuration, and performs a shift operation in synchronization with two horizontal clocks Hck1 and Hck2 having phases opposite to each other.

Then, the first shift register..., 41n-
, 41n, 41n + 1,... Are transferred to the second shift registers,.
, 44n + 1,... respectively. Thereby, as shown in the timing chart of FIG. 5, for each transfer input pulse a of the first shift register..., 41n-1, 41n, 41n + 1,.
, 44n-1, 44n + 1, 44n + 1,... Are transmitted by the horizontal clock Hck (Hck1 / Hck1).
Assuming that the pulse width of Hck2) is tw, the phase relationship is shifted by 2tw (one cycle of the horizontal clock Hck).

Here, the first shift register..., 41n-
Each transfer input pulse a of 1, 41n, 41n + 1,.
, 45n-1, 45n, 45n + 1,..., And a second shift register, 44n-1, 44n,.
, 44n + 1,...
, 45n-1, 45n, 45n + 1,... As second horizontal scanning pulses for writing actual data.

These buffers..., 45n-1, 45n,
45n + 1,... Are second shift registers,.
The horizontal scanning pulse b given from 1, 44n, 44n + 1,... Is converted into two horizontal scanning pulses having phases opposite to each other, and supplied to analog switches, for example, CMOS transistors, 46n-1, 46n, 46n + 1,. First shift register ..., 41n-1, 41n, 41n
+1,... Are converted into two horizontal scanning pulses having phases opposite to each other, and analog switches composed of, for example, CMOS transistors, 47n−1, 47
, 47n + 1,...

Analog switches ..., 46n-1, 46
, 46n + 1,... have their output terminals connected to data lines.
4n-1, 24n, 24n + 1,..., And buffers n, 34n-1, 34n, 34n + 1,.
Are turned on by applying two horizontal scanning pulses having phases opposite to each other based on the horizontal scanning pulse a as the actual data writing timing pulse, and each signal voltage Vsig is turned on to the corresponding data line.
, 24n, 24n + 1,...

Thus, the first shift registers..., 41
Each of the input pulses a of n-1, 41n, 41n + 1,...
, 45n-1, 45n, 45n + 1,... Become two horizontal scanning pulses having phases opposite to each other, and are used as analog switches.
, 47n-1, 47n, 47n + 1,..., And these analog switches,.
Perform an on / off operation sequentially, so that one cycle (2t) of the horizontal clock Hck is performed prior to writing of actual data based on the horizontal scanning pulse a.
w) before the data line ..., 25n-1, 25n, 25n
The precharge voltage Psig is applied to +1,..., And the precharge is performed in a dot-sequential manner.

Further, the second shift register..., 44n-
, 45n-1, 44n + 1,... Are transmitted to buffers.
+1... Become two horizontal scanning pulses having phases opposite to each other, and analog switches..., 46n−1, 46n, 46n + 1,.
, 46n−1,
.. Perform an on / off operation in order, so that scanning is performed in the horizontal direction, and writing of actual data is executed in a dot-sequential manner.

As described above, in the active matrix type liquid crystal display device 10 of the dot sequential precharge system,
One of the transfer stages arranged in the horizontal direction, for example, a transfer pulse output from the shift register 41n-1;
That is, the transfer input pulse of the shift register 41n is delayed by, for example, one cycle (2tw) of the horizontal clock Hck through the serially connected shift registers 41n and 44n as a timing pulse for controlling the writing timing of the actual data in the nth column. The horizontal dot sequential driving circuit 12 can also be provided with a dot sequential precharge function by using it as a timing pulse for directly controlling the timing of precharging of the nth column.

When compared with the horizontal point sequential driving circuit according to the first specific example, the second shift register...
Although the circuit configuration is slightly complicated by the addition of 44n-1, 44n, 44n + 1,..., One timing pulse (transfer pulse) generated in its own transfer stage as in the first specific example. To the analog switch for writing the actual data of the own stage and the wiring for transmitting to the analog switch for the precharge of another stage which is separated by the timing to be precharged, so that the wiring is not required. The horizontal point sequential driving circuit according to this example can reduce the occupied area of the circuit.

Further, since the left-right inversion is also processed by the first shift registers..., 41n-1, 41n, 41n + 1,..., The scanning direction control switches 37a and 37b in FIG. Only the circuit configuration can be simplified. In addition to this, there is the following advantage as the scan direction control switch is not required.

That is, the scan direction control switch 37
Since the MOS transistors constituting the transistors a and 37b have a large resistance, in the case of the first specific example requiring the scan direction control switch, buffers.
, 34n + 1, 34n + 1,... Are required to have a large driving capability, and the size of the driving transistor must be increased accordingly. On the other hand, in the case of the second specific example, since the scan direction control switch is unnecessary, the buffers..., 45n-1, 45n, 45n +
Since it is sufficient to use a small driving capacity as 1,..., The size of the driving transistor can be small, and the area occupied by the circuit can be further reduced accordingly.

In the second specific example, the transfer input pulses of the first shift registers..., 41n-1, 41n, 41n + 1,. Registers…, 41n
, 41n, 41n + 1,... Can be used as a precharge timing pulse in the own stage. However, in this case, it is necessary to add one shift register for timing delay. Therefore, the use of the transfer input pulse as the timing pulse for precharging of the own stage is advantageous in reducing the circuit scale because the number of stages of the shift register for timing delay can be minimized.

Since the precharge operation needs to be performed prior to the writing of the actual data, the timing pulse a for the precharge and the timing pulse b for the actual data writing in the timing chart of FIG. The condition is that they do not overlap.
However, in the horizontal point sequential driving circuit according to the second specific example, the first shift registers..., 41n-1, 41n,
41n + 1,... And the second shift register.
There is a possibility that the pulse widths of both timing pulses a and b fluctuate and overlap due to variations in the circuit elements constituting 1, 44n, 44n + 1,.

Therefore, as a modification of the horizontal point sequential drive circuit according to the second specific example, a circuit configuration for controlling the precharge timing pulse a and the actual data write timing pulse b so as not to overlap is proposed. . Hereinafter, the two modified examples will be described.

[First Modification] FIG. 6 is a block diagram showing a first modification of the horizontal point sequential driving circuit according to the second specific example. In the drawing, the same parts as those in FIG. Is shown. Note that, here, only the circuit configuration in the n-th column is shown to simplify the description and facilitate understanding.

In FIG. 6, the first shift register 41n
Is directly supplied to the buffer 45n as the first horizontal scanning pulse, and the inverter 48
And the inverted pulse c is supplied to the AND gate 49.
Is one of the inputs. A transfer pulse b output from the second shift register 44n is applied to the other input of the NAND gate 49. The polarity of the output pulse d of the NAND gate 49 is inverted by the inverter 50, and the inverted pulse e is supplied to the buffer 45n as a second horizontal scanning pulse.

As described above, by taking the logical product of the inverted pulse c of the transfer input pulse a of the first shift register 41n and the transfer pulse b output from the second shift register 44n, it is clear from the timing chart of FIG. In this way, the precharge timing pulse a and the actual data write timing pulse e can never be overlapped.

For example, the pulse width of the transfer pulse b output from the second shift register 44n fluctuates as shown by the dotted line in FIG. 7, and the transfer input pulse a of the first shift register 41n and the output from the second shift register 44n. Assuming that the transfer pulses b to be transferred overlap each other, the transfer pulse b is ANDed with the inverted pulse c of the transfer input pulse a of the first shift register 41n, so that the NAND
Since the output pulse d of the gate 49 becomes a pulse having the same phase as the transfer input pulse a, the actual data write timing pulse e, which is the inverted pulse thereof, is supplied to the first shift register 41.
There is no overlap with the pre-charge timing pulse a, which is the n transfer input pulses.

[Second Modification] FIG. 8 is a block diagram showing a second modification of the horizontal point sequential driving circuit according to the second specific example. In the drawing, the same parts as those in FIG. Is shown. In the second modification, the shift register, which is a two-stage series connection in the second specific example, is connected in series at three or more stages, and the actual data writing timing with respect to the precharge timing pulse a according to the number of stages. The configuration is such that the delay time of the pulse b can be set arbitrarily. That is, N-stage (N ≧ 3) shift registers..., 4
1n-1, 41n, 41n + 1, ..., 4Nn-
, 4Nn, 4Nn + 1,... Are connected in series for each column (each transfer stage).

As described above, by adopting a configuration in which the shift registers are connected in N stages in series, the actual data write timing pulse b can be delayed from the precharge timing pulse a by a delay time corresponding to the number of stages. it can. Therefore, the precharge timing pulse a and the actual data write timing pulse b never overlap. When the pulse width of the horizontal clock Hck is tw and the number of stages of the shift register is N, the delay time is set to tw × N. FIG. 9 shows a timing relationship when N = 4.

Here, considering the case where the delay time is extended, in the system in which the wires are routed as in the first specific example shown in FIG. 3, buffers..., 34n−1, 34
, 34n + 1,... On the other hand, the circuit configuration according to the second modified example is advantageous in terms of circuit scale because it is only necessary to increase the number of shift registers of the same size one by one in order to increase the delay time.

[0050]

As described above, according to the present invention,
In an active matrix type liquid crystal display device of a point-sequential precharge system, a transfer pulse output from one of a plurality of transfer stages arranged in a horizontal direction is transmitted.
Used as a timing pulse for writing real data and also as a timing pulse for precharging, so that the drive circuit for writing real data in dot-sequential mode also has a dot-sequential precharge function. By doing so, the circuit scale as a peripheral circuit of the pixel portion can be reduced, so that the frame of the liquid crystal panel can be narrowed and the power consumption can be reduced.

Thus, in a liquid crystal display device mounted on a video camera or a digital camera as a monitor,
Since the outer shape can be reduced, it can greatly contribute to downsizing of a video camera and a digital camera.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a basic configuration of a dot-sequential precharge type active matrix liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating an example of a configuration of a pixel portion.

FIG. 3 is a block diagram showing a first specific example of a horizontal dot sequential drive circuit with a dot sequential precharge function.

FIG. 4 is a block diagram showing a second specific example of the horizontal dot sequential drive circuit with a dot sequential precharge function.

FIG. 5 is a timing chart for explaining the operation of the second specific example.

FIG. 6 is a block diagram showing a first modification of the second specific example.

FIG. 7 is a timing chart for explaining the operation of the first modification;

FIG. 8 is a block diagram showing a second modification of the second specific example.

FIG. 9 is a timing chart for explaining the operation of the second modification.

FIG. 10 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

Reference numeral 11 denotes a pixel portion, 12 denotes a horizontal point sequential drive circuit with a dot sequential precharge function, 13 denotes a vertical drive circuit, 20 denotes a pixel, 21
... Thin film transistor, 22 ... Liquid crystal cell, 25n-1,2
5n, 25n + 1, 25n + 2 ... data lines, 31n-
1,31n, 31n + 1,31n + 2,41n-1,4
1n, 41n + 1, 41n + 2, 44n-1, 44n,
44n + 1, 44n + 2... Shift register, 32n−
1,32n, 32n + 1,33n-1,33n, 33n
+1, 42n-1, 42n, 42n + 1, 43n-1,
43n, 43n + 1 ... scan direction control switch, 34
n-1, 34n, 34n + 1, 34n + 2, 45n-
1, 45n, 45n + 1, 45n + 2 ... buffer, 35
n-1, 35n, 35n + 1, 35n + 2, 46n-
1,46n, 46n + 1,46n + 2 ... Analog switch for writing actual data, 36n-1,36n, 36n +
1,36n + 2,47n-1,47n, 47n + 1,4
7n + 2 ... Precharge analog switch

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Meiji Kawamura 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (72) Inventor Mitsuyuki Shirae 6-7-1, Kita-Shinagawa, Shinagawa-ku, Tokyo No. 35 Sony Corporation F term (reference) 2H093 NA42 NC10 NC12 NC16 NC22 ND34 ND39 ND42 ND49 5C006 AC09 AF72 BB16 BC12 BC16 BF03 BF26 BF27 BF34 FA16 FA41 FA47 5C080 AA10 BB05 DD22 DD26 FF11 JJ02 JJ04

Claims (5)

[Claims] 1. A display device, comprising:
A first switch group for selectively supplying a signal to the data line; a second switch group for selectively applying a predetermined voltage to the data line prior to the supply of a signal to the data line; And the switches of the second switch group are sequentially operated based on transfer pulses output from each transfer stage, and based on transfer pulses output from the same transfer stage. A liquid crystal display device comprising: a driving circuit for sequentially operating each switch of the first switch group. 2. The drive circuit according to claim 1, wherein the drive circuit operates a switch separated by a predetermined number of transfer stages among the switches of the first and second switch groups based on a transfer pulse output from the same transfer stage. 2. The liquid crystal display device according to claim 1, wherein 3. A driving circuit comprising: a first transfer stage group for sequentially outputting transfer pulses; and a first delay unit for delaying a transfer pulse output from each transfer stage of the first transfer stage group by a predetermined delay time. Two transfer stage groups, and sequentially operates the switches of the second switch group based on a transfer input pulse or a transfer output pulse of each transfer stage of the first transfer stage group, and performs the same transfer. 2. The liquid crystal display device according to claim 1, wherein each switch of the first switch group is sequentially operated based on a transfer pulse output from a stage and passing through a corresponding transfer stage of the second transfer stage group. . 4. The driving circuit according to claim 2, wherein said driving circuit outputs an inverted pulse obtained by inverting the polarity of a transfer input pulse or a transfer output pulse of each transfer stage of said first transfer stage group and said second transfer signal output from the same transfer stage. An AND gate for performing an AND operation with a transfer pulse that has passed through a corresponding transfer stage of the stage group, wherein each switch of the first switch group is sequentially operated based on an output pulse of the AND gate. The liquid crystal display device according to claim 3. 5. The transfer circuit according to claim 3, wherein the second transfer stage group includes a plurality of serially connected transfer stages for each transfer stage of the first transfer stage group. Liquid crystal display.