CN101257040B - Semiconductor device with gate stack structure - Google Patents
Semiconductor device with gate stack structure Download PDFInfo
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- CN101257040B CN101257040B CN 200710305601 CN200710305601A CN101257040B CN 101257040 B CN101257040 B CN 101257040B CN 200710305601 CN200710305601 CN 200710305601 CN 200710305601 A CN200710305601 A CN 200710305601A CN 101257040 B CN101257040 B CN 101257040B
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- silicide
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims abstract description 675
- 229910052751 metal Inorganic materials 0.000 claims abstract description 250
- 239000002184 metal Substances 0.000 claims abstract description 250
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 160
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 160
- 229910052721 tungsten Inorganic materials 0.000 claims description 433
- 239000010937 tungsten Substances 0.000 claims description 428
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 424
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 401
- 239000010936 titanium Substances 0.000 claims description 316
- 229910052719 titanium Inorganic materials 0.000 claims description 257
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 254
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical group [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 230
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 230
- 229910052757 nitrogen Inorganic materials 0.000 claims description 213
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 154
- 229920005591 polysilicon Polymers 0.000 claims description 128
- 229910052715 tantalum Inorganic materials 0.000 claims description 120
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 118
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 87
- 238000005477 sputtering target Methods 0.000 claims description 86
- 238000005546 reactive sputtering Methods 0.000 claims description 70
- 238000004062 sedimentation Methods 0.000 claims description 67
- 229910052710 silicon Inorganic materials 0.000 claims description 54
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 53
- 239000010703 silicon Substances 0.000 claims description 53
- 239000012535 impurity Substances 0.000 claims description 50
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 claims description 50
- 229910052732 germanium Inorganic materials 0.000 claims description 15
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 13
- 230000009977 dual effect Effects 0.000 claims description 7
- 239000010410 layer Substances 0.000 description 1259
- 238000000034 method Methods 0.000 description 156
- 238000005240 physical vapour deposition Methods 0.000 description 101
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical group [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 51
- 238000005229 chemical vapour deposition Methods 0.000 description 51
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 51
- 238000004544 sputter deposition Methods 0.000 description 48
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 42
- 239000011651 chromium Substances 0.000 description 34
- 238000000137 annealing Methods 0.000 description 32
- 238000000059 patterning Methods 0.000 description 29
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 27
- 229910052796 boron Inorganic materials 0.000 description 27
- 229910052698 phosphorus Inorganic materials 0.000 description 19
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 17
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 17
- 229910052804 chromium Inorganic materials 0.000 description 17
- 229910017052 cobalt Inorganic materials 0.000 description 17
- 239000010941 cobalt Substances 0.000 description 17
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 17
- 229910052735 hafnium Inorganic materials 0.000 description 17
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 17
- 229910052759 nickel Inorganic materials 0.000 description 17
- 239000011574 phosphorus Substances 0.000 description 17
- 229910052697 platinum Inorganic materials 0.000 description 17
- VSZWPYCFIRKVQL-UHFFFAOYSA-N selanylidenegallium;selenium Chemical compound [Se].[Se]=[Ga].[Se]=[Ga] VSZWPYCFIRKVQL-UHFFFAOYSA-N 0.000 description 17
- 230000015572 biosynthetic process Effects 0.000 description 16
- 150000003657 tungsten Chemical class 0.000 description 16
- 229910052581 Si3N4 Inorganic materials 0.000 description 12
- 229910008484 TiSi Inorganic materials 0.000 description 12
- 238000006243 chemical reaction Methods 0.000 description 12
- 230000000593 degrading effect Effects 0.000 description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 12
- 238000009792 diffusion process Methods 0.000 description 11
- -1 tungsten nitride Chemical class 0.000 description 11
- 230000000694 effects Effects 0.000 description 9
- 239000000463 material Substances 0.000 description 9
- 239000012212 insulator Substances 0.000 description 8
- 238000005530 etching Methods 0.000 description 6
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 5
- 229910007991 Si-N Inorganic materials 0.000 description 4
- 229910006294 Si—N Inorganic materials 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- QGLKJKCYBOYXKC-UHFFFAOYSA-N nonaoxidotritungsten Chemical compound O=[W]1(=O)O[W](=O)(=O)O[W](=O)(=O)O1 QGLKJKCYBOYXKC-UHFFFAOYSA-N 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 150000003481 tantalum Chemical class 0.000 description 2
- 229910001930 tungsten oxide Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910008807 WSiN Inorganic materials 0.000 description 1
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 1
- 238000005054 agglomeration Methods 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 1
- 150000003608 titanium Chemical class 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
A semiconductor device having a grid stacking structure includes a first conductive layer, a first intermediate structure over the first conductive layer, a second intermediate structure over the first intermediate structure, and a second conductive layer over the second intermediate structure. The first intermediate structure includes a metal silicide layer and a nitrogen containing metal layer. The second intermediate structure includes at least a nitrogen containing metal silicide layer.
Description
Cross-reference to related applications
The present invention requires the priority of the korean patent application that proposes on December 27th, 2006 and on April 27th, 2007 10-2006-0134326 number and 10-2007-0041288 number, incorporates in full by reference.
Technical field
The present invention relates to a kind of semiconductor device, more specifically relate to a kind of semiconductor device with gate stack structure.
Background technology
Have low-down resistance by stacking polysilicon and the formed tungsten polygate electrodes of tungsten, this low-down resistance is about by stacking polysilicon and the formed polysilicon/tungsten silicide (Poly-Si/WSi of tungsten silicide
x) gate electrode resistance 1/5 to 1/10.Therefore, tungsten polysilicon gate electrode is that manufacturing Asia-60nm memory device is necessary.
Figure 1A to 1C illustrates typical tungsten polysilicon gate stacked structure.Shown in Figure 1A, form tungsten polysilicon gate stacked structure by sequence stack polysilicon layer 11, tungsten nitride (WN) layer 12 and tungsten (W) layer 13.WN layer 12 is as diffusion impervious layer.
During subsequent anneal process or gate re-ox process, make the nitrogen in the WN layer 12 between tungsten layer 13 and polysilicon layer 11, resolve into for example SiN
xAnd SiO
xN
yNon-uniform insulation layer.This non-uniform insulation layer has the thickness of about 2nm to 3nm scope.Therefore, under the frequency of operation of hundreds of megahertzes (MHz) and 1.5V or less operating voltage, may cause for example device error of signal delay.Recently, between polysilicon layer 11 and WN layer 12, formed thin tungsten silicide (WSi
x) or titanium (Ti) layer as diffusion impervious layer, to prevent formation Si-N key between tungsten layer 13 and polysilicon layer 11.
As shown in Figure 1B, if between polysilicon layer 11 and WN layer 12, form tungsten silicide (WSi
x) layer 14, then by employed nitrogen plasma during the formation of WN layer 12, at WSi
xLayer 14 top form the W-Si-N key.Known W-Si-N is the good diffusion barrier layer with metallic character.
Shown in Fig. 1 C, if form titanium (Ti) layer 15 between polysilicon layer 11 and WN layer 12, then in the reactive sputtering process during the formation of WN layer 12, nitrogen plasma is transformed into titanium nitride (TiN) with the titanium of titanium layer 15.The TiN layer is as diffusion impervious layer.As a result, although WN layer 12 is decomposed during the subsequent thermal process, this TiN prevents that nitrogen to polysilicon layer 11 diffusions, therefore, can reduce the formation of Si-N effectively.
Yet, the tungsten polysilicon gate is being applied to dual poly grid [that is N that, is used for N-type metal oxide semiconductor field-effect transistor (NMOSFET)
+-type polycrystalline silicon gate and be used for the P of P-type metal oxide semiconductor field-effect transistor (PMOSFET)
+-type polycrystalline silicon gate] situation under, if in this tungsten polysilicon gate, use WSi
x/ WN diffusing block structure then can significantly increase tungsten layer and P
+Contact resistance between the-type polysilicon layer.On the contrary, if in the tungsten polysilicon gate, use Ti/WN diffusing block structure, then tungsten layer and P
+Contact resistance between-type polysilicon layer is lower and irrelevant with the polysilicon doping material.
At the P that is used for PMOSFET
+In the situation of-type polysilicon, can in the inverted status as actual mode of operation, produce poly-Si depletion effect.The generation of poly-Si depletion effect can be depending at P
+The amount of the boron that keeps in-type the polysilicon.
At WSi
xCan produce than poly-Si depletion effect larger in the Ti/WN diffusing block structure in the/WN diffusing block structure.Therefore, this WSi
x/ WN diffusing block structure may reduce transistor characteristic.As a result, because the generation that the Ti/WN diffusing block structure can provide low contact resistance and prevent P-type depletion of polysilicon between tungsten layer and polysilicon layer, so the Ti/WN diffusing block structure is used in suggestion.
Yet, if use the Ti/WN diffusing block structure, may make the sheet resistor (Rs) of the tungsten (W) that above this Ti/WN diffusing block structure, directly forms increase about 1.5 to 2 times.Therefore, sheet resistor (Rs) is increased in future and may affects the development of tungsten polysilicon gate.
Summary of the invention
Embodiment of the present invention relate to a kind of gate stack that comprises the semiconductor device of intermediate structure, and wherein this intermediate structure has low sheet resistor and contact resistance, and can effectively prevent impurity to outdiffusion, and relate to a kind of method of making this gate stack.
According to an aspect of the present invention, provide a kind of semiconductor device.This semiconductor device comprises: the first conductive layer; Be positioned at the first intermediate structure of this first conductive layer top, this first intermediate structure comprises metal silicide layer and nitrogen containing metal layer; Be positioned at the second intermediate structure of this first intermediate structure top, this second intermediate structure comprises the nitrogen containing metal silicide layer at least; With the second conductive layer that is positioned at this second intermediate structure top.
According to a further aspect in the invention, provide a kind of semiconductor device.This semiconductor device comprises: the first conductive layer; Intermediate structure, it is formed on this first conductive layer top and comprises at least the first metal layer and nitrogen containing metal silicide layer; With the second conductive layer, it is formed on this intermediate structure top.
According to another aspect of the invention, provide a kind of semiconductor device.This semiconductor device comprises: the first conductive layer; Intermediate structure, it is positioned on this first conductive layer and comprises the first metal layer, the second metal level, metal silicide layer and the 3rd metal level; With the second conductive layer that is positioned at this intermediate structure top.
Description of drawings
Figure 1A to 1C illustrates the gate stack structure of typical tungsten polysilicon gate.
Fig. 2 A illustrates various types of intermediate structures at the figure of the contact resistance of tungsten and inter polysilicon.
Fig. 2 B is the figure of depth profile that the boron concentration of various types of gate stack structures is shown.
Fig. 2 C is the figure that the sheet resistor of various types of intermediate structures is shown.
Fig. 3 A illustrates the gate stack structure according to the first embodiment of the present invention.
Fig. 3 B is forming the image that obtains after the tungsten silicon-nitride layer by physical vapour deposition (PVD) (PVD) method above the top of tungsten nitride layer.
Fig. 3 C illustrates the gate stack structure according to the second embodiment of the present invention.
Fig. 3 D illustrates the gate stack structure according to the 3rd embodiment of the present invention.
Fig. 3 E is illustrated in the image of the gate stack structure after the annealing process.
Fig. 4 A illustrates the gate stack structure according to the 4th embodiment of the present invention.
Fig. 4 B illustrates the gate stack structure according to the 5th embodiment of the present invention.
Fig. 4 C illustrates the gate stack structure according to the 6th embodiment of the present invention.
Fig. 5 A illustrates the canopy stacks structure according to the 7th embodiment of the present invention.
Fig. 5 B illustrates the gate stack structure according to the 8th embodiment of the present invention.
Fig. 5 C illustrates the canopy stacks structure according to the 9th embodiment of the present invention.
Fig. 6 A illustrates the canopy stacks structure according to the tenth embodiment of the present invention.
Fig. 6 B illustrates the canopy stacks structure according to the 11 embodiment of the present invention.
Fig. 6 C illustrates the canopy stacks structure according to the 12 embodiment of the present invention.
Fig. 7 A illustrates the gate stack structure according to the 13 embodiment of the present invention.
Fig. 7 B is illustrated in by implementing corresponding chemical vapour deposition (CVD) (CVD) and physical vapour deposition (PVD) (PVD) method at the image that the structure that provides behind the tungsten silicide layer is provided above the nitrogenous tungsten layer.
Fig. 7 C illustrates the canopy stacks structure according to the 14 embodiment of the present invention.
Fig. 7 D illustrates the gate stack structure according to the 15 embodiment of the present invention.
Fig. 8 illustrates the gate stack structure according to the 16 embodiment of the present invention.
Fig. 9 is the figure that illustrates according to the sheet resistor of the tungsten electrode of various types of intermediate structures of embodiment of the present invention.
Figure 10 A to 10C is the profile that illustrates according to the gate pattern method of gate stack structure shown in the acquisition 3A figure of embodiment of the present invention.
Figure 11 is the profile that the gate pattern method of using the gate stack structure shown in Fig. 3 A is shown.
Embodiment
Fig. 2 A illustrates as each class formation of diffusion impervious layer figure at the contact resistance of tungsten and inter polysilicon.Can be observed when using tungsten silicide (WSi
xWhen)/tungsten nitride (WN) or titanium (Ti)/WN structure substitute tungsten nitride (WN) structure, can significantly improve at the polysilicon (N that is doped with N-type impurity
+POLY-Si) and the contact resistance between the tungsten (W), indicate with Rc.
Yet, the tungsten polysilicon gate is being applied to dual poly grid [that is N that, is used for N-type metal oxide semiconductor field-effect transistor (NMOSFET)
+-type polycrystalline silicon gate and be used for the P of P-type metal oxide semiconductor field-effect transistor (PMOSFET)
+-type polycrystalline silicon gate] situation under, if in the tungsten polysilicon gate, use WSi
x/ WN structure then significantly increases W and P
+-type polysilicon (P
+POLY-Si) contact resistance between.On the contrary, if in the tungsten polysilicon gate, use Ti/WN structure, then W and P
+The contact resistance of-type inter polysilicon shows low-level and has nothing to do with the polysilicon doping material.
At the P that is used for PMOSFET
+In the situation of-type polysilicon, can in the inverted status as actual mode of operation, produce poly-Si depletion effect.The generation of poly-Si depletion effect is depended at P
+The amount of the boron that keeps in-type the polysilicon.
Fig. 2 B is the figure of depth profile that the boron concentration of various types of gate stack structures is shown.As at WSi
xShown in/WN the structure, (for example: oxide skin(coating)) interface surface with inter polysilicon is low to moderate about 5 * 10 to boron concentration at gate insulator
19Atom/cm
3When using the Ti/WN structure, boron concentration measured on same position is greater than about 8 * 10
19Atom/cm
3As a result, polysilicon is at WSi
xIn/WN the structure than in the Ti/WN structure, exhausting manyly, thereby WSi
x/ WN Structure Decreasing transistor characteristic.
Therefore, use the Ti/WN structure better, this Ti/WN structure is provided at the low contact resistance between W and the polysilicon and prevents P-type depletion of polysilicon.Yet there is restriction in the application of Ti/WN structure.The sheet resistor (Rs) of the W that forms at the Ti/WN superstructure increases about 1.5 to 2 times.Will this restriction of more detailed description in Fig. 2 C.
Fig. 2 C is the figure that illustrates as the sheet resistor of the W of various types of structures of diffusion impervious layer.The sheet resistor of tungsten (W) is denoted as Rs.Usually, can be at polysilicon layer, silica (SiO
2) layer, silicon nitride (Si
3N
4) layer and WSi
xLayer top forms the nitrogenous tungsten (WN of amorphous
x) layer, thereby can form the have low resistivity W of (that is, in the scope of about 15 μ Ω-cm to 20 μ Ω-cm) thereon.Yet, forming the tungsten with relative little crystallite dimension as titanium (Ti), tungsten (W) and the tantalum (Ta) of pure polycrystalline metal and as the titanium nitride (TiN) of metal nitride materials and tantalum nitride (TaN) top.Therefore, form the tungsten of the high specific resistance with about 30 μ Ω-cm thereon.The increase of the W sheet resistor that application Ti/WN structure causes may produce restriction to the future development of tungsten polysilicon gate.
According to the various embodiments of the present invention that hereinafter will describe, the intermediate structure of dissimilar gate stacks is formed with a plurality of thin layers that a plurality of thin layers of comprising Ti, W, silicon (Si) or nitrogen (N) or each layer comprise nitrogen.This intermediate structure is as diffusion impervious layer, and this diffusion impervious layer can reduce contact resistance and sheet resistor, and prevent impurity penetrate and to outdiffusion.
In following embodiment, term " nitrogenous layer/structure (layer/structure containingnitrogen or nitrogen containing layer/structure) " expression nitrided metal layer/structure and the metal level/structure that contains the nitrogen of certain content/weight ratio.And, WSi
xN
yIn x represent silicon to the ratio of tungsten, its scope is from about 0.5 to 3.0, and y represents nitrogen to the ratio of tungsten silicide, its scope is from about 0.01 to 10.00.
Fig. 3 A illustrates the gate stack structure according to the first embodiment of the present invention.This canopy stacks structure comprises the first conductive layer 21, intermediate structure 22 and the second conductive layer 23 that order forms.The first conductive layer 21 comprises for example boron or the N-type impurity polysilicon layer of phosphorus for example of highly doped P-type impurity.The first conductive layer 21 also can comprise polysilicon germanium layer (Si
1-xGe
x, wherein x is in about scope of 0.01 to 1.0) or silicide layer.For example, this silicide layer comprises the silicide that is selected from nickel (Ni), chromium (Cr), cobalt (Co), titanium (Ti), tungsten (W), tantalum (Ta), hafnium (Hf), zirconium (Zr) and platinum (Pt).
The second conductive layer 23 comprises tungsten layer.This tungsten layer thickness is about 100
To 2,000
, and by implementing physical vapour deposition (PVD) (PVD) method, chemical vapour deposition (CVD) (CVD) method or the formation of ald (ALD) method.The PVD method comprises the sputtering method that uses the tungsten sputtering target.
In nitrogenous tungsten silicide layer 22C silicon to the ratio of tungsten in about scope of 0.5 to 3.0, and the nitrogen content of nitrogenous tungsten silicide layer 22C about 10% to about 60% scope.Nitrogenous tungsten silicide layer 22C represents nitrogenize tungsten silicide layer (that is, tungsten silicon-nitride layer) or contains the tungsten silicide layer of the nitrogen of certain content/weight ratio.The formed thickness of nitrogenous tungsten silicide layer 22C is about 20
To about 200
Scope in.
Particularly, because above nitrogenous tungsten layer 22B, be difficult for the nitrogenous tungsten silicide layer 22C of growth, so use PVD rule such as reactive sputtering sedimentation to form nitrogenous tungsten silicide layer 22C.If form nitrogenous tungsten silicide layer 22C by implementing the CVD method, the nitrogenous tungsten silicide layer 22C that then can't evenly grow above nitrogenous tungsten layer 22B makes its caking (agglomerated) thus.Owing to above nitrogenous tungsten layer 22B, have tungsten oxide (WO
x) layer, thereby weaken adhesive force by the formed nitrogenous tungsten silicide layer 22C of CVD method, so cause this caking.Yet, in nitrogen environment, utilize the tungsten silicide sputtering target to implement the reactive sputtering sedimentation and allow the evenly nitrogenous tungsten silicide layer 22C of formation and irrelevant with bottom-layer-type.
Fig. 3 B is forming the image that obtains behind the nitrogenous tungsten silicide layer by physical vapour deposition (PVD) (PVD) method above the top of nitrogenous tungsten layer.Use the reactive sputtering sedimentation as the PVD method, above nitrogenous tungsten layer, to be formed uniformly nitrogenous tungsten silicide layer.Reference numeral WSiN and WN represent respectively nitrogenous tungsten silicide layer and nitrogenous tungsten layer.
According to the first embodiment of the present invention, gate stack structure comprises the first conductive layer 21, Ti/WN
x/ WSi
xN
yIntermediate structure and the second conductive layer 23.The first conductive layer 21 comprises polysilicon, and the second conductive layer 23 comprises tungsten, forms thus tungsten polysilicon gate stacked structure.
Particularly, Ti/WN
x/ WSi
xN
yIntermediate structure comprises the stacked structure of the first metal layer, the second metal level and nitrogen containing metal silicide layer.More specifically, the first metal layer, the second metal level and nitrogen containing metal silicide layer comprise respectively simple metal layer, nitrogen containing metal layer and nitrogen containing metal silicide layer.For example, the first metal layer, the second metal level and nitrogen containing metal silicide layer are respectively titanium layer 22A, nitrogenous tungsten (WN
x) layer 22B and nitrogenous tungsten silicide (WSi
xN
y) layer 22C.
The intermediate structure that comprises above-mentioned multilayer also can form other different structure.For example, except titanium layer, the first metal layer also comprises tantalum (Ta) layer, and except nitrogenous tungsten layer, the second metal level also comprises nitrogenous titanium tungsten layer.Except nitrogenous tungsten silicide layer, the nitrogen containing metal silicide layer also comprises nitrogenous titanium silicide layer or nitrogenous silication tantalum layer.Form the Ta layer by PVD method, CVD method or the ALD method of implementing to comprise sputter.Form nitrogenous titanium tungsten layer by in nitrogen environment, utilizing titanium tungsten sputtering target to implement the reactive sputtering sedimentation.Form nitrogenous titanium silicide layer and nitrogenous silication tantalum layer by in nitrogen environment, utilizing corresponding titanium silicide and tantalum silicide sputtering target to implement the reactive sputtering sedimentation.The formed thickness of Ta layer is about 10
To 80
The formed thickness of every one deck in nitrogenous titanium tungsten layer, nitrogenous titanium silicide layer and the nitrogenous silication tantalum layer is about 20
To 200
, and every one deck has about nitrogen content of 10% to 60%.In nitrogenous titanium tungsten layer, titanium to the ratio of tungsten in about scope of 0.5 to 3.0.In nitrogenous titanium silicide layer, silicon to the ratio of titanium in about scope of 0.5 to 3.0.In nitrogenous silication tantalum layer, silicon to the ratio of tantalum in about scope of 0.5 to 3.0.
Fig. 3 C illustrates the gate stack structure according to the second embodiment of the present invention.Particularly, this gate stack structure is the exemplary gate stack structure of revising from according to the gate stack structure of the first embodiment of the present invention.In other words, this gate stack structure comprises the nitrogenous titanium layer in order to the titanium layer 22A shown in the alternate figures 3A, and this nitrogenous titanium layer is denoted as TiN
x, wherein x is less than about 1.
Canopy stacks structure according to the second embodiment comprises the first conductive layer 201, intermediate structure 202 and the second conductive layer 203.The first conductive layer 201 comprises for example boron (B) or the N-type impurity polysilicon layer of phosphorus (P) for example of highly doped P-type impurity.Except this polysilicon layer, the first conductive layer 201 also can comprise polycrystalline silicon germanium (Si
1-xGe
x) layer, wherein x perhaps comprises silicide layer in about scope of 0.01 to 1.0.This silicide layer comprises the silicide that is selected from nickel (Ni), chromium (Cr), cobalt (Co), titanium (Ti), tungsten (W), tantalum (Ta), hafnium (Hf), zirconium (Zr) and platinum (Pt).
The second conductive layer 203 comprises tungsten layer.One of them of enforcement PVD method, CVD method and ALD method is to form about 100
To 2,000
Thick tungsten layer.This PVD method comprises the sputtering method that utilizes the tungsten sputtering target.
In nitrogenous tungsten silicide layer 202C silicon to the ratio of tungsten in about 0.5 and 3.0 scope, and the nitrogen content of nitrogenous tungsten silicide layer 202C about 10% to about 60% scope.Nitrogenous tungsten silicide layer 202C represents the tungsten silicon-nitride layer or contains the tungsten silicide layer of the nitrogen of certain content/weight ratio.
Form nitrogenous tungsten layer 202B by implementing PVD method, CVD method or ALD method.Form nitrogenous titanium layer 202A and nitrogenous tungsten silicide layer 202C by implementing the PVD method.This PVD method is carried out sputtering method or reactive sputtering sedimentation.For example, form nitrogenous titanium layer 202A by in nitrogen environment, utilizing the titanium sputtering target to implement sputtering method.Form nitrogenous tungsten layer 202B by in nitrogen environment, utilizing the tungsten sputtering target to implement the reactive sputtering sedimentation.Form nitrogenous tungsten silicide layer 202C by in nitrogen environment, utilizing the tungsten silicide sputtering target to implement the reactive sputtering sedimentation.
Particularly, because above nitrogenous tungsten layer 202B, be difficult for the nitrogenous tungsten silicide layer 202C of growth, so use PVD rule such as reactive sputtering sedimentation to form nitrogenous tungsten silicide layer 202C.If form nitrogenous tungsten silicide layer 202C by implementing the CVD method, the nitrogenous tungsten silicide layer 202C that then can't evenly grow above nitrogenous tungsten layer 202B makes its caking thus.Because above nitrogenous tungsten layer 202B, have tungsten oxide (WO
x) layer, it weakens the adhesive force by the formed nitrogenous tungsten silicide layer 202C of CVD method, so cause this caking.Yet, in nitrogen environment, utilize the tungsten silicide sputtering target to implement the reactive sputtering sedimentation and allow the evenly nitrogenous tungsten silicide layer 202C of formation and irrelevant with bottom-layer-type.
When use is similar to nitrogenous titanium layer 202A in the second embodiment of the titanium layer 22A in the first embodiment, can obtain low contact resistance.The reason of this low contact resistance is because formed nitrogenous tungsten layer 202B supply nitrogen to nitrogenous titanium layer 202A, makes the top of nitrogenous titanium layer 202A firm and prevent simultaneously the agglomeration of titanium-silicon key thus.
Gate stack structure according to the second embodiment of the present invention comprises the first conductive layer 201, TiN
x/ WN
x/ WSi
xN
yIntermediate structure 202 and the second conductive layer 203.The first conductive layer 201 comprises polysilicon, and the second conductive layer 203 comprises tungsten, forms thus tungsten polysilicon gate stacked structure.
Particularly, TiN
x/ WN
x/ WSi
xN
yIntermediate structure 202 forms the stacked structure that comprises the first metal layer, the second metal level and nitrogen containing metal silicide layer.This first and second metal level is the metal level that contains the nitrogen of certain content/weight ratio, and this nitrogen containing metal silicide layer comprises the nitrogen of certain content/weight ratio.For example, this first metal layer is nitrogenous titanium layer 202A.This second metal level is nitrogenous tungsten layer 202B.This metal silicide layer is nitrogenous tungsten silicide layer 202C.
Above-mentioned multilayer intermediate structure also can form other different structure.For example, except nitrogenous titanium layer, this first nitrogen containing metal layer also comprises nitrogenous tantalum (TaN
x) layer, and except nitrogenous tungsten layer, this second nitrogen containing metal layer also comprises nitrogenous titanium tungsten (TiWN
x) layer.Except nitrogenous tungsten silicide layer, this nitrogen containing metal silicide layer also comprises nitrogenous titanium silicide (TiSi
xN
y) layer or nitrogenous tantalum silicide (TaSi
xN
y) layer.By implementing to comprise that PVD method, CVD method or the ALD method of sputter form nitrogenous tantalum layer.Form nitrogenous titanium tungsten layer by in nitrogen environment, utilizing titanium tungsten sputtering target to implement the reactive sputtering sedimentation.Form nitrogenous titanium silicide layer and nitrogenous silication tantalum layer by in nitrogen environment, utilizing corresponding titanium silicide and tantalum silicide sputtering target to implement the reactive sputtering sedimentation.The formed thickness of nitrogenous tantalum layer is about 10
To 80
The formed thickness of every one deck in nitrogenous titanium tungsten layer, nitrogenous titanium silicide layer and the nitrogenous silication tantalum layer is about 20
To 200
, and every one deck has the nitrogen content in about 10% and 60% scope.In nitrogenous titanium tungsten layer, titanium to the ratio of tungsten in about scope of 0.5 to 3.0.In nitrogenous titanium silicide layer, silicon to the ratio of titanium in about scope of 0.5 to 3.0.In nitrogenous silication tantalum layer, silicon to the ratio of tantalum in about scope of 0.5 to 3.0.
Be similar to TiN
x/ WN
x/ WSi
xN
yIntermediate structure comprises that the intermediate structure of the nitrogenous tantalum layer that substitutes nitrogenous titanium layer can have low contact resistance and sheet resistor, and prevents simultaneously depletion of polysilicon.Although the intermediate structure according to the second embodiment forms 3 layers, this intermediate structure may further include at the nitrogenous tungsten (WN that contains above the silication tungsten layer
x) layer.The essentially identical thickness of nitrogenous tungsten layer and the nitrogen content that provides with first is provided this nitrogenous tungsten layer that additionally provides.TiN according to the second embodiment
x/ WN
x/ WSi
xN
yA plurality of layers of intermediate structure comprise nitrogen.As a result, TiN
x/ WN
x/ WSi
xN
yIntermediate structure can have the height of low sheet resistor and contact resistance and minimizing gate stack structure.And, TiN
x/ WN
x/ WSi
xN
yIntermediate structure can reduce because the impurity that the mixes depletion of polysilicon that causes to outdiffusion of boron for example in the first conductive layer 201.
Fig. 3 D illustrates the gate stack structure according to the 3rd embodiment of the present invention.This gate stack structure comprises the first conductive layer 211, intermediate structure 212 and the second conductive layer 213.The first conductive layer 211 comprises for example boron (B) or the N-type impurity polysilicon layer of phosphorus (P) for example of highly doped P-type impurity.Except polysilicon layer, the first conductive layer 211 also can comprise polycrystalline silicon germanium (Si
1-xGe
x) layer, wherein x perhaps can comprise silicide layer in about scope of 0.01 to 1.0.This silicide layer comprises the silicide that is selected from nickel (Ni), chromium (Cr), cobalt (Co), titanium (Ti), tungsten (W), tantalum (Ta), hafnium (Hf), zirconium (Zr) and platinum (Pt).
The second conductive layer 213 comprises tungsten layer.One of them of enforcement PVD method, CVD method and ALD method forms about 100
To 2,000
The tungsten layer of thickness.This PVD method comprises the sputtering method that uses the tungsten sputtering target.
Gate stack structure according to the 3rd embodiment is at the resulting structures to implementing according to the gate stack structure of the first and second embodiments of the present invention to provide after the annealing in process.This annealing is included in and forms the heat treatment of following during the various processes (for example: sept forms and interlayer insulating film forms) of implementing behind this gate stack structure.
With reference to figure 3A and 3D, compare intermediate structure 212 and intermediate structure 22.When titanium layer 22A with from the reaction of the polysilicon of the first conductive layer 21 time, form and have about 1
To 30
The titanium silicide layer 212A of thickness.Silicon among the titanium silicide layer 212A to the ratio of titanium in about scope of 0.5 to 3.0.
When supplying nitrogen to titanium layer 22A from nitrogenous tungsten layer 22B, obtain nitrogenous titanium layer 212B.Nitrogenous titanium layer 212B has about 10
To 100
Thickness and have the nitrogen of about 0.7 to 1.3 scope to the ratio of titanium.Compared to the ratio of the nitrogen in titanium layer 22A to titanium, the nitrogen in nitrogenous titanium layer 212B increases to about 0.7 to 1.3 to the ratio of titanium from about 0.
After annealing, nitrogenous tungsten layer 212C has and is down to about 10% or still less nitrogen content because degrading (denudation).Reference numeral WN
x(D) represent this nitrogenous tungsten layer through degrading.Nitrogenous tungsten layer 212C is about 20
To 200
Thick.Nitrogen in nitrogenous tungsten layer 212C to the ratio of tungsten in about 0.01 and 0.15 scope.With the nitrogen in the nitrogenous tungsten layer 22B shown in Fig. 3 A the ratio of tungsten is compared, the nitrogen in nitrogenous tungsten layer 212C is reduced to about scope of 0.01 to 0.15 to the ratio of tungsten from about scope of 0.3 to 1.5.
Nitrogenous tungsten silicide layer 212D has thickness and the composition roughly the same with nitrogenous tungsten silicide layer 22C.Specifically, nitrogenous tungsten silicide layer 212D has the silicon of about 0.5 to 3.0 scope to the ratio of tungsten and the nitrogen content of about 10% to 60% scope.The thickness of nitrogenous tungsten silicide layer 212D is about 20
To 200
Scope in.
With reference to figure 3D and 3C, compare intermediate structure 212 and intermediate structure 202.During annealing in process, from nitrogenous tungsten layer 202B supply nitrogen to nitrogenous titanium layer 202A.As a result, make nitrogenous titanium layer 202A is transformed into minimal reaction with titanium silicide layer 212A nitrogenous titanium layer 212B.The thickness of titanium silicide layer 212A is about 1
To 30
Scope in, and the thickness of nitrogenous titanium layer 212B is about 10
To 100
Scope in.
Nitrogen among the nitrogenous titanium layer 212B to the ratio of titanium in about scope of 0.7 to 1.3.With the nitrogen among the nitrogenous titanium layer 202A titanium ratio is compared, the nitrogen in nitrogenous titanium layer 212B increases to about scope of 0.7 to 1.3 to the titanium ratio from about scope of 0.2 to 0.8.
After annealing, nitrogenous tungsten layer 212C is down to about 10% or still less nitrogen content because degrading to have.Nitrogenous tungsten layer 212C thick about 20
To 200
Nitrogen among the nitrogenous tungsten layer 212C to the ratio of tungsten in about scope of 0.01 to 0.15.With the nitrogen among the nitrogenous tungsten layer 202B shown in Fig. 3 C the ratio of tungsten is compared, the nitrogen among the nitrogenous tungsten layer 212C is reduced to about scope of 0.01 to 0.15 to the ratio of tungsten from about scope of 0.3 to 1.5.
Nitrogenous tungsten silicide layer 212D has thickness and the composition roughly the same with nitrogenous tungsten silicide layer 202C.Specifically, nitrogenous tungsten silicide layer 212D has the silicon of about 0.5 to 3.0 scope to the ratio of tungsten and the nitrogen content of about 10% to 60% scope.The thickness of nitrogenous tungsten silicide layer 212D is about 20
To 200
Scope in.
Gate stack structure according to the 3rd embodiment comprises the first intermediate structure and the second intermediate structure.The first intermediate structure comprises the first metal silicide layer and the first nitrogen containing metal layer, and the second intermediate structure comprises the second nitrogen containing metal layer and the second nitrogen containing metal silicide layer.For example, form the first intermediate structure by stacking titanium silicide layer 212A and nitrogenous titanium layer 212B.Form the second intermediate structure by stacking nitrogenous tungsten layer 212C and nitrogenous tungsten silicide layer 212D.
Fig. 3 E is illustrated in the image of the gate stack structure after the annealing process.In the first to the 3rd embodiment, identical Reference numeral represents identical element.Therefore, omitting it is described in detail.
Fig. 4 A illustrates the gate stack structure according to the 4th embodiment of the present invention.This gate stack structure comprises the first conductive layer 31, intermediate structure 32 and the second conductive layer 33.The first conductive layer 31 comprises for example boron or the N-type impurity polysilicon layer of phosphorus for example of highly doped P-type impurity.The first conductive layer 31 also can comprise polysilicon germanium layer (Si
1-xGe
x, wherein x is in about scope of 0.01 to 1.0) or silicide layer.For example, this silicide layer comprises the silicide that is selected from nickel (Ni), chromium (Cr), cobalt (Co), titanium (Ti), tungsten (W), tantalum (Ta), hafnium (Hf), zirconium (Zr) and platinum (Pt).
The second conductive layer 33 comprises tungsten layer.This tungsten layer thick about 100
To 2,000
, and by implementing PVD method, CVD method or the formation of ALD method.The PVD method comprises the sputtering method that uses the tungsten sputtering target.
Intermediate structure 32 comprises titanium layer 32A and nitrogenous tungsten silicide (WSi
xN
y) layer 32B.Specifically, the thickness of titanium layer 32A is about 10
To about 80
Scope in.The silicon that nitrogenous tungsten silicide layer 32B has about 0.5 to 3.0 scope is to the ratio of tungsten and have about nitrogen content of 10% to 60%.Nitrogenous tungsten silicide layer 32B represents the tungsten silicon-nitride layer or comprises the tungsten silicide layer of the nitrogen of certain content/weight ratio.The formed thickness of nitrogenous tungsten silicide layer 32B is about 20
To 200
Gate stack structure according to the 4th embodiment of the present invention comprises the first conductive layer 31, Ti/WSi
xN
yIntermediate structure 32 and the second conductive layer 33.The first conductive layer 31 comprises polysilicon, and the second conductive layer 33 comprises tungsten, therefore forms tungsten polysilicon gate stacked structure.
Particularly, Ti/WSi
xN
yIntermediate structure comprises metal level and nitrogen containing metal silicide layer.This metal level comprises the simple metal layer, and this metal silicide layer comprises nitrogenous tungsten silicide layer.For example, this metal level is that titanium layer 32A and this metal silicide layer are nitrogenous tungsten silicide layer 32B.
Multilayer intermediate structure according to the 4th embodiment also can form other structure.Except titanium layer, this metal level also comprises tantalum layer, and except nitrogenous tungsten silicide layer, this nitrogen containing metal silicide layer also comprises nitrogenous titanium silicide (TiSi
xN
y) layer or nitrogenous tantalum silicide (TaSi
xN
y) layer.Form tantalum layer by PVD method, CVD method or the ALD method that comprises sputtering method.Form nitrogenous titanium silicide layer by in nitrogen environment, utilizing the titanium silicide sputtering target to implement the reactive sputtering sedimentation.Form nitrogenous silication tantalum layer by in nitrogen environment, utilizing the tantalum silicide sputtering target to implement the reactive sputtering sedimentation.This tantalum layer thick about 10
To 80
The formed thickness of every one deck in nitrogenous titanium silicide layer and the nitrogenous silication tantalum layer is about 20
To 200
And every one deck has about nitrogen content of 10% to 60%.Silicon in this nitrogenous titanium silicide layer to the ratio of titanium in about scope of 0.5 to 3.0.This nitrogenous silication tantalum layer has about silicon of 0.5 to 3.0 to the ratio of tantalum.
Fig. 4 B illustrates the gate stack structure according to the 5th embodiment of the present invention.Described gate stack structure is to form from revising according to the gate stack structure of the second embodiment.In other words, use nitrogenous titanium (TiN
x) layer instead of titanium, wherein x is less than about 1.
This gate stack structure comprises the first conductive layer 301, intermediate structure 302 and the second conductive layer 303.This first conductive layer 301 comprises for example boron or the N-type impurity polysilicon layer of phosphorus for example of highly doped P-type impurity.The first conductive layer 301 also can comprise polysilicon germanium layer (Si
1-xGe
x, wherein x is in about scope of 0.01 to 1.0) or silicide layer.For example, this silicide layer comprises the silicide that is selected from nickel (Ni), chromium (Cr), cobalt (Co), titanium (Ti), tungsten (W), tantalum (Ta), hafnium (Hf), zirconium (Zr) and platinum (Pt).
The second conductive layer 303 comprises tungsten layer.Form about 100 by implementing PVD method, CVD method or ALD method
To 2,000
Thick tungsten layer.The PVD method comprises the sputtering method that uses the tungsten sputtering target.
Nitrogenous tungsten silicide layer 302B has the silicon of 0.5 to 3.0 scope to the ratio of tungsten and about 10% to about 60% nitrogen content.Nitrogenous tungsten silicide layer 302B represents the tungsten silicon-nitride layer or contains the tungsten silicide layer of the nitrogen of certain content/weight ratio.
Form nitrogenous titanium layer 302A and nitrogenous tungsten silicide layer 302B by the PVD method.The PVD method is carried out sputtering method or reactive sputtering sedimentation.For example, form nitrogenous titanium layer 302A by in nitrogen environment, utilizing the titanium target to implement the reactive sputtering sedimentation.Form nitrogenous tungsten silicide layer 302B by in nitrogen environment, utilizing the tungsten silicide sputtering target to implement the reactive sputtering sedimentation.
Irrelevant with bottom-layer-type because the PVD method allows evenly to form nitrogenous tungsten silicide layer 302B, so use PVD rule such as above-mentioned reactive sputtering sedimentation to form nitrogenous tungsten silicide layer 302B.
Gate stack structure according to the 5th embodiment comprises the first conductive layer 301, TiN
x/ WSi
xN
yIntermediate structure 302 and the second conductive layer 303.The first conductive layer 301 and the second conductive layer 303 comprise respectively polysilicon layer and tungsten layer.As a result, provide tungsten polysilicon gate stacked structure.
Particularly, this TiN
x/ WSi
xN
yIntermediate structure comprises metal level and nitrogen containing metal silicide layer.This metal level comprises the metal level of the nitrogen that contains certain content/weight ratio, and this metal silicide layer comprises the metal silicide layer of the nitrogen that contains certain content/weight ratio.For example, this metal level comprises nitrogenous titanium layer 302A, and this metal silicide layer comprises nitrogenous tungsten silicide layer 302B.
Multilayer intermediate structure according to the 5th embodiment can form other different structure.Except nitrogenous titanium layer, this nitrogen containing metal layer also comprises nitrogenous tantalum (TaN
x) layer.Except nitrogenous tungsten silicide (WSi
xN
y) layer outside, this nitrogen containing metal silicide layer also comprises nitrogenous titanium silicide (TiSi
xN
y) layer or nitrogenous tantalum silicide (TaSi
xN
y) layer.Form nitrogenous tantalum layer by PVD method, CVD method or the ALD method that comprises sputtering method.Form nitrogenous titanium silicide layer by in nitrogen environment, utilizing the titanium silicide sputtering target to implement the reactive sputtering sedimentation.Form nitrogenous silication tantalum layer by in nitrogen environment, utilizing the tantalum silicide sputtering target to implement the reactive sputtering sedimentation.Nitrogenous tantalum layer has about 10
To 80
The thickness of scope.The formed thickness of every one deck in nitrogenous titanium silicide layer and the nitrogenous silication tantalum layer is about 20
To 200
, and every one deck has about nitrogen content of 10% to 60%.Silicon in the nitrogenous titanium silicide layer to the ratio of titanium in about scope of 0.5 to 3.0.Nitrogenous silication tantalum layer has the silicon of about 0.5 to 3.0 scope to the ratio of tantalum.
Fig. 4 C illustrates the gate stack structure according to the 6th embodiment of the present invention.This gate stack structure comprises the first conductive layer 311, intermediate structure 312 and the second conductive layer 313.The first conductive layer 311 comprises for example boron (B) or the N-type impurity polysilicon layer of phosphorus (P) for example of highly doped P-type impurity.Except polysilicon layer, the first conductive layer 311 also can comprise polysilicon germanium layer (Si
1-xGe
x), wherein x perhaps can comprise silicide layer in about scope of 0.01 to 1.0.This silicide layer comprises the silicide that is selected from nickel (Ni), chromium (Cr), cobalt (Co), titanium (Ti), tungsten (W), tantalum (Ta), hafnium (Hf), zirconium (Zr) and platinum (Pt).
The second conductive layer 313 comprises tungsten layer.Form about 100 by one of them that implement PVD method, CVD method and ALD method
To 2,000
Thick tungsten layer.The PVD method comprises the sputtering method that uses the tungsten sputtering target.
Intermediate structure 312 comprises titanium silicide (TiSi
x) layer 312A, nitrogenous titanium (TiN
x) layer 312B and nitrogenous tungsten silicide (WSi
xN
y) layer 312C.Can be according to forming this intermediate structure at the described selection material of the 4th and the 5th embodiment with other different structure.
Gate stack structure according to the 6th embodiment is at the resulting structures to implementing according to the gate stack structure of the of the present invention the 4th and the 5th embodiment to provide after the annealing in process.This annealing is included in and forms the heat treatment of following during the various processes (for example, sept forms and interlayer insulating film forms) of implementing behind the gate stack structure.
In the situation that forms nitrogenous tungsten silicide layer 32B above the titanium layer 32A (Fig. 4 A), after annealing, in the borderline region between titanium layer 32A and nitrogenous tungsten silicide layer 32B, the trace nitrogen among the nitrogenous tungsten silicide layer 32B decomposes.As a result, shown in Fig. 4 C, the top of titanium layer 32A is transformed into nitrogenous titanium layer 312B, and the bottom of titanium layer 32A with from the reaction of the polysilicon of the first conductive layer 31, to form titanium silicide layer 312A.
The thickness of titanium silicide layer 312A is 1
To 30
Scope in, and the silicon among the titanium silicide layer 312A to the ratio of titanium in about scope of 0.5 to 3.0.Nitrogenous titanium layer 312B thick about 10
To 100
And has the nitrogen of about 0.7 to 1.3 scope to the ratio of titanium.
Nitrogenous tungsten silicide layer 312C has thickness and the composition roughly the same with nitrogenous tungsten silicide layer 32B.Specifically, nitrogenous tungsten silicide layer 312C has the silicon of about 0.5 to 3.0 scope to the ratio of tungsten and the nitrogen content of about 10% to 60% scope.The thickness of nitrogenous tungsten silicide layer 312C is about 20
To 200
Scope in.
With reference to figure 4C and 4B, compare intermediate structure 312 and intermediate structure 302.During annealing in process, from nitrogenous tungsten silicide layer 302B supply nitrogen to nitrogenous titanium layer 302A, nitrogenous titanium layer 302A is transformed into the nitrogenous titanium layer 312B that minimal reaction is arranged with titanium silicide layer 312A thus.The thickness of titanium silicide layer 312A is about 1
To 30
Scope in, and the thickness of nitrogenous titanium layer 312B is about 10
To 100
Scope in.Nitrogen among the nitrogenous titanium layer 312B to the ratio of titanium in about scope of 0.7 to 1.3.With the nitrogen among the nitrogenous titanium layer 302A titanium ratio (seeing Fig. 4 C) is compared, the nitrogen among the nitrogenous titanium layer 312B increases to about scope of 0.7 to 1.3 to the titanium ratio from about scope of 0.2 to 0.8.
Nitrogenous tungsten silicide layer 312C has thickness and the composition roughly the same with nitrogenous tungsten silicide layer 302B.Specifically, nitrogenous tungsten silicide layer 312C has the silicon of about 0.5 to 3.0 scope to the ratio of tungsten and the nitrogen content of about 10% to 60% scope.The thickness of nitrogenous tungsten silicide layer 312C is about 20
To 200
Scope in.
Gate stack structure according to the 6th embodiment comprises the first intermediate structure and the second intermediate structure.The first intermediate structure comprises metal silicide layer and nitrogen containing metal layer, and the second intermediate structure comprises the nitrogen containing metal silicide layer.For example, form the first intermediate structure by stacking this titanium silicide layer 312A and nitrogenous titanium layer 312B.The second intermediate structure comprises nitrogenous tungsten silicide layer 312C.
Fig. 5 A illustrates the gate stack structure according to the 7th embodiment of the present invention.This gate stack structure comprises the first conductive layer 41, intermediate structure 42 and the second conductive layer 43.The first conductive layer 41 comprises for example boron or the N-type impurity polysilicon layer of phosphorus for example of highly doped P-type impurity.The first conductive layer 41 also can comprise polysilicon germanium layer (Si
1-xGe
x, wherein x is in about scope of 0.01 to 1.0) or silicide layer.For example, silicide layer comprises the silicide that is selected from nickel (Ni), chromium (Cr), cobalt (Co), titanium (Ti), tungsten (W), tantalum (Ta), hafnium (Hf), zirconium (Zr) and platinum (Pt).
The second conductive layer 43 comprises tungsten layer.This tungsten layer thick about 100
To 2,000
And form by implementing PVD method, CVD method or ALD method.The PVD method comprises the sputtering method that uses the tungsten sputtering target.
Nitrogen among the nitrogenous tungsten layer 42C to the ratio of tungsten in about scope of 0.3 to 1.5.Nitrogenous tungsten layer 42C represents tungsten nitride layer or comprises the tungsten layer of the nitrogen of certain content/weight ratio.The thickness of nitrogenous tungsten layer 42C is about 20
To 200
Scope in.Although will be described below, nitrogenous tungsten layer 42C supply nitrogen is to nitrogenous tungsten silicide layer 42B.Therefore, after annealing, nitrogenous tungsten layer 42C becomes unazotized pure tungsten layer or contains the tungsten layer of trace nitrogen.
The PVD method is carried out sputtering method or reactive sputtering sedimentation.For example, form titanium layer 42A by utilizing the titanium sputtering target to implement sputtering method.Form nitrogenous tungsten layer 42C by in nitrogen environment, utilizing the tungsten sputtering target to implement the reactive sputtering sedimentation.Form nitrogenous tungsten silicide layer 42B by in nitrogen environment, utilizing the tungsten silicide sputtering target to implement the reactive sputtering sedimentation.Particularly, allow the evenly nitrogenous tungsten silicide layer 42B of formation and irrelevant with bottom-layer-type because in nitrogen environment, utilize the tungsten silicide sputtering target to implement above-mentioned reactive sputtering sedimentation, so use PVD rule such as reactive sputtering sedimentation to form nitrogenous tungsten silicide layer 42B.
Gate stack structure according to the 7th embodiment of the present invention comprises the first conductive layer 41, Ti/WSi
xN
y/ WN
xIntermediate structure 42 and the second conductive layer 43.The first conductive layer 41 comprises polysilicon, and the second conductive layer 43 comprises tungsten, therefore forms tungsten polysilicon gate stacked structure.
Particularly, Ti/WSi
xN
y/ WN
xIntermediate structure 42 comprises the first metal layer, nitrogen containing metal silicide layer and the second metal level.The first metal layer comprises the simple metal layer.The second metal level comprises the nitrogen containing metal layer.Metal silicide layer comprises the nitrogen containing metal silicide layer.For example, the first metal layer is titanium layer 42A.The second metal level is nitrogenous tungsten layer 42C.Metal silicide layer is nitrogenous tungsten silicide layer 42B.
Multilayer intermediate structure according to the 7th embodiment can also form other structure.Except titanium layer, the first metal layer also comprises tantalum layer.Except nitrogenous tungsten layer, the second metal level also comprises nitrogenous titanium tungsten (TiWN
x) layer.Except nitrogenous tungsten silicide layer, metal silicide layer also comprises nitrogenous titanium silicide (TiSi
xN
y) layer or nitrogenous tantalum silicide (TaSi
xN
y) layer.Form tantalum layer by PVD method, CVD method or the ALD method that comprises sputtering method.Form nitrogenous titanium tungsten layer by in nitrogen environment, utilizing titanium tungsten sputtering target to implement reactive sputtering.Form this nitrogen titanium silicide layer by in nitrogen environment, utilizing the titanium silicide sputtering target to implement the reactive sputtering sedimentation.Form nitrogenous silication tantalum layer by in nitrogen environment, utilizing the tantalum silicide sputtering target to implement the reactive sputtering sedimentation.This tantalum layer thick about 10
To 80
The formed thickness of every one deck in nitrogenous titanium tungsten layer and the nitrogenous silication tantalum layer is about 20
To 200
, and and every one deck have about nitrogen content of 10% to 60%.Nitrogenous titanium tungsten layer has the titanium of about 0.5 to 3.0 scope to the ratio of tungsten.Silicon in the nitrogenous titanium silicide layer to the ratio of titanium in about scope of 0.5 to 3.0.Nitrogenous silication tantalum layer has about silicon of 0.5 to 3.0 to the ratio of tantalum.
Fig. 5 B illustrates the gate stack structure according to the 8th embodiment of the present invention.This gate stack structure comprises the first conductive layer 401, intermediate structure 402 and the second conductive layer 403.The first conductive layer 401 comprises for example boron or the N-type impurity polysilicon layer of phosphorus for example of highly doped P-type impurity.The first conductive layer 401 also can comprise polysilicon germanium layer (Si
1-xGe
x, wherein x is in about scope of 0.01 to 1.0) or silicide layer.For example, this silicide layer comprises the silicide that is selected from nickel (Ni), chromium (Cr), cobalt (Co), titanium (Ti), tungsten (W), tantalum (Ta), hafnium (Hf), zirconium (Zr) and platinum (Pt).
The second conductive layer 403 comprises tungsten layer.This tungsten layer thick about 100
To 2,000
And form by implementing PVD method, CVD method or ALD method.The PVD method comprises the sputtering method that uses the tungsten sputtering target.
In about scope of 0.5 to 3.0, and the nitrogen content of nitrogenous tungsten silicide layer 402B is in about scope of 10% to 60% to the ratio of tungsten for silicon among the nitrogenous tungsten silicide layer 402B.Nitrogenous tungsten silicide layer 402B also comprises the tungsten silicon-nitride layer or contains the tungsten silicide layer of the nitrogen of certain content/weight ratio.
Form nitrogenous tungsten layer 402C by implementing PVD method, CVD method or ALD method.Form nitrogenous titanium layer 402A and nitrogenous tungsten silicide layer 402B by implementing the PVD method.
The PVD method is carried out sputtering method or reactive sputtering sedimentation.For example, form nitrogenous titanium layer 402A by in nitrogen environment, utilizing the titanium sputtering target to implement sputtering method.Form nitrogenous tungsten layer 402C by in nitrogen environment, utilizing the tungsten sputtering target to implement the reaction equation sputtering method.Form nitrogenous tungsten silicide layer 402B by in nitrogen environment, utilizing the tungsten silicide sputtering target to implement the reactive sputtering sedimentation.Especially, irrelevant with bottom-layer-type because being formed uniformly nitrogenous tungsten silicide layer 402B, so use PVD rule such as reactive sputtering sedimentation to form nitrogenous tungsten silicide layer 402B.
Gate stack structure according to the 8th embodiment of the present invention comprises the first conductive layer 401, TiN
x/ WSi
xN
y/ WN
xIntermediate structure 402 and the second conductive layer 403.The first conductive layer 401 comprises polysilicon, and the second conductive layer 403 comprises tungsten, therefore forms tungsten polysilicon gate stacked structure.
Particularly, TiN
x/ WSi
xN
y/ WN
xIntermediate structure 402 forms the stacked structure that comprises the first metal layer, nitrogen containing metal silicide layer and the second metal level.The first and second metal levels are nitrogen containing metal layers, and metal silicide layer is the nitrogen containing metal silicide layer.For example, the first metal layer is nitrogenous titanium layer 402A.The second metal level is nitrogenous tungsten layer 402C.Metal silicide layer is nitrogenous tungsten silicide layer 402B.
Above-mentioned multilayer intermediate structure can form other different structure.For example, except nitrogenous titanium layer, the first nitrogen containing metal layer also comprises nitrogenous tantalum layer.Except nitrogenous tungsten layer, the second nitrogen containing metal layer also comprises nitrogenous titanium tungsten layer.Except nitrogenous tungsten silicide layer, the nitrogen containing metal silicide layer also comprises nitrogenous titanium silicide layer or nitrogenous silication tantalum layer.By implementing to comprise that PVD method, CVD method or the ALD method of sputter form nitrogenous tantalum layer.Form nitrogenous titanium tungsten layer by in nitrogen environment, utilizing titanium tungsten sputtering target to implement the reactive sputtering sedimentation.Form nitrogenous titanium silicide layer and nitrogenous silication tantalum layer by in nitrogen environment, utilizing corresponding titanium silicide and tantalum silicide sputtering target to implement the reactive sputtering sedimentation.The formed thickness of nitrogenous tantalum layer is about 10
To 80
The formed thickness of every one deck in nitrogenous titanium tungsten layer, nitrogenous titanium silicide layer and the nitrogenous silication tantalum layer is 20
To 200
, and every one deck has the nitrogen content of about 10% to 60% scope.In nitrogenous titanium tungsten layer, titanium to the ratio of tungsten in about scope of 0.5 to 3.0.In nitrogenous titanium silicide layer, silicon to the ratio of titanium in about scope of 0.5 to 3.0.In nitrogenous silication tantalum layer, silicon to the ratio of tantalum in about scope of 0.5 to 3.0.
Fig. 5 C illustrates the gate stack structure according to the 9th embodiment of the present invention.This gate stack structure comprises the first conductive layer 411, intermediate structure 412 and the second conductive layer 413.The first conductive layer 411 comprises for example boron (B) or the N-type impurity polysilicon layer of phosphorus (P) for example of highly doped P-type impurity.Except polysilicon layer, the first conductive layer 411 also can comprise polycrystalline silicon germanium (Si
1-xGe
x) layer, wherein x perhaps comprises silicide layer in about scope of 0.01 to 1.0.This silicide layer comprises the silicide that is selected from nickel (Ni), chromium (Cr), cobalt (Co), titanium (Ti), tungsten (W), tantalum (Ta), hafnium (Hf), zirconium (Zr) and platinum (Pt).
The second conductive layer 413 comprises tungsten layer.One of them of enforcement PVD method, CVD method and ALD method is to form about 100
To 2,000
Thick tungsten layer.The PVD method comprises the sputtering method that uses the tungsten sputtering target.
Gate stack structure according to the 9th embodiment is at the resulting structures to implementing according to the gate stack structure of the of the present invention the 7th and the 8th embodiment to provide after the annealing in process.This annealing is included in and forms the heat treatment of following during the various processes (for example, sept forms and interlayer insulating film forms) of implementing behind the gate stack structure.
With reference to figure 5C and 5A, compare intermediate structure 412 and intermediate structure 42.When titanium layer 42A with from the reaction of the polysilicon of the first conductive layer 41 time, form and have about 1
To 30
The titanium silicide layer 412A of thickness.Silicon among the titanium silicide layer 212A to the ratio of titanium in about scope of 0.5 to 3.0.
When supplying nitrogen to titanium layer 42A from nitrogenous tungsten layer 42B, obtain nitrogenous titanium layer 412B.Nitrogenous titanium layer 412B has about 10
To 100
The thickness of scope and have the nitrogen of about 0.7 to 1.3 scope to the ratio of titanium.With the nitrogen among the titanium layer 42A ratio of titanium is compared, the nitrogen among the nitrogenous titanium layer 412B increases to about 0.7 to 1.3 to the ratio of titanium from about 0.
Nitrogenous tungsten silicide layer 412C has thickness and the composition roughly the same with nitrogenous tungsten silicide layer 42C.Specifically, nitrogenous tungsten silicide layer 412C has the silicon of about 0.5 to 3.0 scope to the ratio of tungsten and the nitrogen content of about 10% to 60% scope.The thickness of nitrogenous tungsten silicide layer 412C is about 20
With 200
Scope in.
After annealing, nitrogenous tungsten layer 412D has because degrading and is down to about 10% or still less nitrogen content.Reference numeral WN
x(D) the nitrogenous tungsten layer of expression through degrading.Nitrogenous tungsten layer 412D thick about 20
To 200
Nitrogen among the nitrogenous tungsten layer 412D to the ratio of tungsten in about scope of 0.01 to 0.15.With the nitrogen among the described nitrogenous tungsten layer 42C of Fig. 5 A the ratio of tungsten is compared, the nitrogen among the nitrogenous tungsten layer 412D is reduced to about scope of 0.01 to 0.15 to the ratio of tungsten from about scope of 0.3 to 1.5.
In the situation that forms nitrogenous tungsten silicide layer 42B above the titanium layer 42A (seeing Fig. 5 A), after annealing, in the borderline region between titanium layer 42A and nitrogenous tungsten silicide 42B, the trace nitrogen among the nitrogenous tungsten silicide layer 42B decomposes.As a result, shown in Fig. 5 C, the top of titanium layer 42A is transformed into nitrogenous titanium layer 412B, and the bottom of titanium layer 42A with from the reaction of the polysilicon of the first conductive layer 41, to form titanium silicide layer 412A.
With reference to figure 5C and 5B, compare intermediate structure 412 and intermediate structure 402.Nitrogenous titanium layer 402A is transformed into the nitrogenous titanium layer 412B that minimal reaction is arranged with titanium silicide layer 412A.The thickness of titanium silicide layer 412A is about 1
To 30
Scope in, and the thickness of nitrogenous titanium layer 412B is about 10
To 100
Scope in.Nitrogen among the nitrogenous titanium layer 412B to the ratio of titanium in about scope of 0.7 to 1.3.Nitrogenous tungsten silicide layer 412C has thickness and the composition roughly the same with nitrogenous tungsten silicide layer 402B.More specifically, the silicon among the nitrogenous tungsten silicide layer 412C to the ratio of tungsten in about scope of 0.5 to 3.0.Nitrogenous tungsten silicide layer 412C has the nitrogen content of about 10% to 60% scope and forms about 20
To 200
Thickness.
After annealing, nitrogenous tungsten layer 412D has because degrading and is down to about 10% or still less nitrogen content.Nitrogenous tungsten layer 412D is about 20
To 200
Thick.Nitrogen among the nitrogenous tungsten layer 412D to the ratio of tungsten in about scope of 0.01 to 0.15.
Gate stack structure according to the 9th embodiment comprises the first intermediate structure and the second intermediate structure.The first intermediate structure comprises the first metal silicide layer and the first nitrogen containing metal layer, and the second intermediate structure comprises the second nitrogen containing metal layer and nitrogen containing metal silicide layer.For example, form the first intermediate structure by stacking titanium silicide layer 412A and nitrogenous titanium layer 412B.Form the second intermediate structure by stacking nitrogenous tungsten silicide layer 412C and nitrogenous tungsten layer 412C.
Fig. 6 A illustrates the gate stack structure according to the tenth embodiment of the present invention.This gate stack structure comprises the first conductive layer 51, intermediate structure 52 and the second conductive layer 53.The first conductive layer 51 comprises for example boron or the N-type impurity polysilicon layer of phosphorus for example of highly doped P-type impurity.The first conductive layer 51 also can comprise polysilicon germanium layer (Si
1-xGe
x, wherein x is in about 0.01 and 1.0 scope) or silicide layer.For example, this silicide layer comprises the silicide that is selected from nickel (Ni), chromium (Cr), cobalt (Co), titanium (Ti), tungsten (W), tantalum (Ta), hafnium (Hf), zirconium (Zr) and platinum (Pt).
The second conductive layer 53 comprises tungsten layer.This tungsten layer thick about 100
To 2,000
And form by implementing PVD method, CVD method or ALD method.The PVD method comprises the sputtering method that uses the tungsten sputtering target.
Silicon among the nitrogenous tungsten silicide layer 52C to the ratio of tungsten in about scope of 0.5 to 3.0, and the nitrogen content of nitrogenous tungsten silicide layer 52C about 10% to about 60% scope.Nitrogenous tungsten silicide layer 52C represents the tungsten silicon-nitride layer or contains the tungsten silicide layer of the nitrogen of certain content/weight ratio.The formed thickness of nitrogenous tungsten silicide layer 52C is about 20
To about 200
Scope in.
Gate stack structure according to the tenth embodiment comprises the first conductive layer 51, Ti/WN
x/ WSi
xN
y/ WN
xIntermediate structure 52 and the second conductive layer 53.The first conductive layer 51 and the second conductive layer 53 comprise respectively polysilicon layer and tungsten layer, therefore form tungsten polysilicon gate stacked structure.
Particularly, Ti/WN
x/ WSi
xN
y/ WN
xIntermediate structure 52 comprises the first metal layer, the second metal level, nitrogen containing metal silicide layer and the 3rd metal level.The first metal layer comprises the simple metal layer, yet the second and the 3rd metal level comprises the nitrogen containing metal layer.The nitrogen containing metal silicide layer comprises the metal silicide layer of the nitrogen that contains certain content/weight ratio.For example, the first metal layer is titanium layer 52A, and the second and the 3rd metal level is respectively the first and second nitrogenous tungsten layer 52B and 52D.Metal silicide layer is nitrogenous tungsten silicide layer 52C.
Above-mentioned multilayer intermediate structure also can form other different structure.For example, except titanium layer, the first metal layer also comprises tantalum layer.Except nitrogenous tungsten layer, the second and the 3rd metal level also comprises roughly the same material, for example nitrogenous titanium tungsten layer.Except nitrogenous tungsten silicide layer, the nitrogen containing metal silicide layer also comprises nitrogenous titanium silicide layer or nitrogenous silication tantalum layer.Form tantalum layer by PVD method, CVD method or the ALD method of implementing to comprise sputter.Form nitrogenous titanium tungsten layer by in nitrogen environment, utilizing titanium tungsten sputtering target to implement the reactive sputtering sedimentation.Form nitrogenous titanium silicide layer and nitrogenous silication tantalum layer by in nitrogen environment, utilizing corresponding titanium silicide and tantalum silicide sputtering target to implement the reactive sputtering sedimentation.The formed thickness of tantalum layer is about 10
To 80
The formed thickness of every one deck of nitrogenous titanium tungsten layer, nitrogenous titanium silicide layer and nitrogenous silication tantalum layer is about 20
To 200
, and every one deck has the nitrogen content of about 10% to 60% scope.In nitrogenous titanium tungsten layer, titanium to the ratio of tungsten in about scope of 0.5 to 3.0.In nitrogenous titanium silicide layer, silicon to the ratio of titanium in about scope of 0.5 to 3.0.In nitrogenous silication tantalum layer, silicon to the ratio of tantalum in about scope of 0.5 to 3.0.
Fig. 6 B illustrates the gate stack structure according to the 11 embodiment of the present invention.This gate stack structure comprises the first conductive layer 501, intermediate structure 502 and the second conductive layer 503.The first conductive layer 501 comprises for example boron or the N-type impurity polysilicon layer of phosphorus for example of highly doped P-type impurity.The first conductive layer 501 also can comprise polysilicon germanium layer (Si
1-xGe
x, wherein x is in about scope of 0.01 to 1.0) or silicide layer.For example, this silicide layer comprises the silicide that is selected from nickel (Ni), chromium (Cr), cobalt (Co), titanium (Ti), tungsten (W), tantalum (Ta), hafnium (Hf), zirconium (Zr) and platinum (Pt).
The second conductive layer 503 comprises tungsten layer.This tungsten layer thick about 100
To 2,000
And form by implementing PVD method, CVD method or ALD method.The PVD method comprises the sputtering method that uses the tungsten sputtering target.
Every one deck of the first and second nitrogenous tungsten layer 502B and 502D has certain nitrogen to the tungsten ratio, for example in about scope of 0.3 to 1.5.Every one deck of the first and second nitrogenous tungsten layer 502B and 502D also comprises tungsten nitride layer.Although will be described below, the first and second nitrogenous tungsten layer 502B and 502D supply nitrogen are to nitrogenous titanium layer 502A and nitrogenous tungsten silicide layer 502C.Every one deck of the first and second nitrogenous tungsten layer 502B and 502D forms about 20
To 200
Thickness.Because supply nitrogen, the first and second nitrogenous tungsten layer 502B and 502D become pure tungsten layer or contain the tungsten layer of trace nitrogen after annealing.
Silicon among the nitrogenous tungsten silicide layer 502C to the ratio of tungsten in about scope of 0.5 to 3.0, and the nitrogen content of nitrogenous tungsten silicide layer 502C about 10% to about 60% scope.Nitrogenous tungsten silicide layer 502C also comprises the tungsten silicon-nitride layer.Nitrogenous tungsten silicide layer 502C has about 20
To 200
Thickness.
Form the first and second nitrogenous tungsten layer 502B and 502D by implementing PVD method, CVD method or ALD method.Form nitrogenous titanium layer 502A and nitrogenous tungsten silicide layer 502C by implementing the PVD method.
The PVD method is carried out sputtering method or reactive sputtering sedimentation.For example, form nitrogenous titanium layer 502A by in nitrogen environment, utilizing the titanium sputtering target to implement sputtering method.Form the first and second nitrogenous tungsten layer 502B and 502D by in nitrogen environment, utilizing the tungsten sputtering target to implement the reactive sputtering sedimentation.Form nitrogenous tungsten silicide layer 502C by in nitrogen environment, utilizing the tungsten silicide sputtering target to implement the reactive sputtering sedimentation.Especially, irrelevant with bottom-layer-type because being formed uniformly nitrogenous tungsten silicide layer 502C, so use PVD rule such as reactive sputtering sedimentation to form nitrogenous tungsten silicide layer 502C.
Gate stack structure according to the 11 embodiment of the present invention comprises the first conductive layer 501, TiN
x/ WN
x/ WSi
xN
y/ WN
xIntermediate structure 502 and the second conductive layer 503.The first conductive layer 501 comprises polysilicon, and the second conductive layer 503 comprises tungsten, forms thus tungsten polysilicon gate stacked structure.
Particularly, TiN
x/ WN
x/ WSi
xN
y/ WN
xIntermediate structure 502 forms the stacked structure that comprises the first metal layer, the second metal level, nitrogen containing metal silicide layer and the 3rd metal level.First, second, and third metal level is the nitrogen containing metal layer, and the nitrogen containing metal silicide layer comprises the nitrogen of certain content/weight ratio.For example, the first metal layer is nitrogenous titanium layer 502A, and the second and the 3rd metal level is respectively the first and second nitrogenous tungsten layer 502B and 502D.Metal silicide layer is nitrogenous tungsten silicide layer 502C.
Above-mentioned multilayer intermediate structure can also form other different structure.For example, except nitrogenous titanium layer, the first metal layer also comprises nitrogenous tantalum (TaN
x) layer.Except nitrogenous tungsten layer, the second and the 3rd metal level also comprises roughly the same material, for example nitrogenous titanium tungsten (TiWN
x) layer.Except nitrogenous tungsten silicide layer, the nitrogen containing metal silicide layer also comprises nitrogenous titanium silicide (TiSi
xN
y) layer or nitrogenous tantalum silicide (TaSi
xN
y) layer.By implementing to comprise that PVD method, CVD method or the ALD method of sputter form nitrogenous tantalum layer.Form nitrogenous titanium tungsten layer by in nitrogen environment, utilizing titanium tungsten sputtering target to implement the reactive sputtering sedimentation.Form nitrogenous titanium silicide layer and nitrogenous silication tantalum layer by in nitrogen environment, utilizing corresponding titanium silicide and tantalum silicide sputtering target to implement the reactive sputtering sedimentation.Nitrogenous tantalum layer forms about 10
To 80
Thickness.Every one deck of nitrogenous titanium tungsten layer, nitrogenous titanium silicide layer and nitrogenous silication tantalum layer forms about 20
To 200
Thickness, and every one deck has the nitrogen content of about 10% to 60% scope.In nitrogenous titanium tungsten layer, titanium to the ratio of tungsten in about scope of 0.5 to 3.0.In nitrogenous titanium silicide layer, silicon to the ratio of titanium in about scope of 0.5 to 3.0.In nitrogenous silication tantalum layer, silicon to the ratio of tantalum in about scope of 0.5 to 3.0.
Fig. 6 C illustrates the gate stack structure according to the 12 embodiment of the present invention.This gate stack structure comprises the first conductive layer 511, intermediate structure 512 and the second conductive layer 513.The first conductive layer 511 comprises for example boron (B) or the N-type impurity polysilicon layer of phosphorus (P) for example of highly doped P-type impurity.Except polysilicon layer, the first conductive layer 511 also can comprise polycrystalline silicon germanium (Si
1-xGe
x) layer, wherein x perhaps comprises silicide layer in about scope of 0.01 to 1.0.This silicide layer comprises the silicide that is selected from nickel (Ni), chromium (Cr), cobalt (Co), titanium (Ti), tungsten (W), tantalum (Ta), hafnium (Hf), zirconium (Zr) and platinum (Pt).
The second conductive layer 513 comprises tungsten layer.One of them of enforcement PVD method, CVD method and ALD method is to form about 100
To 2,000
Thick tungsten layer.The PVD method comprises the sputtering method that uses the tungsten sputtering target.
Gate stack structure according to the 12 embodiment is at the resulting structures to implementing according to the gate stack structure of the of the present invention the tenth and the 11 embodiment to provide after the annealing in process.This annealing is included in and forms the heat treatment of following during the various processes (for example, sept forms and interlayer insulating film forms) of implementing behind the gate stack structure.
With reference to figure 6C and 6A, compare intermediate structure 512 and intermediate structure 52.When titanium layer 52A with from the reaction of the polysilicon of the first conductive layer 51 time, form and have about 1
To 30
The titanium silicide layer 512A of thickness.Silicon among the titanium silicide layer 512A to the ratio of titanium in about scope of 0.5 to 3.0.
When supplying nitrogen to titanium layer 52A from the first nitrogenous tungsten layer 52B, obtain nitrogenous titanium layer 512B.Nitrogenous titanium layer 512B has about 10
To 100
The thickness of scope and have the nitrogen of about 0.7 to 1.3 scope to the ratio of titanium.
After annealing, every one deck of the first and second nitrogenous tungsten layer 512C and 512E has because degrading is down to about 10% or still less nitrogen content.Reference numeral WN
x(D) the nitrogenous tungsten layer of expression through degrading.Every one deck of the first and second nitrogenous tungsten layer 512C and 512E is about 20
To 200
Thick.Nitrogen in every one deck of the first and second nitrogenous tungsten layer 512C and 512E to the ratio of tungsten in about scope of 0.01 to 0.15.
Nitrogenous tungsten silicide layer 512D has thickness and the composition roughly the same with nitrogenous tungsten silicide layer 52C.Specifically, nitrogenous tungsten silicide layer 512D has the silicon of about 0.5 to 3.0 scope to ratio and about nitrogen content of 10% to 60% of tungsten.The thickness of nitrogenous tungsten silicide layer 512D is about 20
To 200
Scope in.
With reference to figure 6C and 6B, compare intermediate structure 512 and intermediate structure 502.During annealing in process, from nitrogenous tungsten layer 502B supply nitrogen to nitrogenous titanium layer 502A.As a result, nitrogenous titanium layer 502A is transformed into the nitrogenous titanium layer 512B that minimal reaction is arranged with titanium silicide layer 512A.The thickness of titanium silicide layer 512A is about 1
To 30
Scope in, and the thickness of nitrogenous titanium layer 512B is about 10
To 100
Scope in.Nitrogen among the nitrogenous titanium layer 512B to the ratio of titanium in about scope of 0.7 to 1.3.
After annealing, when degrading the first and second nitrogenous tungsten layer 502B and 502D, every one deck of the first and second nitrogenous tungsten layer 512C and 512E has is down to about 10% or nitrogen content still less.Every one deck of the first and second nitrogenous tungsten layer 512C and 512E is about 20
To 200
Thick.Nitrogen in every one deck of the first and second nitrogenous tungsten layer 512C and 512E to the ratio of tungsten in about scope of 0.01 to 0.15.
Nitrogenous tungsten silicide layer 512D has thickness and the composition roughly the same with nitrogenous tungsten silicide layer 502C.Specifically, nitrogenous tungsten silicide layer 512D has the silicon of about 0.5 to 3.0 scope to ratio and about nitrogen content of 10% to 60% of tungsten.The thickness of nitrogenous tungsten silicide layer 512D is about 20
To 200
Scope in.
Gate stack structure according to the 12 embodiment comprises the first intermediate structure and the second intermediate structure.The first intermediate structure comprises metal silicide layer and the first nitrogen containing metal layer, and the second intermediate structure comprises the second nitrogen containing metal layer, nitrogen containing metal silicide layer and the 3rd nitrogen containing metal layer.For example, form the first intermediate structure by stacking titanium silicide layer 512A and nitrogenous titanium layer 512B.Form the second intermediate structure by stacking nitrogenous tungsten layer 512C, nitrogenous tungsten silicide layer 512D and nitrogenous tungsten layer 512E.
Comprise nitrogen containing metal silicide layer for example nitrogenous tungsten silicide layer and a plurality of thin layers of comprising titanium, silicon, tungsten and nitrogen according to each intermediate structure of the first to the 12 embodiment of the present invention.Form nitrogenous tungsten silicide layer by in nitrogen environment, utilizing the tungsten silicide sputtering target to implement the reactive sputtering sedimentation.When the nitrogenous tungsten silicide layer of deposition, the enforcement of reactive sputtering sedimentation makes titanium layer be transformed into titanium nitride layer.Forming in the situation of nitrogenous tungsten layer above the titanium layer, titanium layer is transformed into titanium nitride layer.
Because nitrogenous tungsten silicide layer is as amorphous diffusion barrier, therefore when forming tungsten layer, this tungsten layer has the little of resistance and large crystallite dimension of about 15 μ Ω-cm.Therefore, because can form the tungsten layer with low resistivity, so this tungsten layer has low sheet resistor.
Because when forming nitrogenous tungsten layer or nitrogenous tungsten silicide layer, titanium layer or nitrogenous titanium layer are transformed into titanium nitride layer, so have low contact resistance and reduce exhausting of polysilicon according to the gate stack structure of the first to the 12 embodiment of the present invention.And because comprise nitrogenous tungsten silicide layer in each intermediate structure, gate stack structure has low sheet resistor.
Because above-mentioned titanium layer or nitrogenous titanium layer are transformed into titanium nitride layer, therefore every one deck of included multilayer all comprises nitrogen in intermediate structure.As a result, contact resistance and sheet resistor are lower, and can reduce the height of each gate stack structure.In addition, can reduce because of the impurity that in the first conductive layer, the mixes poly-Si depletion effect that causes to outdiffusion of boron for example.
Fig. 7 A illustrates the gate stack structure according to the 13 embodiment of the present invention.This gate stack structure comprises the first conductive layer 61, intermediate structure 62 and the second conductive layer 63.The first conductive layer 61 comprises for example boron or the N-type impurity polysilicon layer of phosphorus for example of highly doped P-type impurity.The first conductive layer 61 also can comprise polysilicon germanium layer (Si
1-xGe
x, wherein x is in about scope of 0.01 to 1.0) or silicide layer.For example, this silicide layer comprises the silicide that is selected from nickel (Ni), chromium (Cr), cobalt (Co), titanium (Ti), tungsten (W), tantalum (Ta), hafnium (Hf), zirconium (Zr) and platinum (Pt).
The second conductive layer 63 comprises tungsten layer.This tungsten layer thick about 100
To 2,000
And form by implementing PVD method, CVD method or ALD method.The PVD method comprises the sputtering method that uses the tungsten sputtering target.
Every one deck of the first and second nitrogenous tungsten layer 62B and 62D has certain nitrogen to the tungsten ratio, for example in about scope of 0.3 to 1.5.Every one deck of the first and second nitrogenous tungsten layer 62B and 62D also comprises tungsten nitride layer.Although after being described in, the first and second nitrogenous tungsten layer 62B and 62D have metallic character.The first and second nitrogenous tungsten layer 62B and 62D supply nitrogen are to nitrogenous tungsten silicide layer 62C.Every one deck of the first and second nitrogenous tungsten layer 62B and 62D forms about 20
To 200
Thickness.Because supply nitrogen, the first and second nitrogenous tungsten layer 62B and 62D become pure tungsten layer or contain the tungsten layer of trace nitrogen after annealing.
Silicon among the nitrogenous tungsten silicide layer 62C to the ratio of tungsten in about scope of 0.5 to 3.0.Nitrogenous tungsten silicide layer 62C forms about 20
To 100
Thickness.
The PVD method is carried out sputtering method or reactive sputtering sedimentation.For example, form titanium layer 62A by utilizing the titanium sputtering target to implement sputtering method.Implement every one deck that the reactive sputtering sedimentation forms the first and second nitrogenous tungsten layer 62B and 62D by in nitrogen environment, utilizing the tungsten sputtering target.Form nitrogenous tungsten silicide layer 62C by utilizing the tungsten silicide sputtering target to implement the reactive sputtering sedimentation.Form tungsten layer 63 by utilizing the tungsten sputtering target to implement sputtering method.
Gate stack structure according to the 13 embodiment of the present invention comprises the first conductive layer 61, Ti/WN
x/ WSi
x/ WN
xIntermediate structure 62 and the second conductive layer 63.The first conductive layer 61 comprises polysilicon, and the second conductive layer 63 comprises tungsten, forms thus tungsten polysilicon gate stacked structure.
Particularly, Ti/WN
x/ WSi
x/ WN
xIntermediate structure 62 forms the stacked structure that comprises the first metal layer, the second metal level, nitrogen containing metal silicide layer and the 3rd metal level.The first metal layer comprises the simple metal layer.The second and the 3rd metal level comprises the nitrogen containing metal layer, and the nitrogen containing metal silicide layer comprises the pure silicon tungsten layer.For example, the first metal layer is titanium layer 62A, and the second and the 3rd metal level is respectively the first and second nitrogenous tungsten layer 62B and 62D.The nitrogen containing metal silicide layer is nitrogenous tungsten silicide layer 62C.
Above-mentioned multilayer intermediate structure also can form other different structure.For example, except titanium layer, the first metal layer also comprises tantalum layer.Except the silication tungsten layer, metal silicide layer also comprises titanium silicide (TiSi
x) layer, wherein x or comprises tantalum silicide (TaSi in 1.5 to 10 scope
x) layer, wherein x is in 1.5 to 10 scope.Except nitrogenous tungsten layer, the second and the 3rd metal level also comprises nitrogenous titanium tungsten (TiWN
x) layer.Form tantalum layer by PVD method, CVD method or the ALD method of implementing to comprise sputter.Form nitrogenous titanium tungsten layer by in nitrogen environment, utilizing titanium tungsten sputtering target to implement the reactive sputtering sedimentation.Form titanium silicide layer and silication tantalum layer by utilizing corresponding titanium silicide and tantalum silicide sputtering target to implement the reactive sputtering sedimentation.Tantalum layer forms about 10
To 80
Thickness.Nitrogenous titanium tungsten layer is about 20
To 200
Thick.Every one deck of titanium silicide layer and silication tantalum layer forms about 20
To 200
Thickness.Nitrogenous titanium tungsten layer has the nitrogen content of about 10% to 60% scope.In nitrogenous titanium tungsten layer, titanium to the ratio of tungsten in about scope of 0.5 to 3.0.In titanium silicide layer, silicon to the ratio of titanium in about scope of 0.5 to 3.0.In the silication tantalum layer, silicon to the ratio of tantalum in about scope of 0.5 to 3.0.
Above the first nitrogenous tungsten layer 62B, form tungsten silicide layer 62C by implementing PVD rule such as sputtering method.Utilize the tungsten silicide sputtering target to implement sputtering method and allow evenly formation tungsten silicide layer 62C and irrelevant with bottom-layer-type.
Fig. 7 B is illustrated in by implementing corresponding chemical vapour deposition (CVD) (CVD) and physical vapour deposition (PVD) (PVD) method at the image that the structure that provides behind the tungsten silicide layer is provided above the nitrogenous tungsten layer.Although above tungsten nitride layer WN, do not form well tungsten silicide layer CVD-WSi by the CVD method
x, but can above tungsten nitride layer WN, be formed uniformly tungsten silicide layer PVD-WSi by the PVD method
xTherefore, because can above tungsten silicide layer, form the tungsten layer with low resistivity, so can reduce the sheet resistor of tungsten layer.
For the gate stack structure according to the 13 embodiment of the present invention, when forming nitrogenous tungsten layer 62B above titanium layer, this titanium layer is transformed into titanium nitride layer.
According to the 13 embodiment of the present invention, because during the formation of nitrogenous layer, the titanium layer of intermediate structure is transformed into titanium nitride layer, so gate stack structure can obtain low contact resistance and reduce poly-Si depletion effect.In addition, because intermediate structure comprises tungsten silicide layer, so gate stack structure also can obtain low sheet resistor.
Fig. 7 C illustrates the gate stack structure according to the 14 embodiment of the present invention.This gate stack structure comprises the first conductive layer 601, intermediate structure 602 and the second conductive layer 603.The first conductive layer 601 comprises for example boron or the N-type impurity polysilicon layer of phosphorus for example of highly doped P-type impurity.The first conductive layer 601 also can comprise polysilicon germanium layer (Si
1-xGe
x, wherein x is in about scope of 0.01 to 1.0) or silicide layer.For example, this silicide layer comprises the silicide that is selected from nickel (Ni), chromium (Cr), cobalt (Co), titanium (Ti), tungsten (W), tantalum (Ta), hafnium (Hf), zirconium (Zr) and platinum (Pt).
The second conductive layer 603 comprises tungsten layer.This tungsten layer thick about 100
To 2,000
And form by implementing PVD method, CVD method or ALD method.The PVD method comprises the sputtering method that uses the tungsten sputtering target.
Every one deck of the first and second nitrogenous tungsten layer 602B and 602D has certain nitrogen to the tungsten ratio, for example in about scope of 0.3 to 1.5.Every one deck of the first and second nitrogenous tungsten layer 602B and 602D also comprises tungsten nitride layer.The first and second nitrogenous tungsten layer 602B and 602D supply nitrogen are to tungsten silicide layer 602C.Every one deck of the first and second nitrogenous tungsten layer 602B and 602D forms about 20
To 200
Thickness.Because supply nitrogen, the first and second nitrogenous tungsten layer 602B and 602D become pure tungsten layer or contain the tungsten layer of trace nitrogen after annealing.
Silicon among the tungsten silicide layer 602C to the tungsten ratio in about scope of 0.5 to 3.0.The thickness of tungsten silicide layer 602C is about 20
To 200
Form the first and second nitrogenous tungsten layer 602B and 602D by implementing PVD method, CVD method or ALD method.Form nitrogenous titanium layer 602A and tungsten silicide layer 602C by implementing the PVD method.
The PVD method is carried out sputtering method or reactive sputtering sedimentation.For example, form nitrogenous titanium layer 602A by in nitrogen environment, utilizing the titanium sputtering target to implement sputtering method.Come each self-forming first and second nitrogenous tungsten layer 602B and 602D by in nitrogen environment, utilizing the tungsten sputtering target to implement the reactive sputtering sedimentation.Form tungsten silicide layer 602C by utilizing the tungsten silicide sputtering target to implement the reactive sputtering sedimentation.Form tungsten layer 603 by utilizing the tungsten sputtering target to implement sputtering method.Gate stack structure according to the 14 embodiment of the present invention comprises the first conductive layer 601, TiN
x/ WN
x/ WSi
x/ WN
xIntermediate structure 602 and the second conductive layer 603.The first conductive layer 601 comprises polysilicon, and the second conductive layer 603 comprises tungsten, therefore forms tungsten polysilicon gate stacked structure.
Particularly, TiN
x/ WN
x/ WSi
x/ WN
xIntermediate structure 602 forms the stacked structure that comprises the first metal layer, the second metal level, metal silicide layer and the 3rd metal level.First, second, and third metal level is the nitrogen containing metal layer, and metal silicide layer is the simple metal silicide layer.For example, the first metal layer is nitrogenous titanium layer 602A, and the second and the 3rd metal level is respectively the first and second nitrogenous tungsten layer 602B and 602D.Metal silicide layer is tungsten silicide layer 602C.
Above-mentioned multilayer intermediate structure also can form other different structure.For example, except nitrogenous titanium layer, the first metal layer also comprises nitrogenous tantalum (TaN
x) layer.Except the silication tungsten layer, metal silicide layer also comprises titanium silicide (TiSi
x), wherein x or comprises tantalum silicide (TaSi in about scope of 1.5 to 10
x), wherein x is in about 1.5 and 10 scope.Except nitrogenous tungsten layer, the second and the 3rd metal level also comprises nitrogenous titanium tungsten (TiWN
x) layer.Form nitrogenous tantalum layer by in nitrogen environment, utilizing tantalum spattering target to implement the reactive sputtering method.Form nitrogenous titanium tungsten layer by in nitrogen environment, utilizing titanium tungsten sputtering target to implement the reactive sputtering sedimentation.Form titanium silicide layer and silication tantalum layer by utilizing corresponding titanium silicide and tantalum silicide sputtering target to implement the reactive sputtering sedimentation.Nitrogenous tantalum layer forms about 10
To 150
Thickness.Every one deck of nitrogenous titanium tungsten layer, titanium silicide layer and silication tantalum layer forms about 20
To 200
Thickness.Nitrogen content in the nitrogenous titanium tungsten layer is in about scope of 10% to 60%.In nitrogenous titanium tungsten layer, titanium to the ratio of tungsten in about scope of 0.5 to 3.0.In titanium silicide layer, silicon to the ratio of titanium in about scope of 0.5 to 3.0.In the silication tantalum layer, silicon to the ratio of tantalum in about scope of 0.5 to 3.0.
In above-mentioned intermediate structure 602, above the first nitrogenous tungsten layer 602B, form tungsten silicide layer 602C by PVD rule such as sputtering method.Utilize the tungsten silicide sputtering target to implement sputtering method and allow evenly formation tungsten silicide layer 602C and irrelevant with bottom-layer-type.
Fig. 7 D illustrates the gate stack structure according to the 15 embodiment of the present invention.This gate stack structure comprises the first conductive layer 611, intermediate structure 612 and the second conductive layer 613.The first conductive layer 611 comprises for example boron (B) or the N-type impurity polysilicon layer of phosphorus (P) for example of highly doped P-type impurity.Except polysilicon layer, the first conductive layer 611 also can comprise polycrystalline silicon germanium (Si
1-xGe
x) layer, wherein x perhaps comprises silicide layer in about scope of 0.01 to 1.0.This silicide layer comprises the silicide that is selected from nickel (Ni), chromium (Cr), cobalt (Co), titanium (Ti), tungsten (W), tantalum (Ta), hafnium (Hf), zirconium (Zr) and platinum (Pt).
The second conductive layer 613 comprises tungsten layer.One of them of enforcement PVD method, CVD method and ALD method is to form about 100
To 2,000
Thick tungsten layer.The PVD method comprises the sputtering method that uses the tungsten sputtering target.
Gate stack structure according to the 15 embodiment of the present invention is at the resulting structures to implementing according to the gate stack structure of the of the present invention the 13 and the 14 embodiment to provide after the annealing in process.This annealing is included in and forms the heat treatment of following during the various processes (for example, sept forms and interlayer insulating film forms) of implementing behind the gate stack structure.
With reference to figure 7D and 7A, compare intermediate structure 612 and intermediate structure 62.When titanium layer 62A with from the reaction of the polysilicon of the first conductive layer 61 time, form and have about 1
To 30
The titanium silicide layer 612A of thickness.Silicon among the titanium silicide layer 612A to the ratio of titanium in about scope of 0.5 to 3.0.
When supplying nitrogen to titanium layer 62A from the first nitrogenous tungsten layer 62B, obtain nitrogenous titanium layer 612B.Nitrogenous titanium layer 612B has about 10
To 100
The thickness of scope and have the nitrogen of about 0.6 to 1.2 scope to the ratio of titanium.
After annealing, every one deck of the first and second nitrogenous tungsten layer 612C and 612E has because degrading is down to about 10% or still less nitrogen content.Reference numeral WN
x(D) the nitrogenous tungsten layer of expression through degrading.Every one deck of the first and second nitrogenous tungsten layer 612C and 612E is about 20
To 200
Thick.Nitrogen in every one deck of the first and second nitrogenous tungsten layer 612C and 612E to the ratio of tungsten in about scope of 0.01 to 0.15.
When the nitrogen that decomposes from the first and second nitrogenous tungsten layer 602B and 602D, tungsten silicide layer 602C is transformed into nitrogenous tungsten silicide layer 612D.Silicon among the nitrogenous tungsten silicide layer 612D to the ratio of tungsten in about scope of 0.5 to 3.0.Nitrogenous tungsten silicide layer 612D has about nitrogen content of 10% to 60% and about 20
To 200
Thickness.
With reference to figure 7D and 7C, compare intermediate structure 612 and intermediate structure 602.During annealing in process, from nitrogenous tungsten layer 602B supply nitrogen to nitrogenous titanium layer 602A.As a result, nitrogenous titanium layer 602A is transformed into the nitrogenous titanium layer 612B that minimal reaction is arranged with titanium silicide layer 612A.The thickness of titanium silicide layer 612A is about 1
To 30
Scope in, and the thickness of nitrogenous titanium layer 612B is about 10
To 100
Scope in.Nitrogen among the nitrogenous titanium layer 612B to the ratio of titanium in about scope of 0.7 to 1.3.
After annealing, when degrading the first and second nitrogenous tungsten layer 602B and 602D, every one deck of the first and second nitrogenous tungsten layer 612C and 612E has is down to about 10% or nitrogen content still less.Every one deck of the first and second nitrogenous tungsten layer 612C and 612E is about 20
To 200
Thick.Nitrogen in every one deck of the first and second nitrogenous tungsten layer 612C and 612E to the ratio of tungsten in about scope of 0.01 to 0.15.
When the nitrogen that degrades from the first and second nitrogenous tungsten layer 602B and 602D, tungsten silicide layer 602C is transformed into nitrogenous tungsten silicide layer 612D.Nitrogenous tungsten silicide layer 612D has about silicon of 0.5 to 3.0 to ratio and about nitrogen content of 10% to 60% of tungsten.The thickness of nitrogenous tungsten silicide layer 612D is about 20
To 200
Scope in.
Gate stack structure according to the 15 embodiment comprises the first intermediate structure and the second intermediate structure.The first intermediate structure comprises metal silicide layer and the first nitrogen containing metal layer, and the second intermediate structure comprises the second nitrogen containing metal layer, nitrogen containing metal silicide layer and the 3rd nitrogen containing metal layer.For example, form the first intermediate structure by stacking titanium silicide layer 612A and nitrogenous titanium layer 612B.Form the second intermediate structure by stacking nitrogenous tungsten layer 612C, nitrogenous tungsten silicide layer 612D and nitrogenous tungsten layer 612E.
The intermediate structure according to the first to the 15 embodiment of the present invention be can implement, thereby except the gate electrode of control dynamic random access memory device (DRAM), the gate electrode of flash memory and the gate electrode of a large amount of logical devices also can be controlled.
Fig. 8 illustrates the canopy stacks structure according to the flash memory of the 16 embodiment of the present invention.Above substrate 701, form the tunnel oxide 702 corresponding to gate insulator.Above tunnel oxide 702, be formed for the first polysilicon electrode 703 of floating grid FG.
Above the first polysilicon electrode 703, form dielectric layer 704, and above dielectric layer 704, be formed for controlling the second polysilicon electrode 705 of canopy utmost point CG.
Above the second polysilicon electrode 705, form the intermediate structure 706 that is selected from the first to the 15 described various types of intermediate structures of embodiment of the present invention.Intermediate structure 706 comprises the Ti/WN according to the first embodiment of the present invention
x/ WSi
xN
yIntermediate structure.Therefore, form intermediate structure 706 by sequence stack titanium layer 706A, nitrogenous tungsten layer 706B and nitrogenous tungsten silicide layer 706C.
Above intermediate structure 706, form tungsten electrode 707 and hard mask 708.Reference numeral W and H/M represent respectively tungsten electrode 707 and hard mask 708.
The gate stack structure of the flash memory with intermediate structure 706 shown in Figure 8 has low sheet resistor and contact resistance.Except gate electrode, embodiment of the present invention also can be applicable to various metal interconnected, for example bit line, metal wire and comprise the electrode for capacitors of intermediate structure.In addition, embodiment of the present invention can be applicable to the gate stack structure of semiconductor device, wherein this gate stack structure consists of the dual poly grid, and this dual poly grid is made of with second grid stacked structure (comprising the polysilicon electrode that is doped with P-type impurity and the tungsten electrode that forms above intermediate structure) first grid stacked structure (being included in the polysilicon electrode of the N-type that the is doped with impurity that forms below the intermediate structure and the tungsten electrode that is forming above the intermediate structure).
Fig. 9 is the figure of sheet resistor (Rs) of tungsten layer that the intermediate structure of each type that forms according to the first to the 15 embodiment of the present invention is shown.This tungsten layer has the thickness of about 40nm.
Can be observed at Ti/WN
xThe intermediate structure top additionally applies WSi by CVD method and PVD method
x/ WN
xIntermediate structure (that is, Ti/WN
x/ CVD-WSi
x/ WN
xStructure and Ti/WN
x/ PVD-WSi
x/ WN
xStructure) and WSi
xN
yLayer (that is, Ti/WN
x/ WSi
xN
yStructure) in the situation, the sheet resistor of tungsten electrode reduces.Yet, because can't be at WN by the CVD method
xWSi well grows in layer top
xLayer is so need by PVD rule such as sputtering method at WN
xLayer top forms WSi
xLayer.Implement WSi by the reactive sputtering sedimentation of using tungsten silicide sputtering target and nitrogen
xN
yThe formation of layer.
To relatively be used for Ti/WN
x/ CVD-WSi
x/ WN
xIntermediate structure, Ti/WN
x/ PVD-WSi
x/ WN
xIntermediate structure and Ti/WN
x/ WSi
xN
yThe sheet resistor of the tungsten electrode of intermediate structure.The sheet resistor of this tungsten electrode is only being used Ti/WN
x/ PVD-WSi
x/ WN
xLower in the situation of intermediate structure, and Ti/WN
x/ WSi
xN
yIntermediate structure and application WSi
x/ WN
xThe situation of intermediate structure is identical.Applying WSi by the CVD method
xIn the situation of layer, can't be at this WN
xLayer top is formed uniformly WSi
xLayer.As a result, at WN
xLayer top produces caking, increases thus sheet resistor.On the contrary, utilize WSi if use
xThe sputtering method of sputtering target or reactive sputtering sedimentation then can be formed uniformly WSi
xDiffusion layer reduces the sheet resistor of this tungsten electrode thus.
Figure 10 A to 10C illustrates the gate pattern process of using the gate stack structure shown in Fig. 3 A.Represent herein identical element with Reference numeral identical among Fig. 3 A.
With reference to figure 10A, above substrate 800, form gate insulator 801, wherein in substrate 801, implement ion implantation process to form separator, trap and raceway groove.
Above gate insulator 801, form patterning the first conductive layer 21.Above patterning the first conductive layer 21, form intermediate structure 22.Above intermediate structure 22, form patterning the second conductive layer 23.
Patterning the first conductive layer 21 comprises for example boron or the N-type impurity polysilicon layer of phosphorus for example of highly doped P-type impurity.Patterning the first conductive layer 21 also can comprise polysilicon germanium layer (Si
1-xGe
x, wherein x is in about scope of 0.01 to 1.0) or silicide layer.For example, this silicide layer comprises the silicide that is selected from nickel (Ni), chromium (Cr), cobalt (Co), titanium (Ti), tungsten (W), tantalum (Ta), hafnium (Hf), zirconium (Zr) and platinum (Pt).
Patterning the second conductive layer 23 comprises tungsten layer.Form this tungsten layer by implementing PVD method, CVD method or ALD method.The PVD method comprises the sputtering method that uses the tungsten sputtering target.
Above patterning the second conductive layer 23, form hard mask 802.Can omit the formation of hard mask 802.Hard mask 802 comprises silicon nitride (Si
3N
4).
Implement the gate pattern process, to form described gate stack structure.Particularly, although do not show, but use the etching barrier grid mask (not shown) that is formed by photoresist layer to implement the first patterning process, with etch hard mask layer, the second conductive layer, the multilayer of titanium layer, nitrogenous tungsten layer and nitrogenous tungsten silicide layer that is used for intermediate structure 22 and the part of the first conductive layer.As a result, above gate insulator 801 and substrate 800, form the structure that comprises hard mask 802, patterning the second conductive layer 23, intermediate structure 22 and patterning the first conductive layer 21.
With reference to figure 10B, remove gate mask, then implement pre-sept process, to prevent non-homogeneous etching and the oxidation of patterning the second conductive layer 23 (that is, tungsten layer) and intermediate structure 22.For example, form Si
3N
4Layer 803 is as pre-spacer layer.
With reference to figure 10C, implement second grid patterning process, with etching Si
3N
4The part of layer 803 and patterning the first conductive layer 21.During second grid patterning process, use dry etching method etching Si
3N
4The part of layer 803 forms sept 803A with the sidewall at gate stack structure.Use sept 803A as etch stop layer with etched patternization the first conductive layer 21.Reference numeral 21A represents electrode (for example, polysilicon electrode).
The first and second gate pattern processes of using above-mentioned front pre-parting layer can be applied to the gate stack structure according to the second to the 15 embodiment of the present invention.
Figure 11 illustrates another gate pattern process of using the gate stack structure shown in Fig. 3 A.The same reference numerals of using among Figure 10 A to 10C represents similar elements at this.
Above substrate 800, form gate insulator 801, wherein in substrate 801, implement ion implantation process to form separator, trap and raceway groove.Above gate insulator 801, form patterning the first conductive layer 21B.Above patterning the first conductive layer 21B, form intermediate structure 22.Above intermediate structure 22, form patterning the second conductive layer 23.
Patterning the first conductive layer 21B comprises for example boron or the N-type impurity polysilicon layer of phosphorus for example of highly doped P-type impurity.Patterning the first conductive layer 21B also can comprise polysilicon germanium layer (Si
1-xGe
x, wherein x is in about scope of 0.01 to 1.0) or silicide layer.For example, this silicide layer comprises the silicide that is selected from nickel (Ni), chromium (Cr), cobalt (Co), titanium (Ti), tungsten (W), tantalum (Ta), hafnium (Hf), zirconium (Zr) and platinum (Pt).
Patterning the second conductive layer 23 comprises tungsten layer.Form this tungsten layer by implementing PVD method, CVD method or ALD method.The PVD method comprises the sputtering method that uses the tungsten sputtering target.
Above patterning the second conductive layer 23, form hard mask 802.Can omit the formation of hard mask 802.Hard mask 802 comprises silicon nitride (Si
3N
4).
Implement the gate pattern process, to form described gate stack structure.Particularly, although show, use the etching barrier grid mask (not shown) that is formed by photoresist layer come while etch hard mask layer, the second conductive layer, for the multilayer of titanium layer, nitrogenous tungsten layer and the nitrogenous tungsten silicide layer of intermediate structure 22 and the part of the first conductive layer.As a result, above gate insulator 801 and substrate 800, form the structure that comprises hard mask 802, patterning the second conductive layer 23, intermediate structure 22 and patterning the first conductive layer 21B.The gate pattern process of selecting to implement etching immediately and not using pre-spacer layer is to substitute the gate pattern process that is comprised of two steps using pre-spacer layer.The gate pattern process of not using pre-spacer layer to implement can be applied to the gate stack structure according to the second to the 15 embodiment of the present invention.
According to embodiment of the present invention, by being configured in comprising the intermediate structure that a plurality of thin layers that titanium, tungsten, silicon and nitrogen or every layer comprises nitrogen consist of and to obtain such as poly-Si/WN between tungsten electrode and the polysilicon electrode
x/ W and poly-Si/WN
x/ WSi
xThe sheet resistor that/W intermediate structure is equally low.Therefore, can reduce the height of gate stack structure, be easy to thus procurement process and integrate.
Because boron penetration or boron to the minimizing of outdiffusion, so that can reduce poly-Si depletion effect, therefore can increase the operating current of PMOSFET.In addition, between tungsten electrode and polysilicon electrode, can obtain very low contact resistance, thereby be conducive to the manufacturing of high speed device.
As for the method that forms in order to the tungsten polysilicon gate of making high speed, high density, low power memory spare, can be by the intermediate structure implementing to be consisted of by a plurality of films that comprise Ti, W, Si and N or each film and comprise nitrogen with acquisition low contact resistance and low poly-Si depletion effect.
Although describe the present invention with reference to particular, those skilled in the art it is evident that within not breaking away from spirit of the present invention that appended claims limits and scope can implement various changes and modification.
Claims (43)
1. semiconductor device comprises:
The first conductive layer;
The first intermediate structure above described the first conductive layer, described the first intermediate structure comprises metal silicide layer and nitrogen containing metal layer, the metal silicide layer of wherein said the first intermediate structure comprises one of them of titanium silicide layer and silication tantalum layer, and the nitrogen containing metal layer of wherein said the first intermediate structure comprises nitrogenous titanium layer and nitrogenous tantalum layer one of them;
The second intermediate structure above described the first intermediate structure, described the second intermediate structure comprises at least nitrogen containing metal silicide layer; With
The second conductive layer above described the second intermediate structure.
2. semiconductor device as claimed in claim 1 wherein forms described nitrogen containing metal silicide layer by utilizing the metal silicide sputtering target to implement the reactive sputtering sedimentation in nitrogen environment.
3. semiconductor device as claimed in claim 2, wherein said metal silicide sputtering target comprises the sputtering target that is selected from tungsten silicide sputtering target, titanium silicide sputtering target and tantalum silicide sputtering target.
4. semiconductor device as claimed in claim 2, wherein said nitrogen containing metal silicide layer have the silicon of 10% to 60% nitrogen content and 0.5 to 3.0 to the atomic ratio of metal.
5. semiconductor device as claimed in claim 1, wherein said the second intermediate structure comprises nitrogen containing metal layer and the nitrogen containing metal silicide layer that order forms, and wherein said nitrogen containing metal layer comprises one of them of nitrogenous tungsten layer and nitrogenous titanium tungsten layer and has 0.01 to 0.15 nitrogen to the atomic ratio of metal.
6. semiconductor device as claimed in claim 1, wherein said the second intermediate structure comprises nitrogen containing metal silicide layer and the nitrogen containing metal layer that order forms, and wherein said nitrogen containing metal layer comprises one of them of nitrogenous tungsten layer and nitrogenous titanium tungsten layer and has 0.01 to 0.15 nitrogen to the atomic ratio of metal.
7. semiconductor device as claimed in claim 1, wherein said the second intermediate structure comprises the first nitrogen containing metal layer, nitrogen containing metal silicide layer and the second nitrogen containing metal layer that order forms, and every one deck of wherein said the first nitrogen containing metal layer and described the second nitrogen containing metal layer comprises one of them of nitrogenous tungsten layer and nitrogenous titanium tungsten layer and has 0.01 to 0.15 nitrogen to the atomic ratio of metal.
8. semiconductor device as claimed in claim 1, wherein said metal silicide layer have 0.5 to 3.0 silicon to the atomic ratio of metal.
9. semiconductor device as claimed in claim 1, the nitrogen containing metal layer of wherein said the first intermediate structure have 0.7 to 1.3 nitrogen to the atomic ratio of metal.
10. semiconductor device as claimed in claim 1, wherein said the first conductive layer comprises one of them that is selected from polysilicon layer, polysilicon germanium layer and silicide layer, and described the second conductive layer comprises tungsten.
11. semiconductor device as claimed in claim 10, wherein said doping polycrystalline silicon layer have P-type impurity.
12. semiconductor device as claimed in claim 1, wherein said the first conductive layer comprise that the polysilicon layer that is doped with N-type impurity is doped with the polysilicon layer of P-type impurity with another, provides dual poly canopy stacks structure thus.
13. semiconductor device as claimed in claim 1 also comprises: substrate; Be positioned at the floating grid on the described substrate; Be positioned at the dielectric layer on the described floating grid; With the control grid that is positioned on the described dielectric layer,
Wherein said control grid is described the first conductive layer.
14. a semiconductor device comprises:
The first conductive layer;
Intermediate structure, it is formed on described the first conductive layer top and comprises at least the first metal layer, nitrogen containing metal silicide layer and the second metal level, and wherein said the second metal level comprises one of them of nitrogenous tungsten layer and nitrogenous titanium tungsten layer; With
The second conductive layer, it is formed on described intermediate structure top,
Wherein said the second metal level comprises the first nitrogen containing metal layer and has 0.3 to 1.5 nitrogen to the atomic ratio of metal.
15. semiconductor device as claimed in claim 14, wherein said the second metal level are inserted between described the first metal layer and the described nitrogen containing metal silicide layer.
Comprise described the first metal layer, be positioned at the described nitrogen containing metal silicide layer on the described the first metal layer and be positioned at the stacked structure of described the second metal level on the described nitrogen containing metal silicide layer 16. semiconductor device as claimed in claim 14, wherein said intermediate structure form.
17. semiconductor device as claimed in claim 14, wherein said the second metal level are inserted between described the first metal layer and the described nitrogen containing metal silicide layer, described intermediate structure also comprises the 3rd metal level that is positioned on the described nitrogen containing metal silicide layer.
18. semiconductor device as claimed in claim 14, wherein said the first metal layer comprise simple metal layer and the second nitrogen containing metal layer one of them.
19. semiconductor device as claimed in claim 18, wherein said simple metal layer comprises one of them of titanium layer and tantalum layer.
20. semiconductor device as claimed in claim 18, wherein said simple metal layer forms
Extremely
Thickness.
21. semiconductor device as claimed in claim 18, wherein said the second nitrogen containing metal layer comprises one of them of nitrogenous titanium layer and nitrogenous tantalum layer.
22. semiconductor device as claimed in claim 18, wherein said the second nitrogen containing metal layer forms
Extremely
Thickness.
23. semiconductor device as claimed in claim 18, the nitrogen in wherein said the second nitrogen containing metal layer to the atomic ratio of metal in 0.2 to 0.8 scope.
24. semiconductor device as claimed in claim 17, wherein said the 3rd metal level comprises one of them of nitrogenous tungsten layer and nitrogenous titanium tungsten layer.
25. semiconductor device as claimed in claim 24, wherein said the 3rd metal level have 0.3 to 1.5 nitrogen to the atomic ratio of metal.
26. semiconductor device as claimed in claim 14 wherein forms described nitrogen containing metal silicide layer by utilizing the metal silicide sputtering target to implement the reactive sputtering sedimentation in nitrogen environment.
27. comprising, semiconductor device as claimed in claim 26, wherein said metal silicide sputtering target be selected from a kind of in tungsten silicide sputtering target, titanium silicide sputtering target and the tantalum silicide sputtering target.
28. semiconductor device as claimed in claim 27, wherein said nitrogen containing metal silicide layer have the silicon of 10% to 60% nitrogen content and 0.5 to 3.0 to the atomic ratio of metal.
29. semiconductor device as claimed in claim 14, wherein said the first conductive layer comprises one of them that is selected from polysilicon layer, polysilicon germanium layer and silicide layer, and described the second conductive layer comprises tungsten.
30. semiconductor device as claimed in claim 29, wherein said doping polycrystalline silicon layer have P-type impurity.
31. semiconductor device as claimed in claim 14, wherein said the first conductive layer comprise that the polysilicon layer that is doped with N-type impurity is doped with the polysilicon layer of P-type impurity with another, provides the dual poly gate stack structure thus.
32. semiconductor device as claimed in claim 14 also comprises: substrate; Be positioned at the floating grid on the described substrate; Be positioned at the dielectric layer on the described floating grid; And be positioned at control grid on the described dielectric layer,
Wherein said control grid is described the first conductive layer.
33. a semiconductor device comprises:
The first conductive layer;
Intermediate structure, it is positioned on described the first conductive layer and comprises the first metal layer, the second metal level, metal silicide layer and the 3rd metal level; With
The second conductive layer, it is positioned on the described intermediate structure,
Every one deck of wherein said first, second, and third metal level comprises the nitrogen containing metal layer, and every one deck of the described second and the 3rd metal level comprises one of them of nitrogenous tungsten layer and nitrogenous titanium tungsten layer.
34. semiconductor device as claimed in claim 33, wherein said metal silicide layer comprises one of them of tungsten silicide layer, titanium silicide layer and silication tantalum layer, wherein forms every one deck in described tungsten silicide layer, described titanium silicide layer and the described silication tantalum layer by the reactive sputtering sedimentation.
35. semiconductor device as claimed in claim 33, wherein said metal silicide layer have 0.5 to 3.0 silicon to the atomic ratio of metal.
36. semiconductor device as claimed in claim 34, wherein said nitrogenous tungsten layer have 0.3 to 1.5 nitrogen to the atomic ratio of tungsten.
37. semiconductor device as claimed in claim 34, wherein said nitrogenous titanium tungsten layer have 0.3 to 1.5 titanium to the atomic ratio of tungsten and 10% to 60% nitrogen content.
38. semiconductor device as claimed in claim 34, wherein said the first metal layer have 0.2 to 0.8 nitrogen to the atomic ratio of metal.
39. semiconductor device as claimed in claim 38, wherein said the first metal layer comprises one of them of nitrogenous titanium layer and nitrogenous tantalum layer.
40. semiconductor device as claimed in claim 33, wherein said the first conductive layer comprises one of them that is selected from polysilicon layer, polysilicon germanium layer and silicide layer, and described the second conductive layer comprises tungsten.
41. semiconductor device as claimed in claim 40, wherein said doping polycrystalline silicon layer have P-type impurity.
42. semiconductor device as claimed in claim 33, wherein said the first conductive layer comprise that the polysilicon layer that is doped with N-type impurity is doped with the polysilicon layer of P-type impurity with another, provides the dual poly gate stack structure thus.
43. semiconductor device as claimed in claim 33 also comprises: substrate; Be positioned at the floating grid on the described substrate; Be positioned at the dielectric layer on the described floating grid; With the control grid that is positioned on the described dielectric layer,
Wherein said control grid is described the first conductive layer.
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| TWI581318B (en) * | 2015-06-03 | 2017-05-01 | 華邦電子股份有限公司 | Gate conductor and fabrication method thereof |
| US9461137B1 (en) * | 2015-09-11 | 2016-10-04 | Applied Materials, Inc. | Tungsten silicide nitride films and methods of formation |
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| TWI349956B (en) | 2011-10-01 |
| DE102007060238A1 (en) | 2009-01-29 |
| CN100550306C (en) | 2009-10-14 |
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