CN107845632A - Dynamic random access memory - Google Patents
Dynamic random access memory Download PDFInfo
- Publication number
- CN107845632A CN107845632A CN201610837520.7A CN201610837520A CN107845632A CN 107845632 A CN107845632 A CN 107845632A CN 201610837520 A CN201610837520 A CN 201610837520A CN 107845632 A CN107845632 A CN 107845632A
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- Prior art keywords
- layer
- stochastic
- memory component
- layer structure
- component described
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/50—Peripheral circuit region structures
Abstract
The present invention discloses a kind of dynamic random access memory, includes substrate, multiple embedded grids and multiple bit lines.Embedded grid is provided in the first groove of substrate and extended along a first direction.Bit line is then provided on embedded grid and extended along second direction, and second direction is then across first direction.Each bit line packet contains a barrier layer, and it has a lamination layer structure.Lamination layer structure includes WSixNyAnd the silicone content of its bottom is higher and nitrogen content at the top of it is higher.
Description
Technical field
The present invention relates to a kind of memory component, and memory component is handled more particularly, to a kind of stochastic and dynamic.
Background technology
As various electronic products are towards the trend of miniaturization, dynamic random access memory (Dynamic Random
Access Memory, DRAM) design of unit also has to comply with high product into degree and highdensity requirement.Possess for one recessed
For the DRAM cell of formula grid structure, because it can obtain longer carrier pathway length in identical semiconductor base
Degree, to reduce the generation of the electric leakage situation of capacitance structure, therefore under current mainstream development trend, its gradually substituted only possess it is flat
The DRAM cell of face grid structure.
In general, the DRAM cell for possessing concave grid structure can include a transistor unit and charge storage dress
Put, to receive the voltage signal for coming from bit line and character line.However, be limited to Manufacturing Techniques it is therefore, it is existing possess it is recessed
The DRAM cell for entering formula grid structure has still suffered from many defects, also treats further to improve and effectively lifted concerned memory element
Efficiency and reliability.
The content of the invention
The purpose of the present invention is that providing a kind of stochastic and dynamic handles memory component, and it is to be provided with bit line again
One barrier layer of sheet combination structure, the nitrogen content at the top of the barrier layer is higher and the silicone content of its bottom is higher, thus, can be effective
Reduce the barrier layer and its top and/or the resistance of lower stack layer.
For the above-mentioned purpose, one embodiment of the invention provides a kind of stochastic and dynamic processing memory component, and it includes one
Substrate, multiple embedded grids and multiple bit lines.Those embedded grids are provided in a first groove of the substrate and edge
First direction extension.Those bit lines are then provided on those embedded grids and extended along a second direction, and are somebody's turn to do
Second direction is then across the first direction.Each bit line packet contains a barrier layer, and the barrier layer has a lamination layer structure.Should
The silicone content that lamination layer structure includes WSxiNy and its bottom is higher and nitrogen content at the top of it is higher.
The stochastic and dynamic processing memory component of the present invention be mainly its bit line polysilicon layer and metal conducting layer it
Between, the barrier layer with lamination layer structure is set and the lamination layer structure is by tungsten silicon nitrogen (WSixNy) composition.Wherein, this is multiple
The silicone content of the bottom of sheet combination structure is higher, and the characteristic similar to ohmic contact layer (ohmic layer) can be presented.The opposing party
Face, the top of the lamination layer structure is then that nitrogen content is higher, and the top of the lamination layer structure can be made to have larger big pipe
Core.In the case, the resistance between the barrier layer and underlying polysilicon layer can be can be effectively reduced, and the barrier layer and top
Crystal boundary between metal conducting layer then can be equally can be effectively reduced, thus the barrier layer is had relatively low resistance in itself.
Brief description of the drawings
Fig. 1 is the schematic top plan view that stochastic and dynamic handles memory component in present pre-ferred embodiments；
Fig. 2 is diagrammatic cross-sections of the Fig. 1 along tangent line A-A '；
Fig. 3 is diagrammatic cross-sections of the Fig. 1 along tangent line B-B '；
Fig. 4 is the enlarged schematic partial view of region R in Fig. 3.
Main element symbol description
100 substrates
101 active regions
102 memory areas
104 peripheral regions
106 shallow-channel insulations
108th, 118 groove
110 dynamic random access memories
112 dielectric layers
114 grids
116 insulating barriers
124
160 bit lines
160a bit line contact plugs
161 polysilicon layers
163 barrier layers
163a tungsten silicon layers
163b tungsten nitrogen layers
165 metal conducting layers
170 mask layers
Embodiment
To enable the general technology person for being familiar with the technical field of the invention to be further understood that the present invention, hereafter spy enumerates
Several preferred embodiments of the present invention, and accompanying drawing appended by cooperation, the work(for describing the constitution content of the present invention in detail and being reached
Effect.
Fig. 1 to Fig. 3 is refer to, illustrated is that stochastic and dynamic handles showing for memory component in present pre-ferred embodiments
It is intended to, wherein Fig. 1 is top view, and Fig. 2 and Fig. 3 are then shown in Fig. 1 along tangent line A-A ' and B-B ' sectional view respectively.This implementation
Example is to provide a memory cell (memory cell), e.g. possesses the stochastic and dynamic processing memory of concave grid
(dynamic random access memory, DRAM) element 110, its include an at least transistor unit (not illustrating) with
And an at least capacitance structure (not illustrating), using as the minimum composition unit in DRAM array and receive come from bit line 160 and
The voltage signal of character line.
Dynamic random access memory 110 includes a substrate 100, and exhausted formed with an at least shallow ridges in substrate 100
Edge 106, to define multiple active regions (active area, AA) 101 in substrate 100, as shown in Figure 1.In addition, substrate 100
On there is also defined a memory areas 102 and a peripheral region 104.Wherein, multiple words of dynamic random access memory 110
Symbol line (word line, BL, i.e. grid 114) is formed in the storage of substrate 100 with multiple bit lines (bit line, BL) 160 etc.
Device area 102, as shown in Fig. 2 and other active members etc. (not illustrating) then may be formed at peripheral region 104.It is noted that it is
Simplify explanation, Fig. 1 of the invention only shows the upper schematic diagram of the element positioned at memory areas 102, and eliminates positioned at week
The element in border area 104.
In the present embodiment, each active region 101 is, for example, and extended in parallel to each other towards a first direction, and grid 114
It is formed in substrate 100 and across on each active region 101.Specifically, each grid 114 is formed in the one of substrate 100
In groove 108, and groove 108 e.g. extends towards the second direction for being different from the first direction, and the second direction is with being somebody's turn to do
First direction intersects, as shown in Figure 1.In one embodiment, the generation type of grid 114 is, for example, and includes to be initially formed to be covered in ditch
One dielectric layer 112 on the surface of groove 108, as gate insulator, it is, for example, one silica layer, formed grid 114, then then at
An insulating barrier 116 is covered on grid 114.Thus, insulating barrier 116 is made to trim the surface of substrate 100, and grid 114 then can be as one
Embedded character line (buried word line, BWL), as shown in Figures 2 and 3.
On the other hand, bit line 160 is then to be formed along a third direction to extend in substrate 100 in parallel to each other, and together
Sample is across each active region 101.Wherein, the third direction is equally to be different from the first direction, and preferably and second direction
Vertically.That is, the first direction, second direction and third direction are all different each other, and the first direction and the second party
To and the third direction all out of plumb, as shown in Figure 1.It is by being formed in substrate 100 between bit line 160 and character line 114
An insulating barrier 124 it is mutually isolated, and bit line 160 further passes through an at least bit line contact plug (bit line
Contact, BLC) 160a is to electrically couple to the source/drain region (not illustrating) of the respectively transistor unit.Bit line contact plug
160a is, for example, to be formed below bit line 160, and boundary is between two character lines 114.Also, bit line contact plug 160a includes one
Conductor layer, the grade semiconductor layer of an e.g. polysilicon layer 161, as shown in Figure 2.
In one embodiment, bit line contact plug 160a generation type is, for example, and includes to be initially formed in substrate 100
Multiple grooves 118, followed by the formation polysilicon layer 161 that fills up groove 118 and be further covered on insulating barrier 124, such as
Shown in Fig. 2 and Fig. 3.Subsequently, continuously form the barrier layer 163 being covered on polysilicon layer 161, a metal conducting layer 165 and
One mask layer 170, then, metal conducting layer 165, barrier layer 163 and the polysilicon layer of patterned mask layer 170 and lower section
161, you can while form bit line 160 and the bit line contact plug 160a positioned at the lower section of part bit line 160.That is, position
Line 160 is integrally formed in fact with bit line contact plug 160a, and is collectively forming by same polysilicon layer 161.
It is noted that bit line 160 is the polysilicon layer 161, barrier layer 163 and metal by being sequentially stacked on substrate 100
Conductive layer 165 is collectively constituted.Wherein, barrier layer 163 is, for example, to include by tungsten silicon nitrogen (WSixNy) the composite bed knot that is formed
Structure, and metal conducting layer 165 is, for example, then comprising tungsten (tungsten, W), aluminium (aluminum, Al) or copper (copper, Cu) etc.
Low-resistance matter metal material, but be not limited.Wherein, barrier layer 163 is for reducing polysilicon layer 161 and metal conducting layer
165 contact resistance (contact resistance) and sheet resistance (sheet resistance), it can for example include mutual
The metal oxide layer of multilayer first of stacking interlocks with the metal oxide layer of multilayer second and repeats to set, and in the different depositional phases
In, at least metal oxide layer of multilayer first or at least metal oxide layer of multilayer second is to be in contact with each other.First metal oxide layer
And second metal oxide layer is to carry out ald (atomic layer deposition, ALD) the manufacture craft phase
Between, sequentially and each lead into different predecessors and formed.For example, first metal oxide layer is, for example, with tungsten hexafluoride
(tungsten hexafluoride,WF6) and silicomethane (silane, SiH4) formed as predecessor, and second metal
Oxide layer is then with tungsten hexafluoride and ammonia (ammonia, NH3) formed as predecessor, thus, make first metal oxide layer
There can be relatively low resistance for a tungsten silicon (tungsten silicon, WSi) layer 163a, and can effectively reduce barrier layer 163
Resistance between the polysilicon layer 161 of lower section；Second metal oxide layer can be then a tungsten nitrogen (tungsten nitride, WN)
Layer 163b and there is larger tube core (grain), and can effectively reduce between barrier layer 163 and the metal conducting layer 165 of top
Crystal boundary (grain boundary).
It is another it is noted that though the barrier layer 163 of the present embodiment in formation is to be made with being passed through tungsten hexafluoride with ammonia at the beginning
Formed for predecessor based on tungsten nitrogen layer 163b circulation, but simultaneously with being formed between each tungsten nitrogen layer 163b circulation is formed
Tungsten nitrogen layer 163a circulation, and in the depositional phase in the early stage, preferably make tungsten nitrogen layer 163b and tungsten silicon layer 163a stacking
Number of plies ratio is about 2:1 to 4:3, as shown in Figure 4.Or in other embodiments, selected in depositional phase that also can be in the early stage
Tungsten nitrogen layer 163b and tungsten silicon layer 163a stacking number ratio is set to reach 0.1-1:10-20, but be not limited.And in barrier layer
During 163 form, tungsten nitrogen layer 163b circulation i.e. gradually increase is formed, therefore, at end of the barrier layer 163 in formation,
Tungsten nitrogen layer 163b and tungsten silicon layer 163a stacking number ratio is then preferably about 5:1 to 10:1, as shown in Figure 4.Or at it
In his embodiment, it can also select to reach tungsten nitrogen layer 163b and tungsten silicon layer 163a stacking number ratio in the depositional phase in latter stage
To 10-20:0.1-1, but be not limited.That is, though the barrier layer 163 in the present embodiment is by tungsten silicon nitrogen (WSixNy)
The lamination layer structure formed, and depositional phase in the early stage are the bottoms for making formed barrier layer 163 (that is, close to more
The part of crystal silicon layer 161) silicone content it is higher (silicon-rich), e.g. make tungsten silicon nitrogen (WSixNy) in x:Y ratio is about
For 10-20:0.1；And in the depositional phase in latter stage, then it is the top for making formed barrier layer 163 (that is, close to metallic conduction
Layer 165 part) nitrogen content it is higher (nitrogen-rich), e.g. make tungsten silicon nitrogen (WSixNy) in x:Y ratio is about
0.1:10-20, but be not limited.
In addition, in another embodiment, also may be selected directly to form silicone content or nitrogen content is in the one of continuous gradient relation
Barrier layer, the barrier layer are, for example, to include tungsten silicon nitrogen (WSixNy), wherein, x, y are all the constant more than zero, and x:Y ratio is
Changed with each position of the barrier layer, preferably from its bottom toward top be approximately from 20:0.1 changes to 0.1:20, but not with this
It is limited.Specifically, the barrier layer is, for example, to have a single film layer, but in the lower half of the barrier layer, its x:Y ratio
About 10-20:0.1-1, and its x ratio regular meeting with more toward the first half of the barrier layer and it is smaller, and y ratio regular meeting then with
More toward the first half of the barrier layer and it is bigger, therefore, in the first half of the barrier layer, its x:Y ratio can reach 0.1:10-
20。
In addition, this area person will be readily appreciated that, though it is to illustrate first to carry out 3 formation tungsten silicon layer 163a in Fig. 4 of the present invention
Circulation carry out 4 circulations for forming tungsten nitrogen layer 163b again, carry out 2 circulations for forming tungsten silicon layer 163a and 4 times again afterwards
Form tungsten nitrogen layer 163b circulation etc., but the manufacture craft of barrier layer of the present invention 163 not with preferentially form tungsten silicon layer 163a or
Tungsten nitrogen layer 163b is limited.In other embodiments, the circulation that also may be selected first to carry out being formed tungsten nitrogen layer 163b carries out forming tungsten again
Silicon layer 163a circulation, but still need to the stacking number ratio for making tungsten nitrogen layer 163b and tungsten silicon layer 163a in the lower half of barrier layer 163
Reach 4:3 to 2:1, and the stacking number ratio of tungsten nitrogen layer 163b and tungsten silicon layer 163a in the first half of barrier layer 163 is reached 10-
20:1-0.1。
It follows that the stochastic and dynamic processing memory component in present pre-ferred embodiments is mainly in the more of its bit line
Between crystal silicon layer and metal conducting layer, the barrier layer with lamination layer structure is set, and the lamination layer structure is by tungsten silicon nitrogen
(WSixNy) composition.Wherein, the bottom of the lamination layer structure is by higher proportion (that is, close to the part of underlying polysilicon layer)
Tungsten silicon layer is formed, and therefore, its silicone content is higher, such as makes x:Y ratio is about 10-20:1-0.1.In the case, this is multiple
The characteristic similar to ohmic contact layer (ohmic contact layer) can be presented in the bottom of sheet combination structure, and can effectively reduce
Resistance between the barrier layer resistance in itself and the barrier layer and underlying polysilicon layer.Conversely, the top of the lamination layer structure
Portion is then made up of (that is, close to the part of upper metal conductive layer) the tungsten nitrogen layer of higher proportion, therefore, its nitrogen content compared with
Height, such as make x:Y ratio is about 0.1-1:10-20.In the case, the top of the lamination layer structure can have larger big
Tube core, and can effectively reduce the crystal boundary between the barrier layer and the metal conducting layer of top.Thus, barrier layer of the invention itself
Resistance can by globality be lowered.On the other hand, though barrier layer of the invention has a lamination layer structure, its composition is single
And only need to be formed by an ald manufacture craft, thus need not be additionally formed comprising other materials or composition
Stacked material layers, the effect that the height of the bit line of the present invention can be effectively improved and simplified with manufacture craft.
Presently preferred embodiments of the present invention is the foregoing is only, all equivalent changes done according to the claims in the present invention are with repairing
Decorations, it should all belong to the covering scope of the present invention.
Claims (11)
1. a kind of stochastic and dynamic handles memory component, it is characterised in that includes：
Multiple embedded grids, it is arranged in a first groove of a substrate and extends along a first direction；And
Multiple bit lines, be arranged on those embedded grids and along a second direction extend, the second direction across this first
Direction, respectively the bit line packet contain barrier layer, the wherein barrier layer includes lamination layer structure, and the lamination layer structure includes WSxiNy, this is multiple
The silicone content of the bottom of sheet combination structure is higher and the nitrogen content at the top of the lamination layer structure is higher.
2. according to the stochastic and dynamic processing memory component described in claim 1, it is characterised in that the bottom of the lamination layer structure
In, x:Y ratio is about 10-20:1-0.1.
3. according to the stochastic and dynamic processing memory component described in claim the 1, it is characterised in that the lamination layer structure
In top, x:Y ratio is about 0.1-1:10-20.
4. according to the stochastic and dynamic processing memory component described in claim 1, it is characterised in that x is in the lamination layer structure
It is about 0.1 that bottom, which is about 20 and is little by little decremented to about 0.1, y in the bottom of the lamination layer structure toward top, and little by little past
Top is incremented to about 20.
5. according to the stochastic and dynamic processing memory component described in claim 1, it is characterised in that the lamination layer structure includes phase
The multiple tungsten silicon layers and multiple tungsten nitrogen layers mutually stacked.
6. according to the stochastic and dynamic processing memory component described in claim 5, it is characterised in that in being somebody's turn to do for the lamination layer structure
In bottom, the quantitative proportion of tungsten nitrogen layer and tungsten silicon layer is about 2:1 to 4:3.
7. according to the stochastic and dynamic processing memory component described in claim 5, it is characterised in that in being somebody's turn to do for the lamination layer structure
In top, the quantitative proportion of tungsten nitrogen layer and tungsten silicon layer is about 5:1 to 10:1.
8. according to the stochastic and dynamic processing memory component described in claim 1, it is characterised in that respectively the bit line packet is containing conduction
Layer, is arranged on the barrier layer.
9. according to the stochastic and dynamic processing memory component described in claim 1, it is characterised in that respectively the bit line packet contains polysilicon
Layer, is arranged under the barrier layer.
10. according to the stochastic and dynamic processing memory component described in claim 1, it is characterised in that also include:
An at least contact plunger, it is arranged under the bit line and between the two embedded grids.
11. according to the stochastic and dynamic processing memory component described in claim 10, it is characterised in that the contact plunger is more with this
Crystal silicon layer is integrally formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610837520.7A CN107845632A (en) | 2016-09-21 | 2016-09-21 | Dynamic random access memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610837520.7A CN107845632A (en) | 2016-09-21 | 2016-09-21 | Dynamic random access memory |
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| Publication Number | Publication Date |
|---|---|
| CN107845632A true CN107845632A (en) | 2018-03-27 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201610837520.7A Pending CN107845632A (en) | 2016-09-21 | 2016-09-21 | Dynamic random access memory |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101211771A (en) * | 2006-12-27 | 2008-07-02 | 海力士半导体有限公司 | Method for fabricating semiconductor device with gate stack structure |
| CN103633093A (en) * | 2012-08-27 | 2014-03-12 | 三星电子株式会社 | Semiconductor devices including metal-silicon-nitride patterns and methods of forming the same |
-
2016
- 2016-09-21 CN CN201610837520.7A patent/CN107845632A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101211771A (en) * | 2006-12-27 | 2008-07-02 | 海力士半导体有限公司 | Method for fabricating semiconductor device with gate stack structure |
| CN103633093A (en) * | 2012-08-27 | 2014-03-12 | 三星电子株式会社 | Semiconductor devices including metal-silicon-nitride patterns and methods of forming the same |
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Application publication date: 20180327 |