CN108962907A - Semiconductor storage and its forming method - Google Patents
Semiconductor storage and its forming method Download PDFInfo
- Publication number
- CN108962907A CN108962907A CN201710384107.4A CN201710384107A CN108962907A CN 108962907 A CN108962907 A CN 108962907A CN 201710384107 A CN201710384107 A CN 201710384107A CN 108962907 A CN108962907 A CN 108962907A
- Authority
- CN
- China
- Prior art keywords
- those
- semiconductor storage
- bit line
- substrate
- storage according
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
Abstract
The present invention disclose a kind of semiconductor storage and its forming method, wherein semiconductor storage includes multiple active regions, multiple grids, multiple bit lines, multiple bit line plugs and multiple cap rocks.Multiple active regions are to be defined in substrate, and multiple grids are arranged in substrate.On the other hand, multiple bit lines are then to be arranged in substrate, and part bit line has been respectively arranged below multiple bit line plugs.Multiple cap rocks are arranged on multiple grids, and it is to protrude from the top surface of substrate and bit line plugs, and between each bit line that multiple cap rocks, which include multiple insulation divisions,.
Description
Technical field
The present invention relates to a kind of manufacture craft of semiconductor storage, especially a kind of dynamic random handles memory device
The manufacture craft set.
Background technique
As various electronic products are towards the trend of miniaturization, dynamic random access memory (dynamic random
Access memory, DRAM) design of device also has to comply with high integration and highdensity requirement.In general, dynamically with
Machine access memory is to form an array area by storage unit (memory cell) aggregation of huge number, is used to storing data,
And each storage unit can be composed in series by a transistor unit with a charge-storage devices, to receive from character line
The voltage signal of (word line, WL) and bit line (bit line, BL).In response to product demand, the storage unit in array area is close
Degree must be promoted persistently, and relative production technique is caused to be continuously increased with the degree of difficulty in design with complexity.Therefore, the prior art is also
To further improve effectively to promote the efficiency of concerned memory element and reliability.
Summary of the invention
It is one lid of setting above each character line a purpose of the present invention is that providing a kind of semiconductor storage
Layer, and the cap rock has multiple insulation divisions projected, those insulation divisions can protrude from substrate and between each bit line, make this partly
Conductor storage device can maintain certain efficiency.
It another object of the present invention is to provide a kind of forming method of semiconductor storage, is formed in every line
Before, that is, the insulation division being initially formed between each bit line and each memory node therefore can be under the premise of manufacture craft simplifies, shape
At the semiconductor storage of tool element reliability.
In order to achieve the above object, one embodiment of the invention provides a kind of semiconductor storage, it includes multiple active regions,
Multiple grids, multiple bit lines, multiple bit line plugs and multiple cap rocks.Those active regions be defined in a substrate, and those
Grid is then arranged in the substrate.On the other hand, those bit lines are arranged on this substrate, and those bit line plugs are separately positioned on
The partially lower section of the bit line.Those cap rocks are arranged on those grids, those cap rocks include multiple insulation divisions, those insulation
Portion protrudes from the top surface of the substrate Yu those bit line plugs, and between each bit line.
In order to achieve the above object, another embodiment of the present invention provides a kind of forming method of semiconductor storage, packet
Containing following steps.Firstly, forming a shallow trench isolation in a substrate, and multiple active regions are defined in the substrate, and at this
A mask layer is formed in substrate, and the mask layer is made to cover those active regions and those shallow trench isolations.Then, the mask layer with
Multiple grooves are formed in the substrate, and multiple grids are formed in those grooves.Then, an insulation is formed on those grids
Layer, makes the insulating layer fill up those grooves.Later, the mask layer of a part and the insulating layer of a part are removed, is formed more
A bit line trenches, and it is formed simultaneously the multiple cap rocks being covered on those grids.Finally, being formed in those bit line trenches multiple
Bit line, wherein respectively the cap rock includes multiple insulation divisions, those insulation divisions are between those bit lines.
Generally, forming method of the invention is by defining rear extended meeting in advance with certain thickness mask layer
The insulation division being set between bit line and memory node, and keep the insulation division and the cap rock on character line integrally formed simultaneously
Include identical material.The cap rock that can deposit manufacture craft using same road to be formed on the character line as a result, Yi Jijie
The insulation division between the memory node and the bit line, and it is reliable to form tool element under the premise of manufacture craft simplifies
The semiconductor storage of degree.And utilize the obtained semiconductor storage of forming method of the invention, then absolutely using this
The setting of edge and the cap rock enables the semiconductor storage to maintain certain element efficiency.
Detailed description of the invention
The step of Fig. 1 to Figure 11 is the forming method of semiconductor storage in first preferred embodiment of the invention is illustrated
Figure, in which:
Fig. 1 is the upper schematic diagram of semiconductor storage device；
Fig. 2 is diagrammatic cross-section of the semiconductor storage device after forming shallow trench isolation；
Fig. 3 is diagrammatic cross-section of the semiconductor storage device after forming mask layer；
Fig. 4 is diagrammatic cross-section of the semiconductor storage device after forming groove；
Fig. 5 is diagrammatic cross-section of the semiconductor storage device after character line is buried in formation；
Fig. 6 is diagrammatic cross-section of the semiconductor storage device after forming bit line trenches；
Fig. 7 is diagrammatic cross-section of the semiconductor storage device after forming bit line；
Fig. 8 is stereoscopic schematic diagram of the semiconductor storage device after forming bit line；
Fig. 9 is another diagrammatic cross-section of the semiconductor storage device after forming bit line；
Figure 10 is diagrammatic cross-section of the semiconductor storage device after forming memory node；
Figure 11 is another diagrammatic cross-section of the semiconductor storage device after forming memory node；
Figure 12 to Figure 13 is the step section of the forming method of semiconductor memory element in second preferred embodiment of the invention
Schematic diagram；Wherein
Figure 12 is diagrammatic cross-section of the semiconductor storage device after forming bit line；
Figure 13 is stereoscopic schematic diagram of the semiconductor storage device after forming bit line.
Main element symbol description
100 substrates
101 active regions
102 shallow trench isolations
130 mask layers
131 first mask layers
133 second mask layers
135 third mask layers
150 character lines
151 gate dielectrics
153 barrier layers
157 grids
160 insulating layers
161 cap rocks
163 insulation divisions
170 bit lines
170a bit line contact plug
172,174 clearance wall
190 contact plungers
200 grooves
210 bit line trenches
210a plug trenches
D1 first direction
D2 second direction
D3 third direction
Specific embodiment
To enable the general technology person for being familiar with the technical field of the invention to be further understood that the present invention, hereafter spy is enumerated
Several preferred embodiments of the invention, and cooperate appended attached drawing, the constitution content that the present invention will be described in detail and to be reached
Effect.
Fig. 1 to Figure 11 is please referred to, illustrated is the formation side of semiconductor storage device in the preferred embodiment of the present invention
The step schematic diagram of method, wherein Fig. 1 is the upper schematic diagram of the semiconductor storage, and Fig. 2 to Fig. 7 and Fig. 9 to Figure 11 are should
Semiconductor storage is in each formation stages schematic side view, and Fig. 2 to Fig. 7 is to illustrate in Fig. 1 along the side view of hatching A-A '
It along the schematic side view of hatching B-B ', Figure 11 is then that side view in Fig. 1 along hatching C-C ' is shown that figure, Fig. 9 to Figure 10, which are in Fig. 1,
It is intended to.In the present embodiment, it is recorded to be simple, each attached drawing only shows the sample of the memory areas of the semiconductor storage
State, and omit the pattern of its peripheral region.
The semiconductor memory system, e.g. a dynamic random handle memory device, and it includes have an at least crystal
Tube elements (not being painted) and an at least capacitance structure (not being painted), to handle the minimum in memory array as stochastic and dynamic
Component units are simultaneously received from character line (word line, WL) 150 and the voltage signal of bit line (bit line, BL) 170.
The semiconductor storage includes a substrate 100, an e.g. silicon base, containing silicon base (such as SiC, SiGe) or silicon-coated insulated
(silicon-on-insulator, SOI) substrate etc., substrate 100 are formed with multiple active regions (active area, AA) 101,
It is to extend in parallel to each other along a first direction D1, as shown in Figure 1.And it is then also formed in substrate 100 multiple embedded
Grid (is not illustrated in Fig. 1), and can be used as embedded character line (buried word line, BWL) 150.Each character line 150
It is to extend in parallel to each other along a second direction D2, and across first direction D1.
On the other hand, it is then formed with multiple bit lines 170 in substrate 100, is in parallel to each other along a third direction D3
Extend, and simultaneously across active region 101 and character line 150.That is, third direction D3 be different from first direction D1 with
Second direction D2, and be preferably vertical with second direction D2 and be not orthogonal to first direction D1, as shown in Figure 1.Bit line 170 with
It is the bit line contact plug (bit line contact, BLC) by being formed in 170 lower section of part bit line between character line 150
170a is to electrically couple to the source/drain region (not being painted) of the respectively transistor unit.
The semiconductor storage can be formed using following steps, it is not limited to this.Firstly, as shown in Fig. 2, in base
An at least shallow trench isolation (shallow trench isolation, STI) 102 is formed in bottom 100, in the non-shape of substrate 100
Each active region 101 is defined at the part of shallow trench isolation 102.Then, a mask layer 130 is formed in substrate 100.Come in detail
It says, mask layer preferably has a composite construction, e.g. the first mask layer 131 comprising being sequentially stacked on 100 surface of substrate
One nitrogenous layer in this way/oxygenous layer etc., the second mask layer 133 are, for example, silicon monoxide (SiO2) layer, with third mask layer 135 for example
It is a silicon nitride (SiN) layer, as shown in Figure 3.In one embodiment, the first mask layer 131 may be selected to utilize the production such as thermal oxide
Technique is passed through nitrogen/oxygen to be formed, and then carries out deposition manufacture craft, come sequentially form 133 layers of the second mask layer with
Third mask layer 135, but not limited to this.In another embodiment, it also may be selected to omit third mask layer 135, and formed only
Mask layer (not being painted) with double-layer structure.
Then, the character line 150 being located in substrate 100 is formed.Firstly, form multiple grooves 200, make each groove 200 that
This is parallel and extends towards second direction D2.It is noted that groove 200 is simultaneously formed in mask layer 130 and substrate 100,
And it can be through mask layer 130 and a part of substrate 100, as shown in Figure 4.Then, it is sequentially formed in each groove 200 and fills up groove
The embedded character line 150 of 200 lower half and the insulating layer 160 for filling up 200 upper half of groove.Specifically, ditch is being formed
After slot 200, first sequentially form can 200 overall surface of covering groove a dielectric layer (not being painted), such as it is exhausted comprising silica etc.
Edge material (is not painted) with a barrier layer, such as comprising titanium/titanium nitride (Ti/TiN) layer, is subsequently formed and is filled up the one of groove 200
Conductive layer (is not painted), such as includes the low-resistances matter metal materials such as tungsten (W), aluminium (Al) or copper (Cu).Later, an etch-back is carried out
Manufacture craft forms the gate dielectric 151, barrier layer 153 and grid 157 for only filling up 200 lower half of groove, to collectively form
Character line 150 as shown in Figure 1.It is noted that character line 150 is formed entirely in substrate 100, and therefore, top surface meeting
Significantly lower than the top surface of substrate 100, as shown in Figure 5.And the insulating layer 160 being subsequently formed then fills up groove 200, wherein absolutely
A part of edge layer 160 is located in substrate 100, and another part is then further stretched on 100 surface of substrate, and and mask layer
130 top surface flushes.
Then, an etching process is carried out, to form multiple bit line trenches 210, each bit line trenches in mask layer 130
210 are parallel to each other and extend towards third direction D3.Due to bit line trenches 210 extending direction (third direction D3) with it is aforementioned
The extending direction (second direction D2) of groove 200 formed in manufacture craft intersects vertically, therefore, is carrying out the etching system
When making technique, the mask layer 130 of a part and the insulating layer 160 of a part need to be removed simultaneously, to form bit line trenches 210, such as
Shown in Fig. 6.Wherein, when removing mask layer 130, only third mask layer 135 can be removed with the second mask layer 133, so that
Underlying first mask layer 131 can be exposed from bit line trenches 210.It is noted that when removing insulating layer 160,
The part for being stretched on 100 surface of substrate, that is, not eating thrown insulating layer 160 are only removed, retains insulating layer 160 and is located at substrate
The part in 100, and as a cap rock 161.Then, another etching process is carried out, is further removed from bit line trenches
First mask layer 131 of 210 parts exposed, the cap rock 161 of a part and below between wantonly two adjacent character lines 150
Part active region 101 forms plug trenches 210a.Therefore plug trenches 210a is preferably formed in wantonly two adjacent character lines 150
Between, and the substrate 100 of a part is exposed, as shown in Figure 6.
Continuously form the bit line 170 for filling up each bit line trenches 210.In the present embodiment, bit line 170 can include at least sequentially
It is, for example, titanium/nitrogen that a conductor layer (not being painted) in filling bit line trenches 210, which is, for example, polysilicon etc., a barrier layer (not being painted),
Change titanium etc. and a metal layer (not being painted) low-resistance matter metal such as tungsten or copper (Cu), and the conductor layer of a part can be simultaneously
It inserts in each plug trenches 210a, and bit line contact plug (bit line contact, BLC) 170a can be formed, such as Fig. 7 institute
Show.In other words, each bit line contact plug 170a is formed in the lower section of bit line 170, and with the conductor layer of bit line 170 one at
Type.It is the first mask layer 131 and character line by being retained on 100 surface of substrate between each bit line 170 and character line 150
150 top cap rock 161 and it is mutually isolated.Also, each bit line 170 can be further electrically connected to by bit line contact plug 170a
Respectively the source/drain region of the transistor unit (is not painted, is the active region 101 between wantonly two adjacent character lines 150
On).
At this point, character line 150 in a second direction d 2 on the part Chong Die with bit line 170, be by cap rock 161 therewith every
From.In other words, after aforementioned etching process, a battlement shape structure can be presented in insulating layer 160 on the whole, as shown in Figure 8.
Each insulating layer 160 only maintains the height flushed with 100 top surface of substrate in the part Chong Die with bit line 170, and its not with bit line 170
Part between the part of overlapping, that is, two adjacent bit lines 170 is then to flush with the top surface of mask layer 130, makes each insulating layer
160 have multiple insulation divisions 163 for protruding from 100 top surface of substrate between two adjacent bit lines 170.
In addition, it should be noted that, it is to be formed before bit line 170 in each bit line trenches 210, first with a deposition and can returns
Etching process forms a clearance wall 172 on the side wall of each bit line trenches 210, and being, for example, includes the insulation such as silica
Material, as shown in figure 9, wherein Fig. 9 is the schematic side view in Fig. 1 along hatching B-B '.Then, it is just formed and fills up every duct
The bit line 170 of slot 210.In the case, clearance wall 172 can be used as an insulation barrier (in a second direction d 2), each to be isolated
Bit line 170 and the contact plunger being subsequently formed.
It is subsequent, then carry out the manufacture craft of contact plunger 190.It is to carry out an etching process, removes completely residue
Mask layer 130 and form multiple contact holes (not being painted), make a part substrate 100 can go out from the contact holes exposing.In detail
For, after defining character line 150 and bit line 170, the only insulation division 163 and two bit lines above two character lines 150
Also there are mask layers 130 for position between 170, and the contact can be formed in a self-aligned manner by removing completely mask layer 130
Hole.The contact hole can form close to each bit line 170 and the insulation division and obtain biggish manufacture craft nargin as a result,
(process window).Then, it can be formed and fill up the contact plunger 190 of the contact hole and be similarly figure as shown in Figure 10
Along the schematic side view of hatching B-B ' in 1.In the present embodiment, contact plunger 190 can be by being formed directly into 100 table of substrate
One metal silicide layer (silicide layer, be not painted) in face and another source/drain for being electrically connected to the transistor unit
Polar region (is not painted), and can be used as a memory node (storage node contact, SNC).
The semiconductor storage in first preferred embodiment of the invention is completed as a result,.The semiconductor storage
Though cap rock 161 set by 150 top of character line is entirely located in substrate 100 (top surface of cap rock 161 can be with 100 top surface of substrate
Flush), each cap rock 161 can also have the several insulation divisions 163 for protruding from 100 top surface of substrate.Each insulation division 163 is to be located at
Between two adjacent bit lines 170 (in a second direction d 2), also, in a first direction on D1 (extending direction of active region 101), respectively
Insulation division 163 can be between each memory node (i.e. contact plunger 190) and each bit line 170, as shown in figure 11.Insulation division 163
Top surface flushed with each memory node 190 with the top surface of each bit line 170, and be higher than 100 top surface of substrate and bit line plugs 170a, because
And can be used as each memory node 190 and the isolation barrier of each bit line 170 in the first direction dl, it avoids that short circuit occurs.
Method according to the present embodiment is before the manufacture craft of bit line 170 and memory node 190, i.e., first with tool
There is certain thickness mask layer 130 to form insulating layer 160.Later, with defining groove 200 and position in mask layer 130
The manufacture crafts such as line trenches 210, insulating layer 160 can be then formed simultaneously only in substrate 100, and are located on character line 150
Cap rock 161, and 100 surface of substrate, and the insulation division 163 between two adjacent bit lines 170 are protruded from from cap rock 161.Cause
This, after memory node and each bit line 170 are formed, part of each insulation division 163 between memory node and each bit line 170,
It then can be used as isolation barrier between the two.In other words, using the method for the present embodiment, using depositing manufacture craft with along with
Insulation division 163 come the cap rock 161 formed on character line 150, and between each memory node and each bit line 170, and make
Cap rock 161 is integrally formed with insulation division 163 and includes identical material.As a result, can manufacture craft simplify under the premise of,
Before bit line 170 and memory node 190 are formed, i.e., the insulation division 163 that extended meeting falls between after setting in advance leads this partly
Body storage device can maintain certain element reliability.
However, this field person should can will readily appreciate that, the manufacture craft of stochastic and dynamic processing memory component of the invention
It may be reached with other means, however it is not limited to making step above-mentioned.It therefore, hereafter will be further directed to manufacture craft of the present invention
Other embodiments or change type be illustrated.And for simplify explanation, illustrate below mainly for each embodiment difference into
Row is described in detail, and no longer repeats to something in common.In addition, identical element is with identical in various embodiments of the present invention
Label is indicated, in favor of checking one against another between each embodiment.
It please refers to shown in Figure 12 to Figure 13, is painted the formation of semiconductor storage in second preferred embodiment of the invention
The step schematic diagram of method.In the present embodiment, leading portion step is generally identical as aforementioned first preferred embodiment, such as Fig. 1
To shown in Fig. 6, do not repeated in this.The manufacture craft of the present embodiment is with aforementioned first preferred embodiment main difference, this
Embodiment is directly formed the bit line 170 for filling up each bit line trenches 210.Also, it is etched manufacture craft subsequent and defines
After the contact hole, clearance wall 174 is formed on the side wall of the contact hole.Clearance wall 174 equally will form in bit line as a result,
On 170 side wall, as shown in figure 12.On the other hand, because the clearance wall of the present embodiment 174 is re-formed after the formation of bit line 170
In on its side wall, so that clearance wall 174 can be also formed simultaneously on the side wall of insulation division 163.Therefore, if from as shown in fig. 13 that
From the point of view of one top view, an enclosing square circle can be presented in clearance wall 174, can be surrounded on the four of the contact plunger 190 being subsequently formed
Week.
Generally, forming method of the invention is by defining rear extended meeting in advance with certain thickness mask layer
The insulation division being set between bit line and memory node, and keep the insulation division and the cap rock on character line integrally formed simultaneously
Include identical material.The cap rock that can deposit manufacture craft using same road to be formed on the character line as a result, Yi Jijie
The insulation division between the memory node and the bit line, and it is reliable to form tool element under the premise of manufacture craft simplifies
The semiconductor storage of degree.And utilize the obtained semiconductor storage of forming method of the invention, then absolutely using this
The setting of edge enables the semiconductor storage to maintain certain element efficiency.
The above description is only a preferred embodiment of the present invention, all equivalent changes done according to the claims in the present invention with repair
Decorations, should all belong to the scope of the present invention.
Claims (18)
1. a kind of semiconductor storage, it is characterised in that include:
Multiple active regions, those active regions are defined in a substrate；
Multiple grids are arranged in the substrate；
Multiple bit lines, setting is on this substrate；
Multiple bit line plugs are separately positioned on the lower section of part bit line；And
Multiple cap rocks are arranged on those grids, and respectively the cap rock includes the multiple insulation divisions for protruding from the substrate, those insulation divisions
Between the respectively bit line, and the top surface of those insulation divisions is higher than the top surface of those bit line plugs.
2. semiconductor storage according to claim 1, which is characterized in that the top surface of those insulation divisions and those
The top surface of bit line flushes.
3. semiconductor storage according to claim 1, which is characterized in that those bit lines extend on a direction, should
A little insulation divisions extend on an other direction, and the other direction is vertically and the direction.
4. semiconductor storage according to claim 1, which is characterized in that also include:
The multiple plugs being set in the substrate.
5. semiconductor storage according to claim 4, which is characterized in that those insulation divisions are set on a first direction
It sets between those plugs and those bit lines.
6. semiconductor storage according to claim 1, which is characterized in that also include:
Clearance wall is arranged in the respectively bit line two sides.
7. semiconductor storage according to claim 6, which is characterized in that the clearance wall is additionally arranged at the respectively insulation division
Two sides.
8. semiconductor storage according to claim 1, which is characterized in that also include:
Shallow trench isolation is set in the substrate, and the shallow trench isolation is around those active regions.
9. a kind of forming method of semiconductor storage, it is characterised in that include:
A shallow trench isolation is formed in a substrate, and multiple active regions are defined in the substrate；
A mask layer is formed on this substrate, which covers those active regions and those shallow trench isolations；
Multiple grooves are formed in the mask layer and the substrate；
Multiple grids are respectively formed in those grooves；
An insulating layer is formed on those grids, which fills up those grooves；
The mask layer of a part and the insulating layer of a part are removed, forms multiple bit line trenches, and formed and be respectively overlay in
Multiple cap rocks on those grids；And
Multiple bit lines are formed in those bit line trenches, wherein respectively the cap rock includes the multiple insulation divisions for protruding from the substrate, should
A little insulation divisions are between wantonly two adjacent bit lines.
10. the forming method of semiconductor storage according to claim 9, which is characterized in that also include:
Multiple plugs are formed on this substrate, wherein those insulation divisions are folded between those plugs and those bit lines.
11. the forming method of semiconductor storage according to claim 10, which is characterized in that also include:
Before forming those plugs, a clearance wall is formed.
12. the forming method of semiconductor storage according to claim 11, which is characterized in that the clearance wall is formed in
On the side wall of those bit line trenches.
13. the forming method of semiconductor storage according to claim 11, which is characterized in that the clearance wall is formed in
On the side wall of those bit lines.
14. the forming method of semiconductor storage according to claim 13, which is characterized in that form those plugs
Step also includes:
The mask layer is removed, to form multiple contact holes；And
Those plugs are formed in those contact holes.
15. the forming method of semiconductor storage according to claim 14, which is characterized in that the clearance wall is also set up
On the side wall of those contact holes.
16. the forming method of semiconductor storage according to claim 9, which is characterized in that those grooves, those masters
Dynamic area and those bit lines are respectively facing different directions extension.
17. the forming method of semiconductor storage according to claim 9, which is characterized in that also include:
The cap rock of a part and the substrate of a part are removed, to be respectively formed multiple plug ditches in those bit line trenches
Slot；And
Multiple bit line plugs are formed in those plug trenches.
18. the forming method of semiconductor storage according to claim 17, which is characterized in that those bit line plugs with
Those bit lines are integrally formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710384107.4A CN108962907A (en) | 2017-05-26 | 2017-05-26 | Semiconductor storage and its forming method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710384107.4A CN108962907A (en) | 2017-05-26 | 2017-05-26 | Semiconductor storage and its forming method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108962907A true CN108962907A (en) | 2018-12-07 |
Family
ID=64494205
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710384107.4A Pending CN108962907A (en) | 2017-05-26 | 2017-05-26 | Semiconductor storage and its forming method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108962907A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111640759A (en) * | 2020-06-11 | 2020-09-08 | 福建省晋华集成电路有限公司 | Semiconductor memory device and method of forming the same |
| CN113241346A (en) * | 2021-05-08 | 2021-08-10 | 福建省晋华集成电路有限公司 | Semiconductor device and method of forming the same |
| US20220359528A1 (en) * | 2021-05-08 | 2022-11-10 | Fujian Jinhua Integrated Circuit Co., Ltd. | Semiconductor device and fabricating method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101944507A (en) * | 2009-07-03 | 2011-01-12 | 海力士半导体有限公司 | Method for manufacturing buried gate using pre landing plug |
| CN102237335A (en) * | 2010-04-26 | 2011-11-09 | 海力士半导体有限公司 | Semiconductor device and method for manufacturinmg the same |
| US20140319645A1 (en) * | 2010-04-22 | 2014-10-30 | SK Hynix Inc. | Semiconductor device and method for manufacturing the same |
-
2017
- 2017-05-26 CN CN201710384107.4A patent/CN108962907A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101944507A (en) * | 2009-07-03 | 2011-01-12 | 海力士半导体有限公司 | Method for manufacturing buried gate using pre landing plug |
| US20140319645A1 (en) * | 2010-04-22 | 2014-10-30 | SK Hynix Inc. | Semiconductor device and method for manufacturing the same |
| CN102237335A (en) * | 2010-04-26 | 2011-11-09 | 海力士半导体有限公司 | Semiconductor device and method for manufacturinmg the same |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111640759A (en) * | 2020-06-11 | 2020-09-08 | 福建省晋华集成电路有限公司 | Semiconductor memory device and method of forming the same |
| CN113241346A (en) * | 2021-05-08 | 2021-08-10 | 福建省晋华集成电路有限公司 | Semiconductor device and method of forming the same |
| US20220359528A1 (en) * | 2021-05-08 | 2022-11-10 | Fujian Jinhua Integrated Circuit Co., Ltd. | Semiconductor device and fabricating method thereof |
| US11744062B2 (en) * | 2021-05-08 | 2023-08-29 | Fujian Jinhua Integrated Circuit Co., Ltd. | Semiconductor device having bit line comprising a plurality of pins extending toward the substrate |
| CN113241346B (en) * | 2021-05-08 | 2023-09-26 | 福建省晋华集成电路有限公司 | Semiconductor device and method of forming the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110634869B (en) | Memory array and method of manufacturing the same | |
| CN108389861B (en) | Semiconductor element and forming method thereof | |
| CN108573926B (en) | Semiconductor memory device and method of manufacturing the same | |
| KR101129922B1 (en) | Semiconductor device and method for forming the same | |
| US8691680B2 (en) | Method for fabricating memory device with buried digit lines and buried word lines | |
| TWI455250B (en) | Low parasitic capacitance contact and gate structure and process for dynamic random access memory | |
| JP2004526325A (en) | Processing of upper part of vertical gate processed to improve GC and CB of window frame | |
| CN108573971B (en) | Organization of semiconductor memory | |
| JPH10313100A (en) | Dram cell device and manufacture thereof | |
| US11770924B2 (en) | Semiconductor device | |
| CN108962907A (en) | Semiconductor storage and its forming method | |
| EP1717852A2 (en) | Manufacturing method for a trench capacitor for use in a semiconductor memory cell | |
| JP5697952B2 (en) | Semiconductor device, semiconductor device manufacturing method, and data processing system | |
| US9419001B1 (en) | Method for forming cell contact | |
| US10062700B2 (en) | Semiconductor storage device and manufacturing method thereof | |
| US7074689B2 (en) | Method for fabricating a trench capacitor having an insulation collar, which is electrically connected to a substrate on one side via a buried contact, in particular for a semiconductor memory cell | |
| CN113241346B (en) | Semiconductor device and method of forming the same | |
| CN109509751A (en) | Semiconductor structure and preparation method thereof with character line | |
| US8467220B2 (en) | DRAM device and manufacturing method thereof | |
| US5780337A (en) | Method of fabricating a bit line of a dynamic random access memory | |
| US20060079064A1 (en) | Fabrication method for a trench capacitor having an insulation collar which on one side is electrically connected to a substrate via a buried contact, in particular for a semiconductor memory cell, and corresponding trench capacitor | |
| US11930631B2 (en) | Semiconductor memory device and method of fabricating the same | |
| CN218920890U (en) | Semiconductor device with a semiconductor layer having a plurality of semiconductor layers | |
| CN108695324B (en) | Semiconductor element and preparation method thereof | |
| CN113764419B (en) | Semiconductor device and method for forming the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20181207 |
|
| WD01 | Invention patent application deemed withdrawn after publication |