KR20080087276A - Semiconductor device and method for fabricating the same - Google Patents

Abstract

A semiconductor device and a method for manufacturing the same are provided to prevent the attack of a gate dielectric due to an over-etching of a lower poly silicon by increasing the uniformity of a surface of tungsten deposited to lower sheet resistance. A poly silicon layer is formed on an upper portion of a substrate(201). An etch stop layer(205A) having an etch selectivity and tungsten are formed on the poly silicon layer. A tungsten layer is formed on the etch stop layer. A mask pattern(207) is formed on the tungsten layer. The tungsten layer is etched. The etch stop layer is etched. The poly silicon layer is etched. The etch stop layer is made of TiN. A thickness of the TiN is at least 30 Å to 100 Å. The TiN is deposited by one selected from a group consisting of PVD(Physical Vapor Deposition), CVD(Chemical Vapor Deposition), and ALD(Atomic Layer Deposition). The tungsten layer is formed by CVD or ALD, When the tungsten layer is etched, a fluorine based gas is used.

Description

Semiconductor device and its manufacturing method {SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME}

1 is a cross-sectional view showing a dual poly gate,

2 is a graph showing inversion capacitance of a dual polygate;

3 is a cross-sectional view showing a semiconductor device having a dual poly gate according to the prior art;

4 is a graph for comparing the sheet resistance according to the type of barrier metal,

5 is a TEM photograph showing uniformity after tungsten deposition according to the prior art;

6 is a cross-sectional view illustrating a semiconductor device in accordance with a preferred embodiment of the present invention;

7A to 7D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention;

8A to 8F are cross-sectional views illustrating a method of manufacturing a semiconductor device having a dual poly gate according to a preferred embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

201: substrate 202: gate insulating film

203A: Polysilicon Electrode 204A: Barrier Metal

205A: etch stop layer 206A: tungsten electrode

207: Mask Pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a semiconductor device having tungsten as a gate electrode and a manufacturing method thereof.

As the semiconductor devices are highly integrated, the pitch between gates is reduced in the process of processing a CMOS device using a silicon wafer. In the conventional CMOS device, a polysilicon film doped with n-type impurities is used as each gate electrode of the NMOS and PMOS devices. In this case, the NMOS device has a surface channel characteristic, whereas the PMOS device has a buried channel characteristic. However, when the width (half width) of the gate electrode is narrowed to 100 nm or less due to the buried channel characteristic of the PMOS device, there is a problem in that a short channel effect appears.

Accordingly, a dual gate structure has been proposed in which a gate electrode of a PMOS device is formed of a polysilicon layer doped with P-type impurities in a CMOS device process having a narrow gate channel length, so that the PMOS device has surface channel characteristics. . This double gate structure reduces the short channel effect.

1 is a cross-sectional view illustrating a general dual poly gate.

Referring to FIG. 1, a gate insulating film 12 is formed on a semiconductor substrate 11 in which NMOS and PMOS are defined, and an N-type polysilicon film doped with phosphorus (P) in each NMOS on the gate insulating film 12. (13b), P-type polysilicon film 13a doped with boron was formed in PMOS. Subsequently, metal electrodes (Xix) 14 were formed on each of the polysilicon films 13a and 13b.

Although the dual poly gate has the effect of reducing the short channel effect, the threshold voltage shift and fluctuation due to boron penetration into the channel region appear, and the interface between the gate insulating layer 12 and the polysilicon layers 13a and 13b is observed. There is a problem in that deterioration of device characteristics due to poly silicon depletion occurs.

The phenomenon due to boron penetration into the channel region can be reduced by nitriding the surface of the gate insulating film 12, but the polysilicon depletion phenomenon caused by the out diffusion of boron toward the metal electrode cannot be prevented.

2 is a graph comparing inversion capacitances of dual poly gates.

Referring to FIG. 2, an inversion capacitance of an N-type polysilicon electrode of an NMOS and a P-type polysilicon electrode of a PMOS may be compared. Looking at the graph, in the case of PMOS, since the boron is out-diffused to the metal electrode, the capacitance value of the PMOS is smaller than the capacitance value of the NMOS due to the polysilicon depletion phenomenon. This means that the capacitive equivalent thickness (CET) of the gate insulating film is increased. In the case of semiconductor devices having a gate-to-gate spacing of 100 nm or less, the threshold voltage change value becomes large, resulting in deterioration of device characteristics. .

In addition, tungsten is used instead of tungsten silicide to secure high-speed device characteristics of semiconductor devices. However, when tungsten is directly formed as a metal electrode on the polysilicon electrode, a volume expansion occurs due to siliconization during a subsequent thermal process, and a stress reaction occurs, thereby causing a diffusion barrier between the tungsten and the polysilicon electrode. Diffusion Barrier membrane is required.

3 is a cross-sectional view and a graph for comparing a semiconductor device having a dual poly gate according to the prior art. For convenience of description, only the PMOS region of the semiconductor device is illustrated in FIG. 3.

As shown in Fig. 3, a barrier metal and tungsten 26, which are a stack of a gate oxide film 22, a P-type polysilicon 23, Ti 24 and? N 25, on a semiconductor substrate 21 of a PMOS. This stacked dual poly gate is formed.

As described above, applying the barrier metal reduces the gate resistance and improves the polydepletion rate of the PMOS.

However, in the conventional method of forming tungsten, the grain size of tungsten is deposited because PVN (Physical Vapor Deposition) method is deposited on top of Ti as ＷN is used as the barrier metal. There is a problem that is formed small to increase the sheet resistance value. Since the increased width of the tungsten sheet resistance increases rapidly as the gate line width increases, there is a problem in that future devices that require a fine line width of less than 100 nm cannot be applied.

That is, as shown in FIG. 4, it can be seen that the sheet resistance increased by at least three times when the barrier structure of Ti and ＷN was formed of barrier metal, compared with the barrier metal of ＷSix and ＷN. have. At this time, the barrier metal in which Xix and XN are stacked is not used because of low sheet resistance but a problem in that the gate interface resistance is increased and the reliability of the gate oxide film is deteriorated.

In order to solve the above problems, when tungsten is formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD), the specific resistance of tungsten is lowered, but the uniformity of the deposition thickness is lowered compared to that formed using PVD. There is (see FIG. 5).

When the uniformity of the thickness of the deposited tungsten is reduced, the non-uniform surface of tungsten is transferred to the lower polysilicon as it is etched to form the subsequent gate pattern, and overetched to the gate oxide layer, thereby deteriorating device characteristics and yield. There is a problem.

The present invention has been proposed to solve the above problems of the prior art, a method of manufacturing a semiconductor device for preventing the deterioration of the characteristics and yield of the device in the etching process for the subsequent gate pattern formation by the non-uniformity of tungsten The purpose is to provide.

The semiconductor device according to the present invention includes a polysilicon electrode formed on the substrate, an etch stop layer formed on the polysilicon electrode, having an etch selectivity with tungsten, and a tungsten electrode formed on the etch stop layer. do.

In addition, the method of manufacturing a semiconductor device according to the present invention comprises the steps of forming a polysilicon layer on the substrate, forming an etch stop layer having an etch selectivity with tungsten on the polysilicon layer, on the etch stop layer Forming a tungsten layer, forming a mask pattern on the tungsten layer, etching the tungsten layer, etching the etch stop layer, and etching the polysilicon layer. do.

In addition, the method of manufacturing a semiconductor device having a dual poly gate according to the present invention includes forming a gate insulating film on a substrate having an NMOS region and a PMOS region, and forming an N-type polysilicon layer on the NMOS region on the gate insulating film. Forming a P-type polysilicon layer in the PMOS region, forming a barrier metal layer on the N-type and P-type polysilicon layers, and an etch stop layer having an etch selectivity with tungsten and an etching selectivity on the barrier metal layer Forming a tungsten layer on the etch stop layer, forming a mask pattern on the tungsten layer, etching the tungsten layer, etching the etch stop layer, the N-type and P It characterized in that it comprises the step of etching the type polysilicon layer.

In particular, the etch stop layer is TiN, the tungsten layer is characterized by etching with a fluorine-based gas, the etch stop layer with a chlorine-based gas.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

6 is a cross-sectional view illustrating a semiconductor device in accordance with a preferred embodiment of the present invention.

As shown in FIG. 6, a gate pattern in which a gate insulating film 102, a polysilicon electrode 103, a barrier metal 104, an etch stop layer 105, and a tungsten electrode 106 are stacked on a substrate 101. To form. Here, the gate insulating film 102 may be an oxide film, and the polysilicon electrode 103 may be a P-type polysilicon. In addition, the barrier metal 104 may have a stacked structure of Ti and ＷN, and the etch stop layer 105 may be a material having an etching selectivity with the tungsten electrode 106 but may be TiN.

As described above, a material having an etching selectivity with the tungsten electrode 106 as the etch stop layer 105, that is, TiN is formed to form a deposition thickness by chemical vapor deposition or atomic layer deposition. Even if a non-uniform tungsten electrode 106 is formed, the etching is stopped on the etch stop layer 105 after the tungsten electrode 106 is etched to form the gate pattern, so that the subsequent etching process may be performed with a uniform thickness.

Accordingly, the polysilicon electrode 103 is uniformly etched regardless of the non-uniformity of the tungsten electrode 106 while forming low resistivity tungsten (Low Resistance LW) having a low specific resistance, resulting from transient etching of the gate insulating film 102. The problem of deterioration of device characteristics and deterioration of yield can be prevented.

7A to 7D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

As shown in FIG. 7A, a gate insulating film 202 is formed on the substrate 201. Here, the substrate 201 may be a semiconductor substrate in which a DRAM process is performed, and the gate insulating film 202 may be an oxide film.

Next, a polysilicon layer 203 is formed on the gate insulating film 202. Here, the polysilicon layer 203 may be P-type polysilicon.

Next, a barrier metal (BM) 204 is formed on the polysilicon layer 203. Here, the barrier metal layer 204 serves as a diffusion barrier, that is, tungsten and polysilicon are in direct contact with each other to prevent a silicide reaction from occurring in a subsequent thermal process, thereby preventing a stress reaction due to volume expansion. Titanium) and 와 N (tungsten nitride film). Therefore, the Rc (contact resistance) and Rs (surface resistance) values of the gate can be simultaneously lowered.

Subsequently, an etch stop layer 205 is formed on the barrier metal layer 204. Here, the etch stop layer 205 may be formed of a material having an etching selectivity with tungsten, but may be formed of TiN (titanium nitride). At this time, TiN is selected from the group of physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD). In any one deposition method, TiCl ₃ may be formed as a source gas.

TiN is formed to a thickness of at least 30 GPa or more (30 GPa to 100 GPa) and formed into a crystal phase. Therefore, the internal nitrogen (N) is not decomposed during the subsequent thermal process, and thus does not affect the interfacial resistance and the poly depletion effect of the gate.

Next, a tungsten layer 206 is formed on the etch stop layer 205. Here, the tungsten layer 206 may be formed by CVD or ALD to lower the specific resistance of tungsten itself. That is, a large grain of bulk tungsten is grown by forming a seed layer (amorphous state) by B ₂ H ₆ , ＷF ₆ and NH ₃ treatment by CVD or ALD. By doing so, the sheet resistance value of tungsten can be lowered regardless of the kind of lower barrier material. Such tungsten is called low resistance tungsten (LRsten).

As shown in FIG. 7B, a mask pattern 207 is formed on the tungsten layer 206. The mask pattern 207 may be formed by coating a photoresist on the tungsten layer 206 and patterning the gate pattern region to be defined by exposure and development.

Next, the tungsten layer 206 is etched using the mask pattern 207. In this case, since the tungsten layer 206 is formed of FF ₆ as the source gas, the tungsten layer 206 may be etched using the fluorine (F) -based gas. In this case, since the fluorine-based gas for etching the tungsten layer 206 has an etching selectivity with TiN, the etching stops at the top of the etching stop layer 205 having a different selectivity after etching the tungsten layer 206.

Therefore, the etching stop layer 205 opened after etching is completed regardless of the surface unevenness of the tungsten layer 206 has a uniform surface.

Hereinafter, the tungsten layer 206 on which the etching is completed is referred to as 'tungsten electrode 206A'.

As shown in FIG. 7C, the etch stop layer 205 and the barrier metal layer 204 are etched. Here, the etch stop layer 205 and the barrier metal layer 204 may be etched using chlorine (Cl) -based gas.

The etch stop layer 205 and the barrier metal layer 204 have a uniform surface in FIG. 7B to complete the etch while remaining the polysilicon layer 203 at a uniform thickness by the remaining etch stop layer 205. Can be.

Hereinafter, the etch stop layer 205 where the etching is completed is referred to as an etch stop layer 205A and the barrier metal layer 204 as a barrier metal 204A.

As shown in FIG. 7D, the polysilicon layer 203 and the gate insulating layer 202 are etched to form a gate pattern. When the etching is completed, all of the mask patterns 207 may be removed or removed using an oxygen strip.

In this case, since the polysilicon layer 203 and the gate insulating film 202 have a uniform surface and are etched, the unnecessary characteristics of the gate insulating film 202 may not be excessively etched, and thus the device characteristics and the yield may be reduced. Can be.

Accordingly, the gate pattern has a structure in which a gate insulating film 202A, a polysilicon electrode 203A, a barrier metal 204A, an etch stop layer 205A, and a tungsten electrode 206A are stacked.

8A to 8F are cross-sectional views illustrating a method of manufacturing a semiconductor device having a dual poly gate according to a preferred embodiment of the present invention.

As shown in FIG. 8A, a gate insulating film 302 is formed on a semiconductor substrate 301 having an NMOS region and a PMOS region. Here, the gate insulating film 302 may be an oxide film.

Next, a polysilicon layer 303 is formed on the gate insulating film 302. Here, the polysilicon layer 303 may be undoped polysilicon or N-type polysilicon.

Subsequently, a first photoresist film pattern 304 is formed on the polysilicon layer 303 in the PMOS region. Here, the first photoresist layer pattern 304 may be formed by coating a photoresist layer on the polysilicon layer 303 and patterning the polysilicon layer 303 of the NMOS region to open by exposure and development.

Subsequently, an N-type impurity is ion-implanted on the polysilicon layer 303 in the NMOS region to form an N-type polysilicon layer 303A. Here, the N-type impurity may be phosphorus (Ph) or arsenic (As).

As shown in FIG. 8B, the first photoresist pattern 304 is removed. Here, the first photoresist pattern 304 may be removed with an oxygen strip.

Subsequently, a second photosensitive film pattern 305 is formed on the N-type polysilicon layer 303A. Here, the second photoresist pattern 305 is coated on the N-type polysilicon layer 303A and the polysilicon layer 303, and then patterned to open the polysilicon layer 303 of the PMOS region by exposure and development. Can be formed.

Subsequently, P-type impurities are ion-implanted on the polysilicon layer 303 in the PMOS region to form the P-type polysilicon layer 303B. Here, the P-type impurity may be boron (B).

As shown in FIG. 8C, the second photoresist layer pattern 305 is removed. Here, the second photoresist pattern 305 may be removed with an oxygen strip in the same manner as the first photoresist pattern 304.

Next, the barrier metal layer 306 is formed on the N-type and P-type polysilicon layers 303A and 303B. Here, the barrier metal layer 306 serves as a diffusion barrier, that is, tungsten and polysilicon are in direct contact with each other to prevent a silicide reaction from occurring in a subsequent thermal process, thereby preventing a stress reaction due to volume expansion. Titanium) and 와 N (tungsten nitride film). Therefore, the Rc (contact resistance) and Rs (surface resistance) values of the gate can be simultaneously lowered.

Subsequently, an etch stop layer 307 is formed on the barrier metal layer 306. Here, the etch stop layer 307 may be formed of a material having an etching selectivity with tungsten, but may be formed of TiN (titanium nitride). At this time, TiN is any one selected from the group of physical vapor deposition (Physical Vapor Depositon, hereinafter referred to as PVD), chemical vapor deposition (Chemical Vapor Deposition, CVD) and atomic layer deposition (ALD). In one deposition method, TiCl ₃ may be formed as a source gas.

Further, TiN is formed to a thickness of at least 30 GPa or more and formed into a crystal phase. Therefore, the internal nitrogen (N) is not decomposed during the subsequent thermal process, and thus does not affect the interfacial resistance and the poly depletion effect of the gate.

Next, a tungsten layer 308 is formed on the etch stop layer 307. Here, the tungsten layer 308 is formed by CVD or ALD to lower the specific resistance of tungsten itself. That is, a large grain of bulk tungsten is grown by forming a seed layer (amorphous state) by B ₂ H ₆ , ＷF ₆ and NH ₃ treatment by CVD or ALD. By doing so, the sheet resistance value of tungsten can be lowered regardless of the kind of lower barrier material. Such tungsten is called low resistance tungsten (LRsten).

As shown in FIG. 8D, a mask pattern 309 is formed on the tungsten layer 308. The mask pattern 309 may be formed by coating a photoresist on the tungsten layer 308 and patterning the gate pattern region to be defined by exposure and development.

Next, the tungsten layer 308 is etched with the mask pattern 309. In this case, since the tungsten layer 308 is formed of FF ₆ as the source gas, the tungsten layer 308 may be etched using the fluorine (F) -based gas. In this case, since the fluorine-based gas for etching the tungsten layer 308 has an etching selectivity with TiN, the etching stops at the top of the etching stop layer 307 having a different selectivity after etching the tungsten layer 308.

Therefore, regardless of the surface unevenness of the tungsten layer 308, the etching stop layer 307 opened after the etching is completed has a uniform surface.

Hereinafter, the tungsten layer 308 on which the etching is completed is referred to as 'tungsten electrode 308A'.

As shown in FIG. 8E, the etch stop layer 307 and the barrier metal layer 306 are etched. Here, the etch stop layer 307 and the barrier metal layer 306 may be etched using chlorine (Cl) -based gas.

The etch stop layer 307 and the barrier metal layer 308 also have a uniform surface and have a uniform thickness of the N-type and P-type polysilicon layers 303A and 303B by the remaining etch stop layer 307. The etching can be completed while remaining.

Hereinafter, the etch stop layer 307 having completed etching is referred to as an etch stop layer 307A and a barrier metal layer 305 as a barrier metal 305A.

As shown in FIG. 8F, the N-type and P-type polysilicon layers 303A and 303B and the gate insulating layer 302 are etched to form a gate pattern. When the etching is completed, all of the mask patterns 309 may be removed or may be removed using an oxygen strip.

At this time, since the N-type and P-type polysilicon layers 303A and 303B and the gate insulating layer 302 have a uniform surface and are etched, the unnecessary characteristics of the gate insulating layer 302 are not excessively etched, thereby degrading device characteristics and yield. This deterioration problem can be prevented.

Therefore, the gate pattern of the NMOS region has a structure in which a gate insulating film 302A, an N-type polysilicon electrode 303C, a barrier metal 306A, an etch stop layer 307A, and a tungsten electrode 308A are stacked, and a gate of a PMOS region. The pattern is formed by stacking a P-type polysilicon electrode 303D, a barrier metal 306A, an etch stop layer 307A, and a tungsten electrode 308A.

The present invention forms TiN as an etch stop layer between the barrier metal and tungsten. Therefore, even if tungsten with irregular surface is formed by CVD or ALD process to form tungsten with low resistivity value, the tungsten surface is processed after the etching process of tungsten is completed in the etch stop layer during the gate etching process. By etching the lower layer having a uniform thickness irrespective of the non-uniformity, the surface unevenness of tungsten is transferred as it is, thereby causing polysilicon to abnormally etch and thereby fundamentally prevent the gate insulating film from being attacked.

In addition, since the etch stop layer is made of TiN and is a metal and a crystalline phase, nitrogen (N) is not decomposed during the subsequent thermal process, so that the etch stop layer does not affect interfacial resistance and polydepletion.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention, the surface of the tungsten deposited to reduce the sheet resistance is irregularly formed to fundamentally prevent attack of the gate insulating layer due to abnormal excessive etching of the lower polysilicon during the gate etching process, thereby improving device characteristics and yields. There is an effect to improve. In addition, since the etch stop layer to be inserted is TiN metal and crystal phase, nitrogen (N) is not decomposed during the subsequent thermal process, and thus there is no effect of interfacial resistance and polydepletion.

Claims (25)

A polysilicon electrode formed on the substrate; An etch stop layer formed on the polysilicon electrode and having an etch selectivity with tungsten; And Tungsten electrode formed on the etch stop layer Semiconductor device comprising a. The method of claim 1, The etch stop layer is a semiconductor device, characterized in that the TiN. The method of claim 1, The semiconductor device further comprises a barrier metal between the polysilicon electrode and the etch stop layer. The method of claim 3, The barrier metal is a semiconductor device, characterized in that the laminated structure of Ti and ＷN. Forming a polysilicon layer on the substrate; Forming an etch stop layer having an etch selectivity with tungsten on the polysilicon layer; Forming a tungsten layer on the etch stop layer; Forming a mask pattern on the tungsten layer; Etching the tungsten layer; Etching the etch stop layer; And Etching the polysilicon layer Method of manufacturing a semiconductor device comprising a. The method of claim 5, The etching stop layer is a semiconductor device manufacturing method, characterized in that formed by TiN. The method of claim 6, Wherein said TiN is formed to a thickness of at least 30 GPa-100 GPa. The method of claim 7, wherein The TiN manufacturing method of the semiconductor device, characterized in that formed by any one of the deposition method selected from the group of Physical Vapor Deposition (PVD), CVD and ALD. The method of claim 5, The tungsten layer is a method of manufacturing a semiconductor device, characterized in that formed by CVD (Chemical Vapor Deposition) or ALD (Atomic Layer Deposition) method. The method of claim 9, The tungsten layer is formed by forming and growing a seed layer by B ₂ H ₆ , ＷF ₆ and NH ₃ treatment. The method of claim 5, Etching the tungsten layer, A method of manufacturing a semiconductor device, characterized in that the fluorine-based gas is used. The method according to claim 5 or 6, Etching the etch stop layer, A method of manufacturing a semiconductor device, characterized in that the chlorine-based gas is used. The method of claim 5, Before forming the etch stop layer, A method of manufacturing a semiconductor device, further comprising the step of forming a barrier metal layer. The method of claim 13, The barrier metal layer is a semiconductor device manufacturing method characterized in that the laminated structure of Ti and ＷN. Forming a gate insulating film over the substrate having an NMOS region and a PMOS region; Forming an N-type polysilicon layer in the NMOS region and a P-type polysilicon layer in the PMOS region on the gate insulating film; Forming a barrier metal layer on the N-type and P-type polysilicon layers; Forming an etch stop layer having tungsten and an etch selectivity on the barrier metal layer; Forming a tungsten layer on the etch stop layer; Forming a mask pattern on the tungsten layer; Etching the tungsten layer; Etching the etch stop layer; And Etching the N-type and P-type polysilicon layers Method of manufacturing a semiconductor device having a dual poly gate comprising a. The method of claim 15, The etch stop layer is a semiconductor device manufacturing method having a dual poly gate, characterized in that formed with TiN. The method of claim 16, And said TiN is formed to have a thickness of at least 30 kPa to 100 kPa. The method of claim 17, The TiN is a method of manufacturing a semiconductor device having a dual poly gate, characterized in that formed by any one of the deposition method selected from the group of physical vapor deposition (PVD), CVD and ALD. The method of claim 15, The tungsten layer is a semiconductor device manufacturing method having a dual poly gate, characterized in that formed by CVD (Chemical Vapor Deposition) or ALD (Atomic Layer Deposition) method. The method of claim 19, The method of producing a semiconductor device having a dual gate poly that the tungsten layer is characterized in that it is formed by growing and forming a seed layer (Seed Layer) due to the B ₂ H _6, WF ₆ and NH ₃ treatment. The method of claim 15, Etching the tungsten layer, A method for manufacturing a semiconductor device having a dual poly gate, characterized in that the fluorine-based gas is used. The method according to claim 15 or 16, Etching the etch stop layer, A method of manufacturing a semiconductor device having a dual poly gate, characterized in that the chlorine-based gas is used. The method of claim 15, The barrier metal layer is a semiconductor device manufacturing method having a dual poly gate, characterized in that the laminated structure of Ti and ＷN. The method of claim 15, Forming the N-type and P-type polysilicon layers, Forming a polysilicon layer on the gate insulating film; Forming a first photoresist pattern on the polysilicon layer of the PMOS region; Implanting N-type impurities into the polysilicon layer of the NMOS region; Removing the first photoresist pattern; Forming a second photoresist pattern on the polysilicon layer of the NMOS region; Implanting P-type impurities into the polysilicon layer of the PMOS region; And Removing the second photoresist pattern Method of manufacturing a semiconductor device having a dual poly gate, characterized in that it comprises a. The method of claim 24, The N-type impurity is phosphorus (Ph) or arsenic (As), and the P-type impurity is boron (B).

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