KR20080089745A - Method for fabricating semiconductor device - Google Patents

Abstract

A method for manufacturing a semiconductor device is provided to improve device characteristics and to increase a yield by forming a tungsten layer having low resistivity and a uniform surface. A polysilicon layer(103) is formed on a substrate(101). A tungsten layer(105A) is formed on the polysilicon layer. A planarization process is performed to planarize the tungsten layer. A mask pattern is formed on the tungsten layer. A first etch process is performed to etch the tungsten layer. A second etch process is performed to etch the polysilicon layer. The tungsten layer is formed by using a CVD(Chemical Vapor Deposition) method or an ALD(Atomic Layer Deposition) method.

Description

Manufacturing method of semiconductor device {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

1 is a cross-sectional view showing a dual poly gate,

2 is a graph showing inversion capacitance of a dual polygate;

3 is a cross-sectional view showing a semiconductor device having a dual poly gate according to the prior art;

4 is a graph for comparing the sheet resistance according to the type of barrier metal,

5 is a TEM photograph showing uniformity after tungsten deposition according to the prior art;

6A through 6D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention;

7A to 7F are cross-sectional views illustrating a method of manufacturing a semiconductor device having a dual poly gate according to a preferred embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

101: substrate

102: gate insulating film

103A: Polysilicon Electrode

104A: Barrier Metal

105B: Tungsten Electrode

106: mask pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a semiconductor device having low resistance tungsten as a gate electrode and a method of manufacturing the same.

As the semiconductor devices are highly integrated, the pitch between gates is reduced in the process of processing a CMOS device using a silicon wafer. In the conventional CMOS device, a polysilicon film doped with n-type impurities is used as each gate electrode of the NMOS and PMOS devices. In this case, the NMOS device has a surface channel characteristic, whereas the PMOS device has a buried channel characteristic. However, when the width (half width) of the gate electrode is narrowed to 100 nm or less due to the buried channel characteristic of the PMOS device, there is a problem in that a short channel effect appears.

Accordingly, a dual gate structure has been proposed in which a gate electrode of a PMOS device is formed of a polysilicon layer doped with P-type impurities in a CMOS device process having a narrow gate channel length, so that the PMOS device has surface channel characteristics. . Such a double gate structure has an effect of reducing the short channel effect.

1 is a cross-sectional view illustrating a general dual poly gate.

Referring to FIG. 1, a gate insulating film 12 is formed on a semiconductor substrate 11 in which NMOS and PMOS are defined, and an N-type polysilicon film doped with phosphorus (P) in each NMOS on the gate insulating film 12. (13b), P-type polysilicon film 13a doped with boron was formed in PMOS. Subsequently, metal electrodes (Xix) 14 were formed on each of the polysilicon films 13a and 13b.

Although the dual poly gate has the effect of reducing the short channel effect, the threshold voltage shift and fluctuation due to boron penetration into the channel region appear, and the interface between the gate insulating layer 12 and the polysilicon layers 13a and 13b is observed. There is a problem in that deterioration of device characteristics due to poly silicon depletion occurs.

The phenomenon due to boron penetration into the channel region can be reduced by nitriding the surface of the gate insulating film 12, but the polysilicon depletion phenomenon caused by the out diffusion of boron toward the metal electrode cannot be prevented.

2 is a graph comparing inversion capacitances of dual poly gates.

Referring to FIG. 2, an inversion capacitance of an N-type polysilicon electrode of an NMOS and a P-type polysilicon electrode of a PMOS may be compared. Looking at the graph, in the case of PMOS, since the boron is out-diffused to the metal electrode, the capacitance value of the PMOS is smaller than the capacitance value of the NMOS due to the polysilicon depletion phenomenon. This means that the capacitive equivalent thickness (CET) of the gate insulating film is increased. In the case of semiconductor devices having a gate-to-gate spacing of 100 nm or less, the threshold voltage change value becomes large, resulting in deterioration of device characteristics. .

In addition, tungsten is used instead of tungsten silicide to secure high-speed device characteristics of semiconductor devices. However, when tungsten is directly formed as a metal electrode on the polysilicon electrode, a volume expansion occurs due to siliconization during a subsequent thermal process, and a stress reaction occurs, thereby causing a diffusion barrier between the tungsten and the polysilicon electrode. Diffusion Barrier) film is formed.

3 is a cross-sectional view and a graph for comparing a semiconductor device having a dual poly gate according to the prior art. For convenience of description, only the PMOS region of the semiconductor device is illustrated in FIG. 3.

As shown in Fig. 3, a barrier metal and tungsten 26, which are a stack of a gate oxide film 22, a P-type polysilicon 23, Ti 24 and? N 25, on a semiconductor substrate 21 of a PMOS. This stacked dual poly gate is formed.

As described above, applying the barrier metal reduces the gate resistance and improves the polydepletion rate of the PMOS.

However, in the conventional method of forming tungsten, the grain size of tungsten is deposited because PVN (Physical Vapor Deposition) method is deposited on top of Ti as ＷN is used as the barrier metal. There is a problem that is formed small to increase the sheet resistance value. Since the increased width of the tungsten sheet resistance increases rapidly as the gate line width increases, there is a problem in that future devices that require a fine line width of less than 100 nm cannot be applied.

That is, as shown in FIG. 4, it can be seen that the sheet resistance increased by at least three times when the barrier structure of Ti and ＷN was formed of the barrier metal, compared with the barrier metal of the ＷSix and ＷN laminated structure. have. At this time, the barrier metal in which Xix and XN are stacked is not used because of low sheet resistance but a problem in that the gate interface resistance is increased and the reliability of the gate oxide film is deteriorated.

In order to solve the above problems, when tungsten is formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD), the specific resistance of tungsten is lowered, but the uniformity of the deposition thickness is lowered compared to that formed using PVD. There is (see FIG. 5).

When the uniformity of the thickness of the deposited tungsten decreases, the non-uniform surface of tungsten is transferred to the lower polysilicon and the gate oxide layer as it is formed during the etching to form the subsequent gate pattern, and the substrate is damaged by the over etching during the gate oxide layer etching. There is a problem of deterioration in characteristics and yield of the device.

The present invention has been proposed to solve the above problems of the prior art, the surface of the tungsten is not uniform during the formation of the low resistance tungsten prevents the substrate from being attacked when forming the gate pattern to lower the characteristics and yield of the device It is an object of the present invention to provide a method for manufacturing a semiconductor device.

The method of manufacturing a semiconductor device according to the present invention for achieving the above object comprises the steps of forming a polysilicon layer on the substrate, forming a tungsten layer on the polysilicon layer, planarizing the tungsten layer, the tungsten Forming a mask pattern on the layer, etching the tungsten layer, and etching the polysilicon layer.

In addition, the method of manufacturing a semiconductor device having a dual poly gate according to the present invention is to form an N-type polysilicon layer in the NMOS region and a P-type polysilicon layer in the PMOS region, respectively, on the substrate having the NMOS region and the PMOS region. Forming a barrier metal layer on the N-type and P-type polysilicon layers; forming a tungsten layer on the barrier metal layer; planarizing the tungsten layer; and forming a mask pattern on the tungsten layer. Forming, etching the tungsten layer, and etching the N-type and P-type polysilicon layer.

In particular, the planarization process may be carried out by a chemical mechanical polishing process.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

6A to 6D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

As shown in FIG. 6A, a gate insulating film 102 is formed on the substrate 101. Herein, the substrate 101 may be a semiconductor substrate in which a DRAM process is performed, and the gate insulating layer 102 may be an oxide layer.

Next, a polysilicon layer 103 is formed on the gate insulating film 102. Here, the polysilicon layer 103 may be P-type polysilicon.

Next, a barrier metal layer (BM) 104 is formed on the polysilicon layer 103. The barrier metal layer 104 serves as a diffusion barrier and may have a stacked structure of Ti (titanium) and ＷN (tungsten nitride). That is, the tungsten formed of the metal layer and polysilicon are in direct contact with each other, so that a silicide reaction occurs in a subsequent thermal process, thereby preventing a stress reaction due to volume expansion, thereby lowering the Rc (contact resistance) of the gate due to stress. In addition, when the polysilicon layer 103 is doped polysilicon, impurities may be prevented from being out-diffused to the upper layer.

Next, a tungsten layer 105 is formed on the barrier metal layer 104. Here, the tungsten layer 105 may be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD) in order to lower the specific resistance of tungsten itself. That is, a large grain of bulk tungsten is grown by forming a seed layer (amorphous state) by B ₂ H ₆ , ＷF ₆ and NH ₃ treatment by CVD or ALD. By doing so, the sheet resistance value (Rs) of tungsten can be lowered regardless of the type of barrier material underneath. Such tungsten is called low resistance tungsten (LRsten).

As shown in FIG. 6B, the tungsten layer 105 is planarized. Here, the planarization may be carried out by a chemical mechanical polishing process.

By planarization, the tungsten layer 105 becomes a tungsten layer 105A having a uniform thickness on the surface.

As shown in FIG. 6C, a mask pattern 106 is formed on the tungsten layer 105A. The mask pattern 106 may be formed by coating a photoresist on the tungsten layer 105A and patterning the gate pattern region to be defined by exposure and development.

As shown in FIG. 6D, the tungsten layer 105A is etched using the mask pattern 106. The tungsten layer 105A is etched using fluorine (F) -based gas because the tungsten layer 105A is formed of? F ₆ as the source gas.

The tungsten layer 105 having an uneven surface by growing with bulk tungsten to form a low resistive tungsten (LRW) is changed to a uniform thickness during patterning by changing the tungsten layer 105A to a uniform surface through the planarization process in FIG. 6B. Etching is possible. That is, the uniform surface of the tungsten layer 105A is transferred to the lower barrier metal layer 104 so that the barrier metal layer 104 also has a uniform surface thickness.

Hereinafter, the tungsten layer 105A on which the etching is completed is referred to as 'tungsten electrode 105B'.

Next, the barrier metal layer 104 is etched. Here, the barrier metal layer 104 may be etched using chlorine (Cl) -based gas.

The barrier metal layer 104 on which the etching is completed is referred to as 'barrier metal 104A'.

Next, the polysilicon layer 103 and the gate insulating film 102 are etched. Since the planarized tungsten layer 105A is formed in advance before the formation of the tungsten electrode 105B, a uniform surface is transferred to the lower layer so that the polysilicon layer 103 and the gate insulating layer 102 may have an even surface and may be etched. . Therefore, when the etching process is completed to remove the residue after the etching to the gate insulating film 102, the substrate 101 is attacked to prevent the problem of deterioration of device characteristics and yield.

When the etching is completed, all of the mask patterns 106 may be removed or removed using an oxygen strip.

The gate pattern is formed by stacking a gate insulating film 102A, a polysilicon electrode 103A, a barrier metal 104A, and a tungsten electrode 105B.

7A to 7F are cross-sectional views illustrating a method of manufacturing a semiconductor device having a dual poly gate according to a preferred embodiment of the present invention.

As shown in FIG. 7A, a gate insulating film 202 is formed on a semiconductor substrate 201 having an NMOS region and a PMOS region. The gate insulating film 202 may be an oxide film.

Next, a polysilicon layer 203 is formed on the gate insulating film 202. Here, the polysilicon layer 203 may be undoped polysilicon or N-type polysilicon.

Subsequently, a first photoresist pattern 204 is formed on the polysilicon layer 203 in the PMOS region. The first photoresist layer pattern 204 may be formed by coating a photoresist layer on the polysilicon layer 203 and patterning the polysilicon layer 203 of the NMOS region to open by exposure and development.

Subsequently, an N-type impurity is ion-implanted on the polysilicon layer 203 of the NMOS region to form an N-type polysilicon layer 203A. Here, the N-type impurity may be phosphorus (Ph) or arsenic (As).

As shown in FIG. 7B, the first photoresist pattern 204 is removed. Here, the first photoresist pattern 204 may be removed with an oxygen strip.

Subsequently, a second photosensitive film pattern 205 is formed on the N-type polysilicon layer 203A. Here, the second photoresist pattern 205 is coated on the N-type polysilicon layer 203A and the polysilicon layer 203, and then patterned so that the polysilicon layer 203 of the PMOS region is opened by exposure and development. Can be formed.

Subsequently, P-type impurities are ion-implanted on the polysilicon layer 203 in the PMOS region to form the P-type polysilicon layer 203B. Here, the P-type impurity may be boron (B).

As shown in FIG. 7C, the second photoresist pattern 205 is removed. The second photoresist pattern 205 may be removed using an oxygen strip in the same manner as the first photoresist pattern 204.

Next, the barrier metal layer 206 is formed on the N-type and P-type polysilicon layers 203A and 203B. The barrier metal layer 206 may serve as a diffusion barrier and may have a stacked structure of Ti (titanium) and ＷN (tungsten nitride). That is, tungsten and polysilicon are in direct contact with each other to prevent silicide reactions in the subsequent thermal process, thereby preventing stress reaction due to volume expansion, thereby lowering the Rc (contact resistance) value of the gate due to stress. In addition, impurities doped into the N-type and P-type polysilicon layers 203A and 203B may be prevented from being out-diffused to the upper layer.

Next, a tungsten layer 207 is formed on the barrier metal layer 206. Here, the tungsten layer 207 is formed of CVD or ALD to lower the specific resistance of tungsten itself. That is, a large grain of bulk tungsten is grown by forming a seed layer (amorphous state) by B ₂ H ₆ , ＷF ₆ and NH ₃ treatment by CVD or ALD. By doing so, the sheet resistance value of tungsten can be lowered regardless of the kind of lower barrier material. Such tungsten is called low resistance tungsten (LRsten).

As shown in FIG. 7D, the tungsten layer 207 is planarized. Here, the planarization may be carried out by a chemical mechanical polishing process.

By planarization, the tungsten layer 207 becomes a tungsten layer 207A having a uniform thickness on the surface.

As shown in FIG. 7E, a mask pattern 208 is formed on the tungsten layer 207A. The mask pattern 208 may be formed by coating a photoresist on the tungsten layer 207A and patterning the gate pattern region to be defined by exposure and development.

As shown in FIG. 7F, the tungsten layer 207A is etched with the mask pattern 208. Here, the tungsten layer 207A can be etched using fluorine (F) -based gas because the 텅스텐 F ₆ is formed of the source gas.

The tungsten layer 207 having a non-uniform surface by growing with bulk tungsten to form a low resistance tungsten (LRW) is changed to a uniform thickness during patterning by changing the tungsten layer 207A to a uniform surface through the planarization process in FIG. 7D. Etching is possible. That is, the uniform surface of the tungsten layer 207A is transferred to the lower barrier metal layer 206 so that the barrier metal layer 206 also has a uniform surface thickness.

Hereinafter, the tungsten layer 207A on which the etching is completed is referred to as 'tungsten electrode 207B'.

Next, the barrier metal layer 206 is etched. Here, the barrier metal layer 206 may be etched using chlorine (Cl) -based gas.

The barrier metal layer 206 which has been etched is referred to as 'barrier metal 206A'.

Subsequently, the N-type and P-type polysilicon layers 203A and 203B and the gate insulating film 202 are etched. Since the planarized tungsten layer 207A was formed in advance before the formation of the tungsten electrode 207B, a uniform surface was transferred to the lower layer so that the N-type and P-type polysilicon layers 203A, 203B and the gate insulating film 202 were also uniform. The etching can proceed with. Therefore, when the etching process is completed to remove the residue after the etching to the gate insulating film 202, the substrate 201 is attacked to prevent the problem of deterioration of device characteristics and yield.

At the time of completion of etching, the mask pattern 208 may be removed or removed using an oxygen strip.

Accordingly, the gate pattern of the NMOS is formed by stacking the gate insulating film 202A, the N-type polysilicon electrode 203C, the barrier metal 206A, and the tungsten electrode 207B, and the gate pattern of the PMOS is formed by the gate insulating film 202A. , A P-type polysilicon electrode 203D, a barrier metal 206A, and a tungsten electrode 207B may be stacked.

The present invention forms a tungsten layer 105 having a low resistivity value by forming bulk tungsten by CVD or ALD process, thereby tungsten layer 105A having a uniform surface by planarizing the tungsten layer 105 having an uneven surface. When the gate pattern is etched, the uniform surface of the tungsten layer 105A is transferred to the polysilicon layer 103 and the gate insulating layer 102 to complete the etching process. ) Has an advantage of preventing the problem of deterioration of device characteristics and yield due to attack.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention described above has the effect of improving the device characteristics and yield by preventing the substrate is attacked when forming the gate pattern by forming a tungsten uniform surface while having a low specific resistance.

Claims (16)

Forming a polysilicon layer on the substrate; Forming a tungsten layer on the polysilicon layer; Planarizing the tungsten layer; Forming a mask pattern on the tungsten layer; Etching the tungsten layer; And Etching the polysilicon layer Method of manufacturing a semiconductor device comprising a. The method of claim 1, The tungsten layer is a method of manufacturing a semiconductor device, characterized in that formed by CVD (Chemical Vapor Deposition) or ALD (Atomic Layer Deposition) method. The method of claim 2, The tungsten layer is formed by forming and growing a seed layer by B ₂ H ₆ , ＷF ₆ and NH ₃ treatment. The method of claim 1, The planarizing of the tungsten layer may include A method of manufacturing a semiconductor device, characterized in that it proceeds by chemical mechanical polishing (Chemical Mechanical Polishing) process. The method of claim 1, Etching the tungsten layer, A method of manufacturing a semiconductor device, characterized in that the fluorine-based gas is used. The method of claim 1, Before forming the tungsten layer, A method of manufacturing a semiconductor device, further comprising the step of forming a barrier metal layer. The method of claim 6, The barrier metal layer is a semiconductor device manufacturing method characterized in that the laminated structure of Ti and ＷN. Forming an N-type polysilicon layer in the NMOS region and a P-type polysilicon layer in the PMOS region, respectively, on the substrate having an NMOS region and a PMOS region; Forming a barrier metal layer on the N-type and P-type polysilicon layers; Forming a tungsten layer on the barrier metal layer; Planarizing the tungsten layer; Forming a mask pattern on the tungsten layer; Etching the tungsten layer; And Etching the N-type and P-type polysilicon layers Method of manufacturing a semiconductor device having a dual poly gate comprising a. The method of claim 8, The tungsten layer is a semiconductor device manufacturing method having a dual poly gate, characterized in that formed by CVD (Chemical Vapor Deposition) or ALD (Atomic Layer Deposition) method. The method of claim 9, The method of producing a semiconductor device having a dual gate poly that the tungsten layer is characterized in that it is formed by growing and forming a seed layer (Seed Layer) due to the B ₂ H _6, WF ₆ and NH ₃ treatment. The method of claim 8, The planarizing of the tungsten layer may include A method for manufacturing a semiconductor device, characterized in that it proceeds with a chemical mechanical polishing process. The method of claim 8, Etching the tungsten layer, A method for manufacturing a semiconductor device having a dual poly gate, characterized in that the fluorine-based gas is used. The method of claim 8, Before forming the etch stop layer, A method of manufacturing a semiconductor device having a dual poly gate, further comprising forming a barrier metal layer. The method of claim 13, The barrier metal layer is a semiconductor device manufacturing method having a dual poly gate, characterized in that the laminated structure of Ti and ＷN. The method of claim 8, Forming the N-type and P-type polysilicon layers, Forming a gate insulating film over the substrate having an NMOS region and a PMOS region; Forming a polysilicon layer on the gate insulating film; Forming a first photoresist pattern on the polysilicon layer of the PMOS region; Implanting N-type impurities into the polysilicon layer of the NMOS region; Removing the first photoresist pattern; Forming a second photoresist pattern on the polysilicon layer of the NMOS region; Implanting P-type impurities into the polysilicon layer of the PMOS region; And Removing the second photoresist pattern Method of manufacturing a semiconductor device having a dual poly gate, characterized in that it comprises a. The method of claim 15, The N-type impurity is phosphorus (Ph) or arsenic (As), and the P-type impurity is boron (B).

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