KR20020001381A - Method of forming a gate electrode in a semiconductor device - Google Patents
Method of forming a gate electrode in a semiconductor device Download PDFInfo
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- KR20020001381A KR20020001381A KR1020000036056A KR20000036056A KR20020001381A KR 20020001381 A KR20020001381 A KR 20020001381A KR 1020000036056 A KR1020000036056 A KR 1020000036056A KR 20000036056 A KR20000036056 A KR 20000036056A KR 20020001381 A KR20020001381 A KR 20020001381A
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- 238000000034 method Methods 0.000 title claims abstract description 42
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 68
- 239000010937 tungsten Substances 0.000 claims abstract description 68
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 67
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 42
- 229920005591 polysilicon Polymers 0.000 claims abstract description 42
- 230000004888 barrier function Effects 0.000 claims abstract description 26
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 9
- 239000007789 gas Substances 0.000 claims description 16
- 238000010438 heat treatment Methods 0.000 claims description 16
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 7
- 238000004544 sputter deposition Methods 0.000 claims description 5
- 229910052786 argon Inorganic materials 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 238000011065 in-situ storage Methods 0.000 abstract description 8
- 230000002950 deficient Effects 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 14
- 229910052757 nitrogen Inorganic materials 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910021341 titanium silicide Inorganic materials 0.000 description 2
- -1 tungsten nitride Chemical class 0.000 description 2
- 229910008484 TiSi Inorganic materials 0.000 description 1
- 229910008807 WSiN Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 125000004433 nitrogen atom Chemical group N* 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체 소자의 게이트 전극 형성 방법에 관한 것으로, 특히 도프트 폴리실리콘막 상부에 CVD 방법으로 제 1 텅스텐막을 형성하고 NH3를 이용한 급속 열처리 공정을 실시한 후 PVD 방법으로 제 2 텅스텐막을 형성하여 게이트 전극을 형성함으로써 질소의 확산 경로가 짧아지게 되어 인시투 장벽층의 형성 신뢰성을 향상시킬 수 있는 반도체 소자의 게이트 전극 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a gate electrode of a semiconductor device. In particular, a first tungsten film is formed on a doped polysilicon film by a CVD method and a rapid heat treatment process using NH 3 is performed to form a second tungsten film by a PVD method. The present invention relates to a method for forming a gate electrode of a semiconductor device in which the diffusion path of nitrogen is shortened by forming the gate electrode, thereby improving the formation reliability of the in-situ barrier layer.
반도체 소자의 고집적화에 따라 게이트 선폭이 감소하여 기존의 높은 저항을 갖는 텅스텐 실리사이드(WSix) 또는 티타늄 실리사이드(TiSi2)에 의해서는 고집적 소자에서 요구하는 저항을 만족시키지 못하기 때문에 RC 지연 시간이 증가하게 된다. 따라서, 이와 같은 면저항 문제점을 개선시키기 위하여 최근에는 텅스텐 및 폴리실리콘 적층 게이트를 적용하고 있다.Due to the high integration of semiconductor devices, the gate line width decreases, and RC delay time increases because the conventional high resistance tungsten silicide (WSix) or titanium silicide (TiSi 2 ) does not satisfy the resistance required by the highly integrated device. do. Therefore, in order to improve such a sheet resistance problem, tungsten and polysilicon stacking gates have recently been applied.
텅스텐막은 벌크 저항률(bulk resistivity)이 ∼6μΩ㎝로 텅스텐 실리사이드의 ∼80μΩ㎝과 티타늄 실리사이드의 ∼18μΩ㎝에 비해 아주 낮은 저항을 가지므로 고집적 소자의 게이트 물질로 적합하다. 그러나, 텅스텐 및 폴리실리콘의 적층 게이트 구조는 500℃ 이상의 열공정에 의해 텅스텐과 폴리실리콘이 반응하여 텅스텐 실리사이드막이 형성됨으로써 낮은 텅스텐 게이트의 저항을 유지할 수 없는 문제점이 있다. 따라서, 텅스텐과 폴리실리콘막 사이에 장벽층으로 100Å 정도의 두께로 텅스텐 질화막(WNx)을 형성하여 텅스텐과 폴리실리콘막이 반응하여 저항을 증가시키는 것을 방지하거나, 텅스텐 및 폴리실리콘 적층 구조를 HN3가스로 급속 열처리하여 질소를 텅스텐과 실리콘의 계면에 축적(pile up)시켜 인시투로 장벽층을 형성한다.The tungsten film has a bulk resistivity of ˜6 μm cm and has a very low resistance compared to ˜80 μm cm of tungsten silicide and ˜18 μm cm of titanium silicide, and thus is suitable as a gate material of a highly integrated device. However, the laminated gate structure of tungsten and polysilicon has a problem in that the tungsten silicide film is formed by the reaction of tungsten and polysilicon by a thermal process of 500 ° C. or higher, so that the resistance of the low tungsten gate cannot be maintained. Accordingly, a tungsten nitride film (WNx) is formed between the tungsten and the polysilicon film as a barrier layer to a thickness of about 100 Å to prevent the tungsten and the polysilicon film from reacting to increase the resistance, or the tungsten and polysilicon layered structure is formed by HN 3 gas. Rapid heat treatment is performed to accumulate nitrogen at the interface between tungsten and silicon to form a barrier layer in-situ.
장벽층을 형성하기 위한 기존 공정은 텅스텐 및 폴리실리콘을 형성한 후 800℃ 정도의 온도에서 NH3가스를 이용하여 급속 열처리 공정을 실시한다. 그러나, 텅스텐 원자와 실리콘 원자는 약 500℃ 이상의 온도에서 반응하기 시작한다. 그러므로 급속 열처리 공정을 실시한다 하더라도 질소가 내부 확산되어 장벽층이 형성되기 이전에 부분적으로 텅스텐과 실리콘이 반응하여 높은 저항의 텅스텐 실리사이드가 형성된다.Conventional processes for forming the barrier layer is a rapid heat treatment process using NH 3 gas at a temperature of about 800 ℃ after forming tungsten and polysilicon. However, tungsten and silicon atoms begin to react at temperatures above about 500 ° C. Therefore, even though the rapid heat treatment process is performed, tungsten and silicon are partially reacted to form high-resistance tungsten silicide before nitrogen is diffused inside and the barrier layer is formed.
즉, 질소는 분해되어 텅스텐막을 통과하여 열역학적으로 가장 불안정한 텅스텐과 폴리실리콘막 사이에 포화된다. 그런데, 텅스텐막은 전도체지만 텅스텐 타겟을 아르곤 이온을 이용한 스퍼터링 방법에 의해 증착하기 때문에 그레인 사이즈 측면에서는 비정질 상태와 같은 막질을 유지하게 된다. 따라서, 내부 확산되는 질소는 충분히 결정화된 막에 비해 상대적으로 긴 확산 경로를 가지게 됨으로써 인-시투 장벽층을 형성하는데 불리한 조건이 된다.That is, nitrogen decomposes and passes through the tungsten film to saturate between the tungsten and polysilicon film, which are most thermodynamically unstable. By the way, although the tungsten film is a conductor, the tungsten target is deposited by the sputtering method using argon ions, so that the film quality in the amorphous state is maintained in terms of grain size. Thus, the internally diffused nitrogen has a relatively long diffusion path compared to a sufficiently crystallized film, which is an adverse condition for forming an in-situ barrier layer.
본 발명의 목적은 질소 원자의 확산 경로를 감소시켜 텅스텐막과 폴리실리콘막 사이에서 텅스텐 실리사이드가 형성되는 것을 방지할 수 있는 반도체 소자의 게이트 전극 형성 방법을 제공하는데 있다.An object of the present invention is to provide a method for forming a gate electrode of a semiconductor device that can reduce the diffusion path of nitrogen atoms to prevent the formation of tungsten silicide between the tungsten film and the polysilicon film.
본 발명의 다른 목적은 텅스텐막과 폴리실리콘막 사이에 인시투로 장벽층을형성함에 있어 공정 마진 및 공정 안정성을 개선시킬 수 있는 반도체 소자의 게이트 전극 형성 방법을 제공하는데 있다.Another object of the present invention is to provide a method for forming a gate electrode of a semiconductor device capable of improving process margins and process stability in forming an in-situ barrier layer between a tungsten film and a polysilicon film.
도 1(a) 내지 도 1(e)는 본 발명의 일 실시 예에 따른 반도체 소자의 게이트 전극 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도.1 (a) to 1 (e) are cross-sectional views of devices sequentially shown to explain a method of forming a gate electrode of a semiconductor device according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11 : 반도체 기판 12 : 게이트 산화막11 semiconductor substrate 12 gate oxide film
13 : 도프트 폴리실리콘막 14 : 제 1 텅스텐막13: doped polysilicon film 14: first tungsten film
15 : 장벽층 16 : 제 2 텅스텐막15 barrier layer 16 second tungsten film
본 발명의 일 실시 예는 반도체 기판 상부에 게이트 산화막 및 도프트 폴리실리콘막을 형성하는 단계와, 상기 도프트 폴리실리콘막 상부에 제 1 텅스텐막을 형성하는 단계와, 급속 열처리 공정을 실시하여 상기 제 1 텅스텐막과 상기 도프트 폴리실리콘막 사이의 계면에 장벽층을 형성하는 단계와, 전체 구조 상부에 제 2 텅스텐막을 형성하는 단계와, 상기 제 2 텅스텐막, 제 1 텅스텐막, 장벽층, 도프트 폴리실리콘막 및 게이트 산화막을 순차적으로 패터닝하여 게이트 전극을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.According to an embodiment of the present invention, a method of forming a gate oxide film and a doped polysilicon film on a semiconductor substrate, forming a first tungsten film on the doped polysilicon film, and performing a rapid heat treatment process may be performed. Forming a barrier layer at an interface between the tungsten film and the doped polysilicon film, forming a second tungsten film over the entire structure, the second tungsten film, the first tungsten film, the barrier layer, the doping And sequentially patterning the polysilicon film and the gate oxide film to form a gate electrode.
본 발명의 다른 실시 예는 반도체 기판 상부에 게이트 산화막 및 도프트 폴리실리콘막을 형성하는 단계와, 상기 도프트 폴리실리콘막 상부에 텅스텐 실리사이드막을 형성하는 단계와, 급속 열처리 공정을 실시하여 상기 텅스텐 실리사이드막과 상기 도프트 폴리실리콘막 사이의 계면에 장벽층을 형성하는 단계와, 전체 구조 상부에 텅스텐막을 형성하는 단계와, 상기 텅스텐막, 텅스텐 실리사이드막막, 장벽층, 도프트 폴리실리콘막 및 게이트 산화막을 순차적으로 패터닝하여 게이트 전극을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.Another embodiment of the present invention is to form a gate oxide film and a doped polysilicon film on the semiconductor substrate, a tungsten silicide film formed on the doped polysilicon film, and a rapid heat treatment process to perform the tungsten silicide film Forming a barrier layer at an interface between the doped polysilicon film, forming a tungsten film over the entire structure, the tungsten film, a tungsten silicide film, a barrier layer, a doped polysilicon film, and a gate oxide film. And patterning sequentially to form a gate electrode.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 1(a) 내지 도 1(e)는 본 발명의 일 실시 예에 따른 반도체 소자의 게이트 전극 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도이다.1 (a) to 1 (e) are cross-sectional views of devices sequentially shown to explain a method of forming a gate electrode of a semiconductor device according to an embodiment of the present invention.
도 1(a)를 참조하면, 반도체 기판(11) 상부에 게이트 산화막(12)을 형성하고, 그 상부에 도프트 폴리실리콘막(13)을 형성한다. 도프트 폴리실리콘막(13)은 SiH4가스와 PH3가스를 이용하여 600℃ 이하의 온도와 10Torr 이하의 압력에서 형성한다.Referring to FIG. 1A, a gate oxide film 12 is formed over a semiconductor substrate 11, and a doped polysilicon film 13 is formed over the semiconductor substrate 11. The doped polysilicon film 13 is formed at a temperature of 600 ° C. or less and a pressure of 10 Torr or less using SiH 4 gas and PH 3 gas.
도 1(b)를 참조하면, 세정 공정을 실시한 후 전체 구조 상부에 CVD 방법에 의해 제 1 텅스텐막(14)을 형성한다. 제 1 텅스텐막(14)은 WF6와 H2를 이용하여 400∼500℃의 온도와 10Torr 이하의 압력에서 CVD 방법으로 형성한다. CVD 방법으로 형성된 제 1 텅스텐막(14)은 스퍼터링 방법에 의해 형성된 텅스텐막에 비해 상대적으로 큰 그레인 사이즈를 가지게 된다.Referring to FIG. 1B, after the cleaning process, a first tungsten film 14 is formed on the entire structure by a CVD method. The first tungsten film 14 is formed by the CVD method using WF 6 and H 2 at a temperature of 400 to 500 ° C. and a pressure of 10 Torr or less. The first tungsten film 14 formed by the CVD method has a larger grain size than the tungsten film formed by the sputtering method.
도 1(c)를 참조하면, NH3가스를 이용한 급속 열처리 공정을 실시하여 질소 원자가 제 1 텅스텐막(14)을 통하여 제 1 텅스텐막(14)과 도프트 폴리실리콘막(13) 사이의 계면에 축적되어 장벽층(15)이 형성된다. NH3가스를 이용한 급속 열처리 공정은 600∼900℃의 온도에서 120초 이하의 시간동안 실시한다.Referring to FIG. 1C, an interface between the first tungsten film 14 and the doped polysilicon film 13 through a first tungsten film 14 is carried out by performing a rapid heat treatment process using NH 3 gas. Accumulated in the barrier layer 15 is formed. The rapid heat treatment process using NH 3 gas is performed at a temperature of 600 to 900 ° C. for up to 120 seconds.
도 1(d)를 참조하면, 전체 구조 상부에 PVD 방법에 의해 제 2 텅스텐막(16)을 형성한다. 제 2 텅스텐막(16)은 400℃ 이하의 온도와 10mTorr 이하의 압력을 유지하는 챔버에 텅스텐 타겟을 장착한 후 아르곤을 이용한 스퍼터링 방법에 의해 형성한다.Referring to FIG. 1D, a second tungsten film 16 is formed on the entire structure by the PVD method. The second tungsten film 16 is formed by a sputtering method using argon after mounting a tungsten target in a chamber maintaining a temperature of 400 ° C. or less and a pressure of 10 mTorr or less.
도 1(e)는 제 2 텅스텐막(16), 제 1 텅스텐막(14), 장벽층(15), 도프트 폴리실리콘막(13) 및 게이트 산화막(12)을 패터닝하여 게이트 전극을 형성한 상태의 단면도이다.FIG. 1E illustrates a pattern of a second tungsten film 16, a first tungsten film 14, a barrier layer 15, a doped polysilicon film 13, and a gate oxide film 12 to form a gate electrode. It is a cross section of the condition.
상술한 본 발명의 일 실시 예에서는 도프트 폴리실리콘막 상부에 CVD 방법으로 제 1 텅스텐막을 형성하고 NH3를 이용한 급속 열처리 공정을 실시한 후 PVD 방법으로 제 2 텅스텐막을 형성하여 게이트 전극을 형성하였지만, 본 발명의 다른 실시 예로서 제 1 텅스텐막 대신에 텅스텐 실리사이드막을 형성하고 후속 공정을 실시한다. 이때, 형성되는 텅스텐 실리사이드막은 SiH4가스와 PH3가스를 이용하여 500℃ 이하의 온도와 3Torr 이하의 압력에서 형성한다. 그리고, 이때 형성되는 장벽층은 WSiN의 조성을 갖는다.In the above-described embodiment of the present invention, the first tungsten film is formed on the doped polysilicon film by CVD method and the rapid heat treatment process using NH 3 is performed, followed by forming the second tungsten film by PVD method to form the gate electrode. As another embodiment of the present invention, a tungsten silicide film is formed instead of the first tungsten film and a subsequent process is performed. At this time, the formed tungsten silicide film is formed at a temperature of 500 ° C. or less and a pressure of 3 Torr or less using SiH 4 gas and PH 3 gas. The barrier layer formed at this time has a composition of WSiN.
상술한 바와 같이 본 발명에 의하면 도프트 폴리실리콘막 상부에 CVD 방법으로 제 1 텅스텐막을 형성하고 NH3를 이용한 급속 열처리 공정을 실시한 후 PVD 방법으로 제 2 텅스텐막을 형성하여 게이트 전극을 형성함으로써 다음과 같은 효과가 있다.As described above, according to the present invention, a first tungsten film is formed on the doped polysilicon film by a CVD method, a rapid heat treatment process using NH 3 is performed, and a second tungsten film is formed by the PVD method to form a gate electrode. Same effect.
첫째, 도프트 폴리실리콘막 상부에 CVD 방법으로 제 1 텅스텐막을 형성한 후 NH3를 이용한 급속 열처리 공정을 실시하면 제 1 텅스텐막의 두께와 그레인 사이즈측면에서 질소의 확산 경로가 짧아지게 되어 인시투 장벽층의 형성 신뢰성을 향상시킬 수 있다.First, if the first tungsten film is formed on the doped polysilicon film by CVD method and the rapid heat treatment process using NH 3 is performed, the diffusion path of nitrogen is shortened in terms of thickness and grain size of the first tungsten film. The formation reliability of a layer can be improved.
둘째, 기존의 인-시투 장벽층의 불량으로 발생된 텅스텐 실리사이드막에 의한 게이트 식각시의 기판에 발생되는 핀홀을 방지할 수 있어 소자의 신뢰성을 향상시킬 수 있다.Second, pinholes generated in the substrate during the gate etching by the tungsten silicide layer caused by the defect of the existing in-situ barrier layer can be prevented, thereby improving the reliability of the device.
세째, 인-시투 장벽층의 신뢰성을 향상시켜 높은 저항의 텅스텐 실리사이드막이 발생되는 것을 방지하여 저저항의 게이트 면저항을 확보할 수 있다.Third, it is possible to improve the reliability of the in-situ barrier layer to prevent the generation of a high resistance tungsten silicide film to secure a low resistance gate sheet resistance.
네째, 제 1 텅스텐막내에만 질소가 함유되기 때문에 낮은 저항의 텅스텐 게이트 전극을 형성할 수 있다.Fourth, since nitrogen is contained only in the first tungsten film, a low resistance tungsten gate electrode can be formed.
다섯째, 장벽층 형성을 위한 확산 경로가 감소됨으로써 NH3급속 열처리 온도와 시간을 감소시킬 수 있어 소자의 열버짓(thermal budget)을 줄일 수 있다.Fifth, the diffusion path for forming the barrier layer is reduced, thereby reducing the NH 3 rapid heat treatment temperature and time, thereby reducing the thermal budget of the device.
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| KR100456314B1 (en) * | 2000-06-30 | 2004-11-10 | 주식회사 하이닉스반도체 | Method for forming gate electrode in semiconductor deivce |
| KR100897248B1 (en) * | 2002-12-26 | 2009-05-14 | 주식회사 하이닉스반도체 | Method for forming gate-electrode in semiconductor device |
| KR100905185B1 (en) * | 2002-12-27 | 2009-06-29 | 주식회사 하이닉스반도체 | Method for fabricating gate electrode of semiconductor device |
| US8629062B2 (en) | 2007-11-30 | 2014-01-14 | Hynix Semiconductor Inc. | Method for forming tungsten film having low resistivity and good surface roughness and method for forming wiring of semiconductor device using the same |
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| US6048791A (en) * | 1998-03-31 | 2000-04-11 | Kabushiki Kaisha Toshiba | Semiconductor device with electrode formed of conductive layer consisting of polysilicon layer and metal-silicide layer and its manufacturing method |
| KR100296126B1 (en) * | 1998-12-22 | 2001-08-07 | 박종섭 | Gate electrode formation method of highly integrated memory device |
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| KR100456314B1 (en) * | 2000-06-30 | 2004-11-10 | 주식회사 하이닉스반도체 | Method for forming gate electrode in semiconductor deivce |
| KR100897248B1 (en) * | 2002-12-26 | 2009-05-14 | 주식회사 하이닉스반도체 | Method for forming gate-electrode in semiconductor device |
| KR100905185B1 (en) * | 2002-12-27 | 2009-06-29 | 주식회사 하이닉스반도체 | Method for fabricating gate electrode of semiconductor device |
| US8629062B2 (en) | 2007-11-30 | 2014-01-14 | Hynix Semiconductor Inc. | Method for forming tungsten film having low resistivity and good surface roughness and method for forming wiring of semiconductor device using the same |
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