KR20090022336A - Method for fabricating semiconducotr device with tungsten poly gate - Google Patents

Method for fabricating semiconducotr device with tungsten poly gate Download PDF

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KR20090022336A
KR20090022336A KR1020070087622A KR20070087622A KR20090022336A KR 20090022336 A KR20090022336 A KR 20090022336A KR 1020070087622 A KR1020070087622 A KR 1020070087622A KR 20070087622 A KR20070087622 A KR 20070087622A KR 20090022336 A KR20090022336 A KR 20090022336A
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tungsten
film
layer
containing film
pattern
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양홍선
성민규
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/28132—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H01L29/4958—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo with a multiple layer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2

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Abstract

A method for manufacturing a semiconductor device with a tungsten poly gate is provided to prevent impurity like nitrogen in a tungsten layer due to the gas used when using a nitride layer by using the tungsten layer as a capping layer. A gate insulating layer(22) is formed on a substrate(21). A pattern including at least first tungsten containing layer(25) is formed on the gate insulating layer. A second tungsten containing layer to cover the both sides of the pattern is formed. A gate structure is formed by etching the pattern additionally using the second tungsten containing layer as an etch barrier. A selective oxidation process is performed to the substrate under the hydrogen atmosphere preventing the oxidation of the first tungsten containing layer. The first tungsten containing layer is a stack structure of the tungsten nitride layer and the tungsten layer. The second tungsten containing layer is the tungsten layer. The first and second tungsten containing layers are formed by using a physical vapor deposition or chemical vapor deposition method.

Description

텅스텐폴리게이트를 구비한 반도체소자의 제조 방법{METHOD FOR FABRICATING SEMICONDUCOTR DEVICE WITH TUNGSTEN POLY GATE}Method for manufacturing semiconductor device with tungsten polygate {METHOD FOR FABRICATING SEMICONDUCOTR DEVICE WITH TUNGSTEN POLY GATE}

본 발명은 반도체 제조 기술에 관한 것으로, 특히 텅스텐폴리게이트(Tungsten poly gate)를 구비하는 반도체소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method for manufacturing a semiconductor device having a tungsten poly gate.

최근에 텅스텐실리사이드막보다 비저항이 낮은 텅스텐막을 게이트전극으로 적용하는 텅스텐폴리게이트(W Poly Gate)가 제안된 바 있다. 텅스텐폴리게이트는 게이트전극이 폴리실리콘막과 텅스텐막이 적층된 구조로서, 텅스텐막의 낮은 시트저항(Rs)에 의해 고속 동작의 소자에 유리하다. 텅스텐폴리게이트는 폴리실리콘막과 텅스텐막의 반응을 방지하기 위해 확산배리어막(Diffusion Barrier)을 삽입하고 있다.Recently, a tungsten polygate (W Poly Gate) using a tungsten film having a lower resistivity than a tungsten silicide film has been proposed. The tungsten polygate has a structure in which a gate electrode is formed of a polysilicon film and a tungsten film laminated, and is advantageous for devices of high speed operation due to the low sheet resistance Rs of the tungsten film. The tungsten polygate inserts a diffusion barrier film to prevent a reaction between the polysilicon film and the tungsten film.

위와 같이 텅스텐폴리게이트를 적용하는 경우, 게이트 식각을 완료하면 게이트재산화(Gate reoxidation) 공정을 진행하는데, 게이트재산화 공정은 텅스텐막의 산화를 방지하기 위해 선택적산화(Selective Oxidation) 공정이 적용된다. 선택적산화 공정은 수소 분위기에서 진행한다. In the case of applying the tungsten polygate as described above, when the gate etching is completed, a gate reoxidation process is performed. In the gate reoxidation process, a selective oxidation process is applied to prevent oxidation of the tungsten film. The selective oxidation process is carried out in a hydrogen atmosphere.

그러나, 선택적산화 공정시 폴리실리콘막과 확산배리어막 사이에 산화막 계열의 얇은 기생막이 형성되고, 이 기생막은 계면 저항을 증가시켜 신호지연, 예를 들어 링오실레이터(Ring Oscillator) 지연(Delay) 특성을 열화시키는 등의 부작용이 관찰된다. However, during the selective oxidation process, an oxide-based thin parasitic layer is formed between the polysilicon layer and the diffusion barrier layer, and the parasitic layer increases the interfacial resistance, thereby improving signal delay, for example, ring oscillator delay characteristics. Side effects such as deterioration are observed.

이를 개선하기 위해 선택적산화 공정 전에 캡핑막(Capping scheme)을 적용하고 있는데, 이는 1차 게이트식각후 드러난 확산배리어막과 폴리실리콘막의 계면을 저압화학기상증착법에 의한 질화막(Low pressue CVD Nitride)을 이용하여 캡핑하므로써 후속 폴리실리콘막 식각후에 진행되는 선택적산화 공정시 확산배리어막과 폴리실리콘막의 계면을 보호하는 역할을 한다.In order to improve this, a capping scheme is applied before the selective oxidation process, which uses a low pressure chemical vapor deposition method to form an interface between the diffusion barrier layer and the polysilicon layer after the first gate etching. By capping, it protects the interface between the diffusion barrier film and the polysilicon film during the selective oxidation process that is performed after the subsequent polysilicon film etching.

도 1은 종래기술에 따른 텅스텐폴리게이트를 구비한 반도체소자의 구조를 도시한 도면이다.1 is a view showing the structure of a semiconductor device having a tungsten polygate according to the prior art.

도 1을 참조하면, 기판(11) 상에 게이트절연막(12)이 형성되고, 게이트절연막(12) 상에 폴리실리콘막(Poly-si, 13), 확산배리어막(Barrier Metal, 14), 텅스텐막(W, 15) 및 게이트하드마스크막(16)의 순서로 적층된 텅스텐폴리게이트가 형성된다. 텅스텐폴리게이트 중에서 폴리실리콘막(13)의 상부 측벽, 확산배리어막(14), 텅스텐막(15) 및 게이트하드마스크막(16)의 측벽에는 그 재질이 질화막인 캡핑막(17)이 형성되어 있다. 그리고, 폴리실리콘막(13)의 나머지 측벽에는 선택적산화공정에 의한 실리콘산화막(13A)이 형성되어 있다.Referring to FIG. 1, a gate insulating film 12 is formed on a substrate 11, a poly-si 13, a barrier metal 14, and tungsten on the gate insulating film 12. The tungsten polygates stacked in the order of the films W and 15 and the gate hard mask film 16 are formed. Among the tungsten polygates, a capping film 17 made of a nitride film is formed on the upper sidewall of the polysilicon film 13, the diffusion barrier film 14, the tungsten film 15, and the gate hard mask film 16. have. The silicon oxide film 13A by the selective oxidation process is formed on the remaining sidewalls of the polysilicon film 13.

캡핑막(17)으로 사용되는 질화막의 저압화학기상증착 공정은 NH3와 DCS(Dichloro-silane)을 이용한다.The low pressure chemical vapor deposition process of the nitride film used as the capping film 17 uses NH 3 and DCS (Dichloro-silane).

그러나, 텅스텐막의 시트저항(Rs)이 캡핑막(17)으로 사용되는 질화막 공정 직후 증가하는 것이 관찰된다. 즉, 증착상태(As-dep)의 W/WN(400Å/50Å) 박막의 시트저항은 3.4∼3.6Ω/square를 나타내는 반면, 모니터링 웨이퍼(monitoring wafer) 기준의 20Å 두께의 질화막을 텅스텐막 위에 증착한 후의 시트 저항은 5.5∼7.5Ω/square으로 높은 증가를 보여준다. 이는 질화막 증착 공정시 사용되는 NH3 가스가 텅스텐막을 질화(Nitridation)시켜 텅스텐막의 비저항(Resistivity)을 증가시키기 때문이다.However, it is observed that the sheet resistance Rs of the tungsten film increases immediately after the nitride film process used as the capping film 17. That is, while the sheet resistance of the W / WN (400Å / 50Å) thin film in the deposited state (As-dep) shows 3.4 to 3.6Ω / square, a 20Å thick nitride film based on a monitoring wafer is deposited on the tungsten film. After that, the sheet resistance shows a high increase from 5.5 to 7.5Ω / square. This is because NH 3 gas used in the nitride film deposition process increases the resistivity of the tungsten film by nitriding the tungsten film.

이와 같이, 캡핑막으로 사용되는 질화막 공정에 의한 텅스텐막의 비저항 증가는 텅스텐막의 특징인 낮은 시트저항의 장점을 훼손하고, 디자인룰 감소에 따른 메모리셀어레이의 연속적인 게이트패턴(Continuity Pattern)에서의 셀 시트저항(Cell Rs) 증가를 급격히 일으키는 요인으로 작용하게 된다. As such, the increase in the resistivity of the tungsten film by the nitride film process used as the capping film undermines the advantages of the low sheet resistance, which is characteristic of the tungsten film, and the cells in the continuous gate pattern of the memory cell array due to the reduction of design rules. This causes a sudden increase in sheet resistance (Cell Rs).

본 발명은 상기한 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 선택적 산화 공정시 폴리실리콘막과 확산배리어막 사이에 기생막이 형성되는 것을 방지하는 캡핑막을 적용하면서도 캡핑막 공정에 의한 텅스텐막의 시트저항 증가를 억제할 수 있는 반도체소자의 제조 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems of the prior art, while applying a capping film to prevent the formation of parasitic film between the polysilicon film and the diffusion barrier film during the selective oxidation process sheet resistance of the tungsten film by the capping film process It is an object of the present invention to provide a method for manufacturing a semiconductor device that can suppress the increase.

상기 목적을 달성하기 위한 본 발명의 반도체소자의 제조 방법은 기판 상에 게이트절연막을 형성하는 단계, 상기 게이트절연막 상에 적어도 제1텅스텐함유막을 포함하는 패턴을 형성하는 단계, 상기 패턴의 양측벽을 덮는 제2텅스텐함유막을 형성하는 단계, 상기 제2텅스텐함유막을 식각장벽으로 하여 상기 패턴을 추가로 식각하여 게이트 구조를 완성하는 단계, 및 상기 제1텅스텐함유막의 산화를 방지하는 수소 분위기의 선택적 산화공정을 실시하는 단계를 포함하는 것을 특징으로 하고, 상기 제1텅스텐함유막과 제2텅스텐함유막은 텅스텐막인 것을 특징으로 하며, 상기 제1텅스텐함유막은 텅스텐질화막과 텅스텐막의 적층구조이고, 상기 제2텅스텐함유막은 텅스텐막인 것을 특징으로 한다.A method of manufacturing a semiconductor device of the present invention for achieving the above object comprises the steps of forming a gate insulating film on a substrate, forming a pattern including at least a first tungsten-containing film on the gate insulating film, both side walls of the pattern Forming a covering second tungsten-containing film; further etching the pattern using the second tungsten-containing film as an etch barrier to complete a gate structure; and selective oxidation of a hydrogen atmosphere to prevent oxidation of the first tungsten-containing film. And performing a process, wherein the first tungsten-containing film and the second tungsten-containing film are tungsten films, wherein the first tungsten-containing film is a laminated structure of a tungsten nitride film and a tungsten film. The tungsten-containing film is a tungsten film.

본 발명은 캡핑막으로 텅스텐막을 사용하므로써, 질화막 사용시 사용하는 가 스 중의 하나인 NH3에 의해 텅스텐막 내에 질소와 같은 불순물이 함유되는 것을 방지하고, 이로써 전극으로 사용되는 제1텅스텐함유막의 시트저항 증가를 근본적으로 방지할 수 있다.According to the present invention, by using a tungsten film as a capping film, NH 3 , which is one of the gases used when the nitride film is used, prevents impurities such as nitrogen from being contained in the tungsten film, thereby reducing sheet resistance of the first tungsten-containing film used as an electrode The increase can be fundamentally prevented.

또한, 본 발명은 제2텅스텐함유막을 캡핑막으로 사용하므로써 전극으로 사용되는 제1텅스텐함유막의 폭이 증가하는 효과를 가져 셀의 시트저항 감소 효과를 더욱 얻을 수 있다.In addition, the present invention has the effect of increasing the width of the first tungsten-containing film used as an electrode by using the second tungsten-containing film as a capping film can further obtain a sheet resistance reduction effect of the cell.

또한, 본 발명은 캡핑막을 제2텅스텐함유막으로 사용하므로써 스트레스에 의한 게이트의 기울어짐 현상을 방지할 수 있는 효과가 있다.In addition, the present invention has an effect of preventing the tilting of the gate due to stress by using the capping film as the second tungsten-containing film.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

도 2a 내지 도 2d는 본 발명의 실시예에 따른 텅스텐폴리게이트를 구비한 반도체소자의 제조 방법을 도시한 공정 단면도이다.2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device having a tungsten polygate according to an embodiment of the present invention.

도 2a에 도시된 바와 같이, 기판(21) 상에 게이트절연막(22)을 형성한다. 이때, 게이트절연막(22)은 실리콘산화막(SiO2), 실리콘산화질화막(SiON), SiN(silicon Nitride), 금속 산화물 및 금속 실리케이트로 이루어진 그룹 중에서 선택된 어느 하나이거나 또는 적어도 2가지 이상을 조합한 적층구조일 수 있다.As shown in FIG. 2A, a gate insulating film 22 is formed on the substrate 21. In this case, the gate insulating layer 22 may be any one selected from the group consisting of a silicon oxide film (SiO 2 ), a silicon oxynitride film (SiON), a silicon nitride (SiN), a metal oxide, and a metal silicate, or a combination of at least two or more thereof. It may be a structure.

게이트절연막(22) 상에 폴리실리콘막(23)을 형성한다. 여기서, 폴리실리콘막(23)은 불순물이 도핑된 폴리실리콘막, 바람직하게는 P형 도전형 불순물 또는 N형 도전형 불순물이 도핑된 폴리실리콘막이다. P형 도전형 불순물은 붕소(Boron; B)를 포함할 수 있고, N형 도전형 불순물은 인(Phosphorous; P)을 포함할 수 있다.The polysilicon film 23 is formed on the gate insulating film 22. Here, the polysilicon film 23 is a polysilicon film doped with an impurity, preferably a polysilicon film doped with a P-type conductivity or an N-type conductivity. The P-type conductive impurity may include boron (B), and the N-type conductive impurity may include phosphorous (P).

폴리실리콘막(23) 상에 확산배리어막(24)을 형성한다. 이때, 확산배리어막(24)은 폴리실리콘막(23)과 후속 텅스텐막간 반응을 방지하는 역할을 하며, 배리어메탈(Barrier metal)이라고도 한다. 바람직하게, 확산배리어막(24)은 텅스텐실리사이드막, 티타늄질화막(TiN), 티타늄막(Ti), 텅스텐질화막(WN) 및 탄탈륨질화막(TaN)으로 이루어진 그룹 중에서 선택된 어느 하나이거나 또는 적어도 2가지 이상을 조합한 적층구조일 수 있다. 확산배리어막(24)으로 사용되는 물질들은 물리기상증착법(PVD)으로 증착할 수 있다.The diffusion barrier film 24 is formed on the polysilicon film 23. At this time, the diffusion barrier film 24 serves to prevent the reaction between the polysilicon film 23 and the subsequent tungsten film, also referred to as a barrier metal (Barrier metal). Preferably, the diffusion barrier film 24 is any one selected from the group consisting of a tungsten silicide film, a titanium nitride film (TiN), a titanium film (Ti), a tungsten nitride film (WN), and a tantalum nitride film (TaN), or at least two or more. It may be a laminated structure in combination. Materials used as the diffusion barrier film 24 may be deposited by physical vapor deposition (PVD).

확산배리어막(24) 상에 제1텅스텐함유막(25)을 형성한다. 여기서, 제1텅스텐함유막(25)은 질소가 함유된 텅스텐막과 텅스텐막을 포함할 수 있는데, 예를 들어 텅스텐질화막(WN)과 텅스텐막(W)의 이중막일 수 있다. 이때, 텅스텐질화막은 30 ∼100Å 두께로 형성하고, 텅스텐막은 300∼600Å의 두께로 형성한다. 그리고, 제1텅스텐함유막(25)으로 사용되는 텅스텐질화막과 텅스텐막은 물리기상증착법(PVD) 또는 화학기상증착법(CVD)을 이용하여 증착할 수 있다.The first tungsten-containing film 25 is formed on the diffusion barrier film 24. The first tungsten-containing film 25 may include a tungsten film containing tungsten and a tungsten film. For example, the first tungsten-containing film 25 may be a double film of the tungsten nitride film WN and the tungsten film W. At this time, the tungsten nitride film is formed to a thickness of 30 to 100 kPa, and the tungsten film is formed to a thickness of 300 to 600 kPa. The tungsten nitride film and the tungsten film used as the first tungsten-containing film 25 may be deposited using physical vapor deposition (PVD) or chemical vapor deposition (CVD).

제1텅스텐함유막(25) 상에 게이트하드마스크막(26)을 형성한다. 이때, 게이트하드마스크막(26)은 질화막, 예를 들어 실리콘질화막으로 형성할 수 있다.A gate hard mask film 26 is formed on the first tungsten-containing film 25. In this case, the gate hard mask layer 26 may be formed of a nitride layer, for example, a silicon nitride layer.

공지의 방법으로 형성된 감광막패턴(도시 생략)을 식각장벽으로 하여 게이트 하드마스크막(26), 제1텅스텐함유막(25) 및 확산배리어막(24)을 식각하고, 연속해서 폴리실리콘막(23)의 일부를 식각하는 1차 게이트식각 공정을 진행한다. 이때, 일부 식각되는 폴리실리콘막(23)의 두께는 50∼100Å이다.The gate hard mask film 26, the first tungsten-containing film 25, and the diffusion barrier film 24 are etched using the photosensitive film pattern (not shown) formed by a known method as an etch barrier, and the polysilicon film 23 is continuously formed. A first gate etching process is performed to etch a portion of At this time, the thickness of the partially etched polysilicon film 23 is 50 to 100 kPa.

이와 같은 1차 게이트식각에 의해 폴리실리콘막(23), 확산배리어막(24), 제1텅스텐함유막(25) 및 게이트하드마스크막(26)으로 이루어진 패턴(100)이 형성된다.By the primary gate etching, a pattern 100 including the polysilicon layer 23, the diffusion barrier layer 24, the first tungsten-containing layer 25, and the gate hard mask layer 26 is formed.

도 2b에 도시된 바와 같이, 패턴(100)을 포함한 전면에 제2텅스텐함유막(27)을 형성한다. 이때, 제2텅스텐함유막(27)은 텅스텐막일 수 있다.As shown in FIG. 2B, the second tungsten-containing film 27 is formed on the entire surface including the pattern 100. In this case, the second tungsten-containing film 27 may be a tungsten film.

바람직하게, 제2텅스텐함유막(27)으로 사용되는 텅스텐막은 물리기상증착법(PVD) 또는 화학기상증착법(CVD)을 이용하여 30∼200Å 두께로 증착한다.Preferably, the tungsten film used as the second tungsten-containing film 27 is deposited to have a thickness of 30 to 200 GPa using physical vapor deposition (PVD) or chemical vapor deposition (CVD).

도 2c에 도시된 바와 같이, 2차 게이트식각을 진행한다. 이때, 2차 게이트식각은 제2텅스텐함유막(27)을 전면 식각(Blanket etch)하여 1차 게이트식각공정후의 결과물 측벽에 캡핑막(27A)을 형성시키고, 이후, 캡핑막(27A) 및 게이트하드마스크막(26)을 식각장벽으로 하여 폴리실리콘막(23)을 식각하는 공정이다. 여기서, 캡핑막(27A) 형성을 위한 전면식각은 에치백을 사용할 수 있으며, 이때 캡핑막(27A)으로 사용된 물질이 텅스텐막이므로 식각가스로는 SF6 가스를 이용할 수 있다. 폴리실리콘막(23) 식각시에는 Cl2 또는 HBr 가스를 이용할 수 있다.As shown in FIG. 2C, secondary gate etching is performed. At this time, the secondary gate etching is to etch the entire surface of the second tungsten-containing film 27 to form a capping layer 27A on the sidewall of the resultant after the primary gate etching process, and then the capping layer 27A and the gate The polysilicon film 23 is etched using the hard mask film 26 as an etching barrier. Here, the etch back may be used for the front surface etching to form the capping layer 27A. In this case, since the material used as the capping layer 27A is a tungsten layer, SF 6 gas may be used as the etching gas. When etching the polysilicon film 23, Cl 2 or HBr gas may be used.

위와 같은 2차 게이트식각공정후에 폴리실리콘막패턴(23A), 확산배리어막(24), 제1텅스텐함유막(25) 및 게이트하드마스크막(26)의 순서로 적층된 텅스텐폴리게이트(101) 구조가 완성되며, 폴리실리콘막패턴(23A)의 상부 측벽과 확산배리 어막(24), 제1텅스텐함유막(25) 및 게이트하드마스크막(26)의 측벽에는 캡핑막(27A)이 형성된다.After the secondary gate etching process as described above, the tungsten polygate 101 laminated in the order of the polysilicon layer pattern 23A, the diffusion barrier layer 24, the first tungsten-containing layer 25 and the gate hard mask layer 26 The structure is completed, and a capping layer 27A is formed on the upper sidewall of the polysilicon layer pattern 23A, the sidewalls of the diffusion barrier layer 24, the first tungsten-containing layer 25, and the gate hard mask layer 26. .

도 2d에 도시된 바와 같이, 게이트재산화공정으로서 선택적산화 공정을 진행한다. 이때, 선택적산화 공정은 제1텅스텐함유막(25)의 산화를 방지하기 위해서 수소 분위기에서 진행한다. 이로써 선택적 산화 공정은 수소가 다량 함유된 분위기에서 진행하는 습식산화공정(Hydrogen-rich Wet Oxidation)이 된다. 수소분위기에서 선택적산화 공정을 진행하면, 제1텅스텐함유막(25) 측벽의 산화는 일어나지 않고 폴리실리콘막패턴(23A)의 측벽만 선택적으로 산화된다. 이로써, 폴리실리콘막패턴(23A)의 양측벽에만 실리콘산화막(23B)이 형성된다.As shown in FIG. 2D, a selective oxidation process is performed as a gate reoxidation process. At this time, the selective oxidation process is performed in a hydrogen atmosphere in order to prevent oxidation of the first tungsten-containing film 25. Thus, the selective oxidation process is a wet-oxidation process (Hydrogen-rich Wet Oxidation) that proceeds in an atmosphere containing a large amount of hydrogen. When the selective oxidation process is performed in the hydrogen atmosphere, oxidation of the sidewalls of the first tungsten-containing film 25 does not occur, and only sidewalls of the polysilicon film pattern 23A are selectively oxidized. As a result, the silicon oxide film 23B is formed only on both side walls of the polysilicon film pattern 23A.

바람직하게, 수소분위기의 선택적산화 공정은 급속열처리(RTP), 플라즈마열처리(Plasma assist Annealing) 또는 퍼니스열처리(Furnace)를 적용할 수 있다.Preferably, the selective oxidation process of the hydrogen atmosphere may be rapid heat treatment (RTP), plasma heat treatment (Plasma assist Annealing) or furnace heat treatment (Furnace).

상술한 실시예에 따르면, 캡핑막(27A)으로 질화막을 사용하는 것이 아니라 텅스텐막을 사용하므로써, 질화막 사용시 사용하는 가스 중의 하나인 NH3에 의해 텅스텐막 내에 질소와 같은 불순물이 함유되는 것을 방지하고, 이로써 제1텅스텐함유막(25)의 시트저항 증가를 근본적으로 방지할 수 있다.According to the embodiment described above, by using a tungsten film instead of using a nitride film as the capping film 27A, it is possible to prevent impurities such as nitrogen from being contained in the tungsten film by NH 3 , which is one of the gases used when the nitride film is used. As a result, an increase in sheet resistance of the first tungsten-containing film 25 can be prevented.

또한, 질화막을 캡핑막으로 사용하는 경우 게이트의 선폭(CD) 값에는 텅스텐막의 선폭뿐 아니라 캡핑막의 두께까지 포함된 값이 되어 메모리셀패턴에서의 시트저항값에 기여하는 텅스텐막의 선폭은 디자인 룰보다 훨씬 적어 제품의 디자인룰 이 감소할수록 셀의 시트저항이 급격히 증가할 수 있는 데 반해, 제2텅스텐함유막을 캡핑막(27A)으로 사용되면 전극으로 사용되는 제1텅스텐함유막(25)의 폭이 증가하는 효과를 가져 셀의 시트저항 감소 효과를 더욱 얻을 수 있다.In addition, when the nitride film is used as the capping film, the line width (CD) of the gate includes not only the line width of the tungsten film but also the thickness of the capping film, so that the line width of the tungsten film, which contributes to the sheet resistance in the memory cell pattern, is smaller than the design rule. It is much less so that the sheet resistance of the cell can increase rapidly as the design rule of the product decreases, whereas when the second tungsten-containing film is used as the capping film 27A, the width of the first tungsten-containing film 25 used as the electrode is The effect of increasing the sheet sheet resistance of the cell can be further obtained.

또한, 캡핑막(27A)을 제2텅스텐함유막으로 사용하면, 질화막을 사용하는 경우에 관찰되는 게이트 리닝(Gate Leaning) 현상을 방지할 수 있다. 예컨대, 통상의 질화막은 막 자체가 스트레스(Stress)를 갖고, 캡핑막으로서 질화막을 증착하게 되면 스트레스에 의해 게이트가 기울어지는 리닝 현상이 유발된다. 이에 반해, 본 발명은 캡핑막으로서 텅스텐함유막을 사용하기 때문에 스트레스에 의한 게이트의 기울어짐 현상이 근본적으로 발생하지 않는다.In addition, when the capping film 27A is used as the second tungsten-containing film, the gate leaning phenomenon observed when the nitride film is used can be prevented. For example, in the conventional nitride film, the film itself has a stress, and when the nitride film is deposited as a capping film, a lining phenomenon in which the gate is inclined due to the stress is caused. In contrast, in the present invention, since the tungsten-containing film is used as the capping film, the gate tilt due to stress does not occur.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

도 1은 종래기술에 따른 텅스텐폴리게이트를 구비한 반도체소자의 구조를 도시한 도면.1 is a view showing the structure of a semiconductor device having a tungsten polygate according to the prior art.

도 2a 내지 도 2d는 본 발명의 실시예에 따른 텅스텐폴리게이트를 구비한 반도체소자의 제조 방법을 도시한 공정 단면도.2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device having a tungsten polygate according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

21 : 기판 22 : 게이트절연막21 substrate 22 gate insulating film

23A : 폴리실리콘막패턴 23B : 실리콘산화막23A: polysilicon film pattern 23B: silicon oxide film

24 : 확산배리어막 25 : 제1텅스텐함유막24: diffusion barrier film 25: first tungsten-containing film

26 : 게이트하드마스크막 27A : 캡핑막26: gate hard mask film 27A: capping film

Claims (10)

기판 상에 게이트절연막을 형성하는 단계;Forming a gate insulating film on the substrate; 상기 게이트절연막 상에 적어도 제1텅스텐함유막을 포함하는 패턴을 형성하는 단계;Forming a pattern including at least a first tungsten-containing film on the gate insulating film; 상기 패턴의 양측벽을 덮는 제2텅스텐함유막을 형성하는 단계;Forming a second tungsten-containing film covering both sidewalls of the pattern; 상기 제2텅스텐함유막을 식각장벽으로 하여 상기 패턴을 추가로 식각하여 게이트 구조를 완성하는 단계; 및Further etching the pattern using the second tungsten-containing film as an etch barrier to complete a gate structure; And 상기 제1텅스텐함유막의 산화를 방지하는 수소 분위기의 선택적 산화공정을 실시하는 단계Performing a selective oxidation process of hydrogen atmosphere to prevent oxidation of the first tungsten-containing film 를 포함하는 반도체소자의 제조 방법.Method for manufacturing a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 제1텅스텐함유막과 제2텅스텐함유막은 동일 물질인 반도체소자의 제조 방법.And the first tungsten-containing film and the second tungsten-containing film are made of the same material. 제1항에 있어서,The method of claim 1, 상기 제1텅스텐함유막과 제2텅스텐함유막은 텅스텐막인 반도체소자의 제조 방법.The first tungsten-containing film and the second tungsten-containing film are tungsten films. 제1항에 있어서,The method of claim 1, 상기 제1텅스텐함유막은 텅스텐질화막과 텅스텐막의 적층구조이고, 상기 제2텅스텐함유막은 텅스텐막인 반도체소자의 제조 방법.The first tungsten-containing film is a laminated structure of a tungsten nitride film and a tungsten film, and the second tungsten-containing film is a tungsten film. 제1항에 있어서,The method of claim 1, 상기 제1텅스텐함유막과 제2텅스텐함유막은 물리기상증착법(PVD) 또는 화학기상증착법(CVD)을 이용하여 형성하는 반도체소자의 제조 방법.The first tungsten-containing film and the second tungsten-containing film are formed using physical vapor deposition (PVD) or chemical vapor deposition (CVD). 제1항에 있어서,The method of claim 1, 상기 제2텅스텐함유막은 30∼200Å 두께로 형성하는 반도체소자의 제조 방법.And the second tungsten-containing film is formed to a thickness of 30 to 200 GPa. 제1항에 있어서,The method of claim 1, 상기 패턴의 양측벽을 덮는 제2텅스텐함유막을 형성하는 단계는,Forming a second tungsten-containing film covering both side walls of the pattern, 상기 패턴을 포함한 전면에 텅스텐막을 증착하는 단계; 및Depositing a tungsten film on the entire surface including the pattern; And 상기 텅스텐막을 전면식각하는 단계Etching the tungsten film 를 포함하는 반도체소자의 제조 방법.Method for manufacturing a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 선택적산화 공정은,The selective oxidation process, 급속열처리(RTP), 플라즈마열처리(Plasma assist Annealing) 또는 퍼니스열처리(Furnace)를 적용하는 반도체소자의 제조 방법.10. A method for manufacturing a semiconductor device using rapid thermal treatment (RTP), plasma assisted annealing or furnace thermal treatment. 제1항에 있어서,The method of claim 1, 상기 패턴은,The pattern is, 폴리실리콘막, 확산배리어막, 제1텅스텐함유막 및 게이트하드마스크막의 순서로 적층한 후, 상기 폴리실리콘막의 일부까지 식각하여 형성하는 반도체소자의 제조 방법.A method of manufacturing a semiconductor device, wherein a polysilicon film, a diffusion barrier film, a first tungsten-containing film and a gate hard mask film are laminated in this order and then etched to a part of the polysilicon film. 제9항에 있어서,The method of claim 9, 상기 확산배리어막은,The diffusion barrier film, 텅스텐실리사이드막, 티타늄질화막(TiN), 티타늄막(Ti), 텅스텐질화막(WN) 및 탄탈륨질화막(TaN)으로 이루어진 그룹 중에서 선택된 어느 하나이거나 또는 적어도 2가지 이상을 조합한 적층구조인 반도체소자의 제조 방법.Fabrication of a semiconductor device having any one selected from the group consisting of a tungsten silicide film, a titanium nitride film (TiN), a titanium film (Ti), a tungsten nitride film (WN), and a tantalum nitride film (TaN) or a combination of at least two or more thereof Way.
KR1020070087622A 2007-08-30 2007-08-30 Method for fabricating semiconducotr device with tungsten poly gate KR20090022336A (en)

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