KR100542249B1 - Polymetal gate electrode and method for manufacturing the same - Google Patents

Abstract

Disclosed are a polymetal gate electrode structure and a method of manufacturing the same, which reduce a film stress of a gate stack by interposing a stress buffer buffer layer in a middle of a polysilicon layer for a gate electrode, and a method for manufacturing the same The polymetal gate electrode may include a gate insulating layer formed on a semiconductor substrate; And a gate stack patterned on the gate insulating layer, the gate stack having a lower polysilicon layer and an upper layer hardmask insulating layer and a metal layer interposed therebetween, wherein the polysilicon layer is in the middle of the layer. And a stress buffer layer interposed therebetween.

Polymetal, Gate, Stress, Silicide Film

Description

Polymetal gate electrode having stress buffer layer and method for manufacturing the same             

1A through 1D are cross-sectional views of a method of manufacturing a polymetal gate electrode according to the related art, and a process for manufacturing a W / WN _x / Poly-Si gate electrode;

2 is experimental data showing a problem of the prior art,

3 is a cross-sectional view showing a structure of a polymetal gate electrode according to a preferred embodiment of the present invention;

4A-4G are process cross-sectional views illustrating a method for manufacturing the structure of FIG. 3.

※ Explanation of code for main part of drawing

401 silicon substrate 402 gate oxide film

403: first polysilicon layer 404: stress buffer layer (WSi _x )

405: second polysilicon layer 406: diffusion barrier tungsten nitride film

407 tungsten layer 408 hard mask nitride film

400: gate stack

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a polymetal gate electrode and a method of manufacturing the same, and more particularly, to prevent film stress of a gate stack by interposing a stress buffer buffer layer in the middle of the polysilicon layer for the gate electrode. A reduced gate electrode structure and a method of manufacturing the same.

As is well known, the gate electrode of the MOSFET has been formed using poly-silicon (Poly-Si) in the manufacturing process of semiconductor devices such as DRAM, but the doped polysilicon alone is high due to the miniaturization of the gate line width due to high integration. The resistivity characteristic makes it difficult to apply to devices requiring fast operation.

This is a serious problem due to the high integration of semiconductor devices, and to improve this problem, for example, WSi _x / Poly-Si and a high melting point metal silicide film such as tungsten silicide (WSi _x ) and titanium silicide, Gate electrode technology of the same polycide structure has emerged. However, the gate electrode of the polyside structure also has a limitation in improving the operation speed of the ultra-high density semiconductor device because the sheet resistance rapidly increases at the gate line width of 90nm or less.

Recently, as a technology using a high melting point metal such as tungsten (W) as a gate electrode, a polymetal gate electrode structure such as a W / WN _x / Poly-Si structure is used. The W / WN _x / Poly-Si gate electrode structure has the advantage of having a resistance as low as 1/10 as compared to the WSi _x / Poly-Si gate electrode structure. In the W / WN _x / Poly-Si gate electrode structure, the tungsten nitride film WN _x is a diffusion barrier formed between the upper layer tungsten (W) and the lower layer polysilicon (Poly-Si).

On the other hand, the W / WN _x / Poly-Si gate electrode structure has the advantage of low resistivity, but the mechanical stress caused by the hard mask nitride film deposited on the tungsten (W) is severely adversely affected the device. There is a problem affecting.

The above-described prior art and its problems will be described in detail with reference to the accompanying drawings.

1A to 1D are cross-sectional views for manufacturing a W / WN _x / Poly-Si gate electrode as a method of manufacturing a polymetal gate electrode according to the prior art.

Referring to FIG. 1A, a gate oxide layer 102, a gate polysilicon layer 103, a diffusion barrier tungsten nitride layer (WN _x ) 104, and a gate tungsten layer 105 are formed on a silicon substrate 101. Laminate in order.

Subsequently, referring to FIG. 1B, a hard mask nitride layer 106 is formed on the tungsten layer 105.

Here, the reason why the hard mask nitride layer 106 is used is that a self-aligned contact (SAC) process, which is an essential manufacturing process of a DRAM device, is possible, and recently, the gate line width is less than 10 nm. As the gap between gate lines adjacent to each other is also narrowed, a loading effect occurs during the self-aligned contact etching, and thus a very thick hard mask nitride layer is required to increase the process margin.

Subsequently, the photoresist pattern 107 for gate patterning is formed as shown in FIG. 1C, and the mask insulating layer 106, the tungsten layer 105, and tungsten nitride are formed using the photoresist pattern 107 as an etching barrier as shown in FIG. 1D. The layer (WN _x ) 104 and the polysilicon layer 103 are etched to form the gate stack 100.

Thereafter, a gate reoxidation process is performed, and a typical series of transistor manufacturing processes such as LDD ion implantation, gate sidewall spacer formation, and source / drain ion implantation processes are performed to complete MOSFET fabrication.

In the gate stack of the structure as described above, that is, a hard mask (HM NIT) / W / WN _x / Poly-Si, a hard mask nitride layer (HM NIT) and a polysilicon layer (T-Si) in which tungsten (W) is an upper and lower layers are used. ) to the stress caused by each stress and subsequent tear-time thermal expansion difference between the thin film is greatly caused, define subsequent breaks in the gate stack of the _{HM NIT / W / WN x /} Poly-Si maximum temperature due to the thermal expansion coefficient of the size more than doubled compared to the Therefore, stress induced leakage current (SILC) is rapidly deteriorated, which indicates that the stress induced in the gate stack by the subsequent thermal process adversely affects the gate oxide layer underneath, thereby causing a decrease in the refresh characteristics and reliability of the device. it means.

2 shows a problem of the prior art, while GOI deterioration due to film stress of a hard mask material is hardly observed in the gate structure of WSi _x / WN _x / Poly-Si, while W / WN _x / Poly- It can be seen that the polymetal gate structure of Si is very severe.

The present invention is to solve the above-mentioned problems of the prior art, a gate electrode structure that reduces the film stress of the gate stack by interposing a buffer layer for stress buffer in the middle of the polysilicon layer for the gate electrode and its It is an object to provide a manufacturing method.

Polymetal gate electrode of the present invention for achieving the above object is a gate insulating layer formed on a semiconductor substrate; And a gate stack patterned on the gate insulating layer, the gate stack having a lower polysilicon layer and an upper layer hardmask insulating layer and a metal layer interposed therebetween, wherein the polysilicon layer is in the middle of the layer. And a stress buffer layer interposed therebetween.

In the present invention, the stress buffer layer preferably uses a metal silicide layer such as a tungsten silicide layer. In particular, when a CVD tungsten silicide layer or an ALD tungsten silicide layer formed in a gas atmosphere containing florin (F) is used, it is helpful to improve the reliability of the gate oxide film by florin.

In addition, it is preferable that the thickness of the stress buffer layer is thinner than that of each of the polysilicon layers above and below, in order to reduce the interfacial reaction with the polysilicon layer in a subsequent thermal process.

As the metal layer, any one selected from the group of W, Mo, Ta, Ti, Ru, Ir, and Pt can be used, and the diffusion barrier layer can be interposed between the polysilicon layer and the metal layer. The barrier layer is any one selected from the group of WN _x , Si ₃ N ₄ , SiN _x , TiAl _x N _y , HfN _x , ZrN _x , TaN _x , TiN _x , AlN _x , TaSi _x N _y , TiAl _x N _y It is possible to use.

In addition, the polymetal gate electrode manufacturing method of the present invention, forming a gate insulating layer on a semiconductor substrate; Sequentially stacking a first polysilicon layer, a stress buffer layer, and a second polysilicon layer on the gate insulating layer; Stacking a metal layer and a hard mask insulating layer on the second polysilicon layer; And etching the stacked layers by a gate electrode mask and an etching process to form a gate stack.

The stress buffer layer is preferably formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD) in a gas atmosphere containing florin (F).

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to explain in detail enough that a person having ordinary skill in the art to which the present invention pertains can easily carry out the technical idea of the present invention, the most preferred embodiments of the present invention and the effects thereof are referred to the accompanying drawings. This will be described.

3 is a cross-sectional view illustrating a polymetal gate electrode structure according to a preferred embodiment of the present invention, and FIGS. 4A to 4G are cross-sectional views illustrating a method for manufacturing the structure of FIG. 3.

Referring to FIG. 3, a gate oxide film 302 is formed on a silicon substrate 301, and a gate stack 300 is patterned on the gate oxide film 102.

The gate stack 300 includes a first polysilicon layer 303 and a second polysilicon layer 305 and a tungsten silicide layer 304 which is a stress buffer layer interposed therebetween, and is stacked on the second polysilicon layer. A tungsten layer 307 and a hard mask nitride layer 308.

The stress buffer tungsten silicide layer 304 has a thickness thinner than that of the first and second polysilicon layers.

In addition, the gate stack 300 further includes a tungsten nitride film (WN _x ) 306 as a diffusion barrier layer between the second polysilicon layer 305 and the tungsten layer 307. The diffusion barrier tungsten nitride film 304 ) Can be replaced with any one selected from the group of Si ₃ N ₄ , SiN _x , TiAl _x N _y , HfN _x , ZrN _x , TaN _x , TiN _x , AlN _x , TaSi _x N _y , TiAl _x N _y . The diffusion barrier tungsten nitride film 306 may be omitted in the present invention.

The tungsten layer 307 may be replaced with any one metal selected from the group of Mo, Ta, Ti, Ru, Ir, and Pt.

A method for manufacturing the structure of FIG. 3 will be described with reference to FIGS. 4A-4G.

Referring to FIG. 4A, a gate oxide film 402 and a first polysilicon layer 403 or more are stacked on the silicon substrate 401.

Here, the gate oxide layer 402 may use an insulating film containing nitrogen, such as an oxynitride instead of SiO ₂ , and may include Hf, Zr, Al, Ta, Ti, Ce, Pr, and La. It is also possible to use high-k insulating materials such as metal oxides. In addition, poly-Si _1-x Ge _x (x = 0.01 to 0.99) may be used instead of the polysilicon layer 403.

Next, referring to FIG. 4B, a thin tungsten silicide film 404 is formed on the first polysilicon layer 403. The tungsten silicide film 404 is a stress buffer layer having a thickness of about 50 to 350 GPa, and the formation method may be CVD, ALD, PVD, or the like, but chemical vapor deposition such as CVD or ALD is preferable. WF ₆ can be used as a tungsten source gas, because a small amount of florin is diffused into the gate oxide film to help the reliability of the gate oxide film. Specifically, the conditions for forming the tungsten silicide film 404 by CVD or ALD use WF ₆ as the tungsten source gas and SiH ₄ or SiCl ₂ H ₂ as the silicon source gas at a temperature of 550 ° C. or lower.

Next, as shown in FIG. 4C, a second polysilicon layer 405 is formed on the tungsten silicide layer 404. The thickness of the second polysilicon layer 405 is about 50 to 350 GPa and can be replaced by a poly-Si _1-x Ge _x (x = 0.01 to 0.99) layer.

Next, as shown in FIG. 4D, a tungsten nitride layer (WN _x ) 406 which is a diffusion barrier is formed.

The diffusion barrier tungsten nitride layer 406 is selected from the group of Si ₃ N ₄ , SiN _x , TiAl _x N _y , HfN _x , ZrN _x , TaN _x , TiN _x , AlN _x , TaSi _x N _y , TiAl _x N _y any one to replace the possible, Si ₃ to N ₄ when using a diffusion barrier second polyester in a manner that the plasma treatment or heat treatment in an atmosphere containing nitrogen on the silicon layer 405 to form the Si ₃ N ₄ It is possible.

Next, a tungsten layer 407 is formed as a metal layer on the diffusion barrier tungsten nitride layer 406 as shown in FIG. 4E. The tungsten layer can be formed to a thickness of 100 to 700 GPa.

Subsequently, the hard mask nitride layer 408 is formed as shown in FIG. 4F, and the gate stack 400 is formed by a gate mask and an etching process as shown in FIG. 4F.

Subsequently, although not shown in the figure, gate reoxidation is performed to heal damage during gate etching and to improve the characteristics of the gate oxide film. In order to oxidize the silicon substrate 401 and the polysilicon layer 403 while suppressing abnormal oxidation of the tungsten layer 405 during reoxidation, plasma oxidation using RF or a microwave wave is performed. It is preferable to use a gas such as Ar, Kr, etc. in forming plasma, form RF and microwave below 15 GHz, and apply gas such as H ₂ , D ₂ , O ₂ at a temperature of 450 ° C. or lower. Can be. Also applicable is a selective oxidation process which oxidizes in an H ₂ -rich / O ₂ atmosphere.

After that, a series of conventional processes for transistor manufacturing, such as LDD ion implantation, gate sidewall spacer formation, and source / drain ion implantation processes, are performed to complete MOSFET fabrication.

The inventive concept of the gate structure having the stress buffer layer is applicable to a damascene structure in which a gate is formed in the insulating film groove, unlike the stack structure described above. Although specifically described above, it should be noted that the above-described embodiments are for illustrative purposes only and are not intended to be limiting. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention proposes a polymetal gate electrode having a structure in which a stress buffer layer is inserted in a middle portion of a polysilicon layer in order to alleviate film stress caused by a hard mask and stress caused by subsequent thermal processes. The MOSFET of the polymetal gate electrode structure according to the present invention is very useful for low power devices or devices requiring precise operating characteristics by minimizing deterioration of device characteristics caused by stress.

Claims (11)

A gate insulating layer formed on the semiconductor substrate; And A gate stack patterned on the gate insulating layer, The gate stack includes a lower polysilicon layer and an upper layer hard mask insulating layer and a metal layer interposed therebetween, The polysilicon layer is characterized in that the intervening stress buffer layer in the middle of the layer A polymetal gate electrode having a stress buffer layer. The method of claim 1, The stress buffer layer is a polymetal gate electrode having a stress buffer layer, characterized in that the tungsten silicide layer. The method according to claim 1 or 2, The stress buffer layer is a polymetal gate electrode having a stress buffer layer, characterized in that the thickness of the upper, lower than each of the polysilicon layer. The method according to claim 1 or 2, The metal layer is a metal gate electrode having a stress buffer layer, characterized in that any one selected from the group of W, Mo, Ta, Ti, Ru, Ir and Pt. The method according to claim 1 or 2, Further comprising a diffusion barrier layer interposed between the polysilicon layer and the metal layer, the diffusion barrier layer is WN _x , Si ₃ N ₄ , SiN _x , TiAl _x N _y , HfN _x , ZrN _x , TaN _x , A polymetal gate electrode having a stress buffer layer comprising any one selected from the group consisting of TiN _x , AlN _x , TaSi _x N _y , TiAl _x N _y . Forming a gate insulating layer on the semiconductor substrate; Sequentially stacking a first polysilicon layer, a stress buffer layer, and a second polysilicon layer on the gate insulating layer; Stacking a metal layer and a hard mask insulating layer on the second polysilicon layer; And Etching the stacked layers by using a gate electrode mask and an etching process to form a gate stack Polymetal gate electrode manufacturing method comprising a. The method of claim 6, The stress buffer layer is a tungsten silicide layer, characterized in that the polymetal gate electrode manufacturing method having a stress buffer layer. The method according to claim 6 or 7, And forming the stress buffer layer by chemical vapor deposition (CVD) or atomic layer deposition (ALD) in a gas atmosphere containing florin (F). The method according to claim 6 or 7, The stress buffer layer is a polymetal gate electrode manufacturing method, characterized in that formed to a thickness of 50 ~ 350Å thinner than each layer of the first and second polysilicon layers. The method according to claim 6 or 7, The metal layer is a polymetal gate electrode manufacturing method, characterized in that using any one selected from the group of W, Mo, Ta, Ti, Ru, Ir and Pt. The method according to claim 6 or 7, The method of claim 1, further comprising forming a diffusion barrier layer between the second polysilicon layer and the metal layer.

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