CN101257000A - 包括通孔的结构及其制造方法 - Google Patents

包括通孔的结构及其制造方法 Download PDF

Info

Publication number
CN101257000A
CN101257000A CNA200810074179XA CN200810074179A CN101257000A CN 101257000 A CN101257000 A CN 101257000A CN A200810074179X A CNA200810074179X A CN A200810074179XA CN 200810074179 A CN200810074179 A CN 200810074179A CN 101257000 A CN101257000 A CN 101257000A
Authority
CN
China
Prior art keywords
dielectric layer
metal
copper
liner
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA200810074179XA
Other languages
English (en)
Other versions
CN101257000B (zh
Inventor
丹尼尔·C·埃德尔斯坦
野上毅
王平川
王允愈
杨智超
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Core Usa Second LLC
GlobalFoundries Inc
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CN101257000A publication Critical patent/CN101257000A/zh
Application granted granted Critical
Publication of CN101257000B publication Critical patent/CN101257000B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明提供一种结构及相关方法，该结构包括在铜布线和介电层的无衬界面处的难熔金属环。在一实施例中，一结构包括：铜布线，与其上的介电层具有无衬界面；通孔，从该铜布线向上延伸穿过该介电层；以及难熔金属环，从该通孔的侧面部分沿该无衬界面延伸。难熔金属环通过改善通孔周围的界面来防止电迁移造成的狭缝空缺，并防止空缺成核出现在通孔附近。另外，在通孔和介电层无衬界面附近存在空缺时，难熔金属环提供电冗余。

Description

包括通孔的结构及其制造方法
技术领域
本发明总地涉及集成电路(IC)芯片制造，更特别地，涉及在铜布线和介电层无衬界面处具有难熔金属环的包括通孔的结构及相关方法。
背景技术
在集成电路芯片制造工业中，电迁移(electromigration，EM)导致的故障是高级线后端(back end of line)技术的主要关注点。特别地，早期电迁移导致的故障显著减小产品芯片在操作条件下的预期电流限制。一种电迁移导致的故障是“线损耗(line-depletion)”。如图1A-1C所示，线损耗电迁移包括从向上延伸的通孔10向下流入下面的金属布线12的电流。当电流流动时，原子移动造成“狭缝空缺(slit void)”故障14(图1C)，其例如始于通孔10与无衬界面18之间的位点(site)16(图1B)，无衬界面18在金属线12与其上的介电层20之间。众所周知，该狭缝空缺会在电路运行期间在电迁移条件下造成非常早的故障，因为不用多长时间就可形成这样的小空缺。图1A和1B中的箭头显示了电迁移流的方向(例如电迁移期间的原子流)。一般地，狭缝空缺故障14(图1C)在通孔10与金属布线12之间的界面附近的缺陷位点16(图1B)开始(或成核)，且生长到通孔10的底部22，直到它延伸在整个界面上且造成电开口24，如图1C所示。狭缝空缺故障14出现在有(如图所示)或没有通孔刨槽(via gouging)(即通孔10延伸到金属线12中)的结构中。
发明内容
本发明提供一种结构及相关方法，该结构包括在金属布线和介电层的无衬界面处的难熔金属环(collar)。在一实施例中，一结构包括：与其上的介电层具有无衬界面的铜布线；通孔，从该铜布线向上延伸穿过该介电层；以及难熔金属环，从该通孔的侧面部分沿着该无衬界面延伸。难熔金属环通过改善通孔周围的界面来防止电迁移造成的狭缝空缺，并防止空缺成核出现在通孔附近。另外，在通孔和介电层无衬界面附近存在空缺时，难熔金属环提供电冗余。
本发明的第一方面提供一种结构，包括：与其上的介电层具有无衬界面的铜布线；通孔，从该铜布线向上延伸穿过该介电层；以及难熔金属环，从该通孔的侧面部分沿着该无衬界面延伸。
本发明的第二方面提供一种方法，包括：提供铜布线于第一介电层中；在该铜布线上形成第二介电层，以在该铜布线和该第二介电层之间形成无衬界面；形成开口贯穿该第二介电层且到该铜布线中；在该第二介电层下从该开口产生底切(undercut)；形成难熔金属环于该底切中；以及用金属填充该开口以形成通孔。
本发明的第三方面提供一种结构，包括：与其上的介电层具有无衬界面的铜布线；通孔，从该铜布线向上延伸穿过该介电层，该通孔包括在该铜布线中的基本截头圆锥形的部分；在该通孔周围的第一衬垫，该第一衬垫包括难熔金属；以及难熔金属环，从该通孔的侧面部分沿着该无衬界面延伸。
本发明的示例性方面用于解决这里描述的问题和/或未论述的其他问题。
附图说明
本发明的这些和其他特征将从下面结合附图对本发明各方面的详细描述变得更易于理解，附图示出本发明的各实施例，附图中：
图1A-1C示出其中电迁移导致故障的常规通孔和金属布线界面；
图2示出根据本发明实施例的结构。
图3-7示出形成图2结构的方法。
注意，本发明的附图不是按比例的。该附图仅意在表现本发明的一般方面，因此不应认为是对本发明的范围的限定。在附图中，类似的附图标记代表类似的元件。
具体实施方式
图2示出根据本发明实施例的结构100。结构100包括通孔110，其从金属布线112(例如铜)向上延伸穿过介电层120。在一实施例中，通孔110包括在金属布线112中的基本截头圆锥形的部分122。但是，本发明的教导不限于此类通孔。金属布线112位于另一介电层124中，且包括在金属布线112和介电层124之间的衬垫(liner)126。衬垫126可包括任意现在已知的或将来开发的金属扩散阻挡材料，例如钽、氮化钽、钛、氮化钛、钨、氮化钨、钌、氮化钌等。但是需要注意的是，衬垫126仅沿着金属布线112的底部128和侧面130将金属布线112和介电层124分隔开。因此，金属布线112包括与其上的介电层120的无衬界面118。
介电层120包括与金属布线112形成无衬界面118的阻挡层132、以及在阻挡层132上的层间电介质134。阻挡层132可包括任意现在已知的或将来开发的介电阻挡层，诸如碳化硅(SiC)、氮化硅(Si3N4)、二氧化硅(SiO2)、氮或氢掺杂的碳化硅(SiC(N，H))等。层间电介质134可包括任意现在已知的或将来开发的多孔或非多孔层间电介质材料，诸如硅氧化物，硅氮化物，氢化碳氧化硅(SiCOH)，倍半硅氧烷(silsesquioxane)，包含硅、碳、氧、和/或氢原子的碳掺杂氧化物(即有机硅酸酯)，热固性聚芳醚(polyaryleneether)，SiLK(可从Dow Chemical Corporation得到的聚芳醚)，JSR(可从JSR Corporation得到的旋涂含硅碳聚合物材料)，其它低介电常数(＜3.9)材料，或其层。
结构100还包括难熔金属环140，其从通孔110的侧面142部分沿着无衬界面118延伸。另外，第一衬垫144可形成于通孔110周围，第一衬垫144包括相同的难熔金属。在一实施例中，该难熔金属包括钌，但是，其它难熔金属诸如钽(Ta)、钛(Ti)、钨(W)、铱(Ir)、铑(Rh)、铂(Pt)等或其混合物也可被采用。通孔110还可包括在通孔周围的第二衬垫146，其中第二衬垫146包括至少一金属扩散阻挡层150(即衬垫)和为形成通孔110的金属158做种的金属籽层152。在一实施例中，金属158包括铜，但是，其它金属诸如铜合金、铝(Al)、铝合金、银(Ag)等可被采用。金属扩散阻挡层(或多层)150可包括例如钽/氮化钽、钛/氮化钛、钨/氮化钨、钌/氮化钌等。当金属158是铜时，金属籽层152可包括铜(Cu)或其它合金材料，例如铜、铜铝合金、以及其它铜合金诸如铜铱、铜镍、和/或铜钌。
难熔金属环140和金属布线112界面有一慢电迁移路径，其中电迁移流(即电迁移期间的原子流)被迫向下至金属布线112中(如箭头所示)而不是聚集在无衬界面118附近(如图1A-1B所示)。特别地，由于界面处的粘合相较于金属和电介质基阻挡层132材料间的粘合有很大的提高，因此金属布线112(例如铜)和难熔金属环140之间的界面对电迁移导致的空缺形成有很强的抵抗性。因此，在通孔110周围的无衬界面118处的局部电迁移流大大减少。另外，由于难熔金属环140只形成于通孔110周围，而不是直接在通孔110和金属线112接触处的下方，所以通孔接触电阻不受该特征影响。即使空缺形成于通孔110之下，通孔110周围的难熔金属环140也用作冗余导电路径，因此防止结构100电断开。
结构100还减少了热循环故障。热循环测试是反映产品经历的温度偏移的必要的可靠性试验。由于金属和它周围电介质(或多种电介质)之间的热膨胀不匹配，故障或裂纹会发生在通孔和金属布线界面处，导致电断开。难熔金属环140(机械上远强于铜)用作锚(anchor)以防止通孔110在应力下拉出金属布线112。
下面将结合图3-7描述形成结构100(图2)的方法的实施例。要理解的是，多种方法可被采用，下面是一个示例。在图3中，使用任意现在已知的或将来开发的技术将金属布线112设置在介电层124中。例如，将介电层124沉积在基板(未显示)上，图案化(包括光刻)一掩膜(未显示)，蚀刻该掩膜，蚀刻一开口，沉积衬垫126，沉积一金属(布线112)，以及化学机械抛光(CMP)。如前所指，衬垫126仅沿着金属布线112的底部128和侧面130将金属布线112和介电层124分隔开。
图3还示出在金属布线112(和介电层124)上方形成介电层120以形成金属布线112和介电层124之间的无衬界面118。如前所指，介电层120可包括与金属布线112形成无衬界面118的介电阻挡层132(例如氮化硅)、以及位于介电阻挡层132之上的层间电介质134(例如SiCOH)。图3还示出形成穿过介电层134和介电阻挡层132到金属布线112的开口160。尽管开口160示出为使用双镶嵌工艺形成，但是需要理解的是，可以使用单个通孔开口(单镶嵌工艺)。如果需要，开口160还可延伸到金属布线112中。
图4示出将开口160延伸到金属布线112中的可选工艺即气体溅射工艺。在该溅射工艺中使用的气体可包括氩(Ar)、氦(He)、氖(Ne)、氙(Xe)、氮(N2)、氢(H2)、氨(NH3)、二氮烯(N2H2)、或其混合物中的一种，优选地包括氩。基本截头圆锥形的开口162产生在金属布线112中。
图5示出在介电层120下(即在介电阻挡层132下)从开口160制作底切164。在一实施例中，制作底切可包括进行各向异性湿法/干法蚀刻。
图6示出例如通过原子层沉积(ALD)和/或化学气相沉积(CVD)在底切164(图5)中形成难熔金属环140。如前所指，难熔金属可包括钽(Ta)、钛(Ti)、钨(W)、钌(Ru)、铱(Ir)、铑(Rh)和/或铂(Pt)等，或其混合物。图6还示出在用金属填充开口160(图2)之前在开口160内形成第一衬垫144。在该情况下，第一衬垫144可包括用于难熔金属环140的难熔金属。
图7示出在用金属填充开口160之前在开口160内形成第二衬垫146。如前所指，第二衬垫146可包括至少一金属扩散阻挡层150(即衬垫)和金属籽层152。如前所指，金属扩散阻挡层(或多层)150可包括例如钽/氮化钽、钛/氮化钛、钨/氮化钨、钌/氮化钌等。又如前所指，当金属158(图2)是铜时，金属籽层152可包括例如铜，铜铝合金，以及其它铜合金诸如铜铱、铜镍、和/或铜钌。
回到图2，用金属158例如诸如铜的金属填充开口160(图7)以形成通孔110，以及任何必需的平坦化完成结构100。需要理解的是，本发明的教导可在IC芯片的层级内重复多次，且可对于IC芯片的不同层级重复多次。
上述结构和方法用于集成电路芯片的制造。所得集成电路芯片可由制造者以原始晶片(raw wafer)形式(即作为具有多个未封装芯片的单个晶片)作为裸芯片分发，或以封装形式分发。在后一情况中，该芯片安装在单芯片封装中(诸如塑料载具，用连接到主板(motherboard)或其它更高级别载具的引线)，或安装在多芯片封装中(诸如具有任一表面互联或两表面互连、或者埋设互连的陶瓷载具)。在任何情况中，芯片又与其它芯片、离散电路元件、和/或其它信号处理装置集成，作为(a)中间产品诸如主板或(b)最终产品的一部分。最终产品可以是包括集成电路芯片的任意产品，涵盖从玩具和其他低端应用到具有显示器、键盘或其它输入设备、以及中央处理器的高级计算机产品。
前面对本发明各方面的描述是用于示例和说明，其无意详尽本发明或将本发明限制到所公开的精确形式，显然地，许多修改或变型是可行的。这样的修改和变型，其对本领域技术人员而言是显然的，意在被包括在所附权利要求定义的本发明的范围内。

Claims (20)

1.一种结构，包括：
金属布线，与其上的介电层具有无衬界面；
通孔，从该金属布线向上延伸穿过该介电层；以及
难熔金属环，从该通孔的侧面部分沿着该无衬界面延伸。
2.如权利要求1所述的结构，其中该通孔包括在该金属布线中的基本截头圆锥形的部分。
3.如权利要求1所述的结构，其中该难熔金属环包括选自由钽(Ta)、钛(Ti)、钨(W)、钌(Ru)、铱(Ir)、铑(Rh)和铂(Pt)中的至少一种构成的组的材料。
4.如权利要求1所述的结构，还包括在该通孔周围的第一衬垫，该第一衬垫包括该难熔金属。
5.如权利要求4所述的结构，还包括在该通孔周围形成第二衬垫，该第二衬垫包括至少一金属扩散阻挡层和金属籽层。
6.如权利要求5所述的结构，其中该至少一金属扩散阻挡层选自包括钽、氮化钽、钛、氮化钛、钨、氮化钨、钌、以及氮化钌的组。
7.如权利要求5所述的结构，其中该金属布线包括铜，该金属籽层选自包括铜、铜铝、铜铱、铜镍、以及铜钌中的至少一种的组。
8.如权利要求1所述的结构，其中该金属布线位于另一介电层中，且还包括在该金属布线和该另一介电层之间的衬垫。
9.如权利要求1所述的结构，其中该介电层包括与该金属布线形成无衬界面的阻挡层、以及在该阻挡层上方的层间电介质。
10.一种方法，包括：
设置金属布线于第一介电层中；
在该金属布线上形成第二介电层以在该金属布线和该第二介电层之间形成无衬界面；
形成穿过该第二介电层且到该金属布线中的开口；
在该第二介电层下从该开口制作底切；
形成难熔金属环于该底切中；以及
用金属填充该开口以形成通孔。
11.如权利要求10所述的方法，其中所述设置包括仅沿该金属布线的底部和侧面设置衬垫于该金属布线和该第一介电层之间。
12.如权利要求10所述的方法，其中所述形成开口包括进行镶嵌工艺以在该第一介电层中形成所述开口，且进行气体溅射工艺以将该开口延伸到该金属布线中。
13.如权利要求10所述的方法，其中所述制作底切包括进行各向异性湿法/干法蚀刻。
14.如权利要求10所述的方法，还包括在所述填充之前形成第一衬垫于该开口中，该第一衬垫包括该难熔金属。
15.如权利要求14所述的方法，还包括在所述填充之前形成第二衬垫于该开口中，该第二衬垫包括至少一金属扩散阻挡层和金属籽层。
16.如权利要求15所述的方法，其中该至少一金属扩散阻挡层选自包括钽、氮化钽、钛、氮化钛、钨、氮化钨、钌、以及氮化钌的组。
17.如权利要求15所述的方法，其中该金属布线包括铜，该金属籽层选自包括铜、铜铝、铜铱、铜镍、以及铜钌中的至少一种的组。
18.一种结构，包括：
铜布线，与其上的介电层具有无衬界面；
通孔，从该铜布线向上延伸穿过该介电层，该通孔包括在该铜布线中的基本截头圆锥形的部分；
在该通孔周围的第一衬垫，该第一衬垫包括难熔金属；以及
难熔金属环，从该通孔的侧面部分沿该无衬界面延伸。
19.如权利要求18所述的结构，其中该难熔金属环包括选自由钽(Ta)、钛(Ti)、钨(W)、钌(Ru)、铱(Ir)、铑(Rh)和铂(Pt)中的至少一种构成的组的材料。
20.如权利要求18所述的结构，其中该介电层包括与该铜布线形成该无衬界面的阻挡层、以及在该阻挡层上方的层间电介质。
CN200810074179XA 2007-02-27 2008-02-27 包括通孔的结构及其制造方法 Expired - Fee Related CN101257000B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/679,483 US7859113B2 (en) 2007-02-27 2007-02-27 Structure including via having refractory metal collar at copper wire and dielectric layer liner-less interface and related method
US11/679,483 2007-02-27

Publications (2)

Publication Number Publication Date
CN101257000A true CN101257000A (zh) 2008-09-03
CN101257000B CN101257000B (zh) 2010-06-09

Family

ID=39714952

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200810074179XA Expired - Fee Related CN101257000B (zh) 2007-02-27 2008-02-27 包括通孔的结构及其制造方法

Country Status (2)

Country Link
US (1) US7859113B2 (zh)
CN (1) CN101257000B (zh)

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102760722A (zh) * 2011-04-27 2012-10-31 南亚科技股份有限公司 包含铜-铝电路连线的集成电路结构及其制备方法
CN103663344A (zh) * 2012-09-12 2014-03-26 快捷半导体(苏州)有限公司 包括多材料填充物的改进型硅通孔
CN103681555A (zh) * 2012-08-29 2014-03-26 台湾积体电路制造股份有限公司 增加对电迁移的阻力的结构
US9278845B2 (en) 2010-09-18 2016-03-08 Fairchild Semiconductor Corporation MEMS multi-axis gyroscope Z-axis electrode structure
US9278846B2 (en) 2010-09-18 2016-03-08 Fairchild Semiconductor Corporation Micromachined monolithic 6-axis inertial sensor
US9352961B2 (en) 2010-09-18 2016-05-31 Fairchild Semiconductor Corporation Flexure bearing to reduce quadrature for resonating micromachined devices
US9444404B2 (en) 2012-04-05 2016-09-13 Fairchild Semiconductor Corporation MEMS device front-end charge amplifier
US9488693B2 (en) 2012-04-04 2016-11-08 Fairchild Semiconductor Corporation Self test of MEMS accelerometer with ASICS integrated capacitors
US9586813B2 (en) 2010-09-18 2017-03-07 Fairchild Semiconductor Corporation Multi-die MEMS package
US9618361B2 (en) 2012-04-05 2017-04-11 Fairchild Semiconductor Corporation MEMS device automatic-gain control loop for mechanical amplitude drive
US9625272B2 (en) 2012-04-12 2017-04-18 Fairchild Semiconductor Corporation MEMS quadrature cancellation and signal demodulation
US9856132B2 (en) 2010-09-18 2018-01-02 Fairchild Semiconductor Corporation Sealed packaging for microelectromechanical systems
CN107564850A (zh) * 2016-07-01 2018-01-09 中芯国际集成电路制造(北京)有限公司 互连结构及其制造方法
US10050155B2 (en) 2010-09-18 2018-08-14 Fairchild Semiconductor Corporation Micromachined monolithic 3-axis gyroscope with single drive
US10060757B2 (en) 2012-04-05 2018-08-28 Fairchild Semiconductor Corporation MEMS device quadrature shift cancellation
US10065851B2 (en) 2010-09-20 2018-09-04 Fairchild Semiconductor Corporation Microelectromechanical pressure sensor including reference capacitor

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4423379B2 (ja) * 2008-03-25 2010-03-03 合同会社先端配線材料研究所 銅配線、半導体装置および銅配線の形成方法
US20110127673A1 (en) * 2009-12-01 2011-06-02 International Business Machines Corporation Wiring structure and method
CN102097363A (zh) * 2009-12-15 2011-06-15 中芯国际集成电路制造(上海)有限公司 金属互连方法
US9177917B2 (en) 2010-08-20 2015-11-03 Micron Technology, Inc. Semiconductor constructions
US8569888B2 (en) 2011-05-24 2013-10-29 International Business Machines Corporation Wiring structure and method of forming the structure
US8772934B2 (en) 2012-08-28 2014-07-08 Taiwan Semiconductor Manufacturing Company, Ltd. Aluminum interconnection apparatus
DE102012215233A1 (de) * 2012-08-28 2014-03-06 Robert Bosch Gmbh Halbleitervorrichtung und Herstellungsverfahren für eine Halbleitervorrichtung
US10032712B2 (en) * 2013-03-15 2018-07-24 Taiwan Semiconductor Manufacturing Company Limited Semiconductor structure
US9349608B2 (en) * 2013-12-13 2016-05-24 Globalfoundries Inc. Methods of protecting a dielectric mask layer and related semiconductor devices
US9455184B2 (en) 2014-06-17 2016-09-27 Taiwan Semiconductor Manufacturing Company, Ltd. Aluminum interconnection apparatus
US10361119B1 (en) * 2018-04-30 2019-07-23 International Business Machines Corporation Enlarged contact area structure using noble metal cap and noble metal liner
US10818545B2 (en) * 2018-06-29 2020-10-27 Sandisk Technologies Llc Contact via structure including a barrier metal disc for low resistance contact and methods of making the same
US10741441B2 (en) 2018-09-28 2020-08-11 International Business Machines Corporation Collar formation for chamfer-less and chamfered vias

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5300813A (en) * 1992-02-26 1994-04-05 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
US5695810A (en) * 1996-11-20 1997-12-09 Cornell Research Foundation, Inc. Use of cobalt tungsten phosphide as a barrier material for copper metallization
EP1093163B1 (en) * 1997-03-25 2004-11-24 Amitec - Advanced Multilayer Interconnect Technologies Ltd. Electronic interconnect structure
US5969425A (en) * 1997-09-05 1999-10-19 Advanced Micro Devices, Inc. Borderless vias with CVD barrier layer
US6522013B1 (en) * 1997-12-18 2003-02-18 Advanced Micro Devices, Inc. Punch-through via with conformal barrier liner
US6046104A (en) * 1998-05-15 2000-04-04 Advanced Micro Devices, Inc. Low pressure baked HSQ gap fill layer following barrier layer deposition for high integrity borderless vias
US6194755B1 (en) * 1998-06-22 2001-02-27 International Business Machines Corporation Low-resistance salicide fill for trench capacitors
US6333560B1 (en) * 1999-01-14 2001-12-25 International Business Machines Corporation Process and structure for an interlock and high performance multilevel structures for chip interconnects and packaging technologies
US6306749B1 (en) * 1999-06-08 2001-10-23 Winbond Electronics Corp Bond pad with pad edge strengthening structure
US6342733B1 (en) * 1999-07-27 2002-01-29 International Business Machines Corporation Reduced electromigration and stressed induced migration of Cu wires by surface coating
US6613664B2 (en) * 2000-12-28 2003-09-02 Infineon Technologies Ag Barbed vias for electrical and mechanical connection between conductive layers in semiconductor devices
KR100385227B1 (ko) * 2001-02-12 2003-05-27 삼성전자주식회사 구리 다층 배선을 가지는 반도체 장치 및 그 형성방법
JP4198906B2 (ja) * 2001-11-15 2008-12-17 株式会社ルネサステクノロジ 半導体装置および半導体装置の製造方法
KR100413828B1 (ko) * 2001-12-13 2004-01-03 삼성전자주식회사 반도체 장치 및 그 형성방법
US6975032B2 (en) * 2002-12-16 2005-12-13 International Business Machines Corporation Copper recess process with application to selective capping and electroless plating
US7122462B2 (en) * 2003-11-21 2006-10-17 International Business Machines Corporation Back end interconnect with a shaped interface
JP4832807B2 (ja) * 2004-06-10 2011-12-07 ルネサスエレクトロニクス株式会社 半導体装置
US7282802B2 (en) * 2004-10-14 2007-10-16 International Business Machines Corporation Modified via bottom structure for reliability enhancement

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9856132B2 (en) 2010-09-18 2018-01-02 Fairchild Semiconductor Corporation Sealed packaging for microelectromechanical systems
US10050155B2 (en) 2010-09-18 2018-08-14 Fairchild Semiconductor Corporation Micromachined monolithic 3-axis gyroscope with single drive
US9586813B2 (en) 2010-09-18 2017-03-07 Fairchild Semiconductor Corporation Multi-die MEMS package
US9352961B2 (en) 2010-09-18 2016-05-31 Fairchild Semiconductor Corporation Flexure bearing to reduce quadrature for resonating micromachined devices
US9278845B2 (en) 2010-09-18 2016-03-08 Fairchild Semiconductor Corporation MEMS multi-axis gyroscope Z-axis electrode structure
US9278846B2 (en) 2010-09-18 2016-03-08 Fairchild Semiconductor Corporation Micromachined monolithic 6-axis inertial sensor
US10065851B2 (en) 2010-09-20 2018-09-04 Fairchild Semiconductor Corporation Microelectromechanical pressure sensor including reference capacitor
CN102760722A (zh) * 2011-04-27 2012-10-31 南亚科技股份有限公司 包含铜-铝电路连线的集成电路结构及其制备方法
US9488693B2 (en) 2012-04-04 2016-11-08 Fairchild Semiconductor Corporation Self test of MEMS accelerometer with ASICS integrated capacitors
US9444404B2 (en) 2012-04-05 2016-09-13 Fairchild Semiconductor Corporation MEMS device front-end charge amplifier
US10060757B2 (en) 2012-04-05 2018-08-28 Fairchild Semiconductor Corporation MEMS device quadrature shift cancellation
US9618361B2 (en) 2012-04-05 2017-04-11 Fairchild Semiconductor Corporation MEMS device automatic-gain control loop for mechanical amplitude drive
US9625272B2 (en) 2012-04-12 2017-04-18 Fairchild Semiconductor Corporation MEMS quadrature cancellation and signal demodulation
CN103681555A (zh) * 2012-08-29 2014-03-26 台湾积体电路制造股份有限公司 增加对电迁移的阻力的结构
CN103681555B (zh) * 2012-08-29 2016-10-05 台湾积体电路制造股份有限公司 增加对电迁移的阻力的结构
US9425328B2 (en) 2012-09-12 2016-08-23 Fairchild Semiconductor Corporation Through silicon via including multi-material fill
US9802814B2 (en) 2012-09-12 2017-10-31 Fairchild Semiconductor Corporation Through silicon via including multi-material fill
CN103663344A (zh) * 2012-09-12 2014-03-26 快捷半导体(苏州)有限公司 包括多材料填充物的改进型硅通孔
CN103663344B (zh) * 2012-09-12 2017-02-15 快捷半导体(苏州)有限公司 包括多材料填充物的改进型硅通孔
CN107564850A (zh) * 2016-07-01 2018-01-09 中芯国际集成电路制造(北京)有限公司 互连结构及其制造方法
CN107564850B (zh) * 2016-07-01 2020-07-07 中芯国际集成电路制造(北京)有限公司 互连结构及其制造方法

Also Published As

Publication number Publication date
US20080203570A1 (en) 2008-08-28
US7859113B2 (en) 2010-12-28
CN101257000B (zh) 2010-06-09

Similar Documents

Publication Publication Date Title
CN101257000B (zh) 包括通孔的结构及其制造方法
US10804147B2 (en) Semiconductor device with reduced via resistance
US10256186B2 (en) Interconnect structure having subtractive etch feature and damascene feature
US10573593B2 (en) Metal interconnects for super (skip) via integration
US7259463B2 (en) Damascene interconnect structure with cap layer
JP3057054B2 (ja) 銅線の多層相互接続を形成する方法
US9202743B2 (en) Graphene and metal interconnects
CN101390204B (zh) 用于金属集成的新颖结构和方法
CN101651130B (zh) 用于互连结构的含氮金属帽
US9293412B2 (en) Graphene and metal interconnects with reduced contact resistance
KR101382564B1 (ko) 에어갭을 갖는 층간 절연막의 형성 방법
CN100369247C (zh) 改进的hdp氮化物基ild盖层
CN101438404A (zh) 制造用于互连应用的可靠过孔接触
KR20100037015A (ko) 보이드 형성을 방지하는 무전해 도금법을 이용한 전기 배선의 형성 방법
US20120098133A1 (en) Structure and metallization process for advanced technology nodes
US7732924B2 (en) Semiconductor wiring structures including dielectric cap within metal cap layer
US10361119B1 (en) Enlarged contact area structure using noble metal cap and noble metal liner
US7955971B2 (en) Hybrid metallic wire and methods of fabricating same
JP2010010656A (ja) 半導体装置およびその製造方法
US7436040B2 (en) Method and apparatus for diverting void diffusion in integrated circuit conductors
KR20040075746A (ko) 반도체 장치 및 그 제조 방법
KR100924556B1 (ko) 반도체 소자의 금속배선 및 그 형성방법
US20090108450A1 (en) Interconnect structure and method of making same
KR20080001905A (ko) 반도체 소자의 금속 배선 형성방법
US9761529B2 (en) Advanced metallization for damage repair

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20171208

Address after: Grand Cayman, Cayman Islands

Patentee after: GLOBALFOUNDRIES INC.

Address before: American New York

Patentee before: Core USA second LLC

Effective date of registration: 20171208

Address after: American New York

Patentee after: Core USA second LLC

Address before: New York grams of Armand

Patentee before: International Business Machines Corp.

CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20100609

Termination date: 20190227