CN101242160A - Two-stage operational amplifier with class ab output stage - Google Patents
Two-stage operational amplifier with class ab output stage Download PDFInfo
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- CN101242160A CN101242160A CNA2008100048024A CN200810004802A CN101242160A CN 101242160 A CN101242160 A CN 101242160A CN A2008100048024 A CNA2008100048024 A CN A2008100048024A CN 200810004802 A CN200810004802 A CN 200810004802A CN 101242160 A CN101242160 A CN 101242160A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
- H03F3/45183—Long tailed pairs
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0261—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the polarisation voltage or current, e.g. gliding Class A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/30—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor
- H03F3/3001—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor with field-effect transistors
- H03F3/3022—CMOS common source output SEPP amplifiers
- H03F3/3023—CMOS common source output SEPP amplifiers with asymmetrical driving of the end stage
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
- G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45311—Indexing scheme relating to differential amplifiers the common gate stage of a cascode dif amp being implemented by multiple transistors
Abstract
An operational amplifier includes a differential amplifier including an active load, a current mirror including a first branch and a second branch, a first switch connected between a first power source and an output node and switched in response to a voltage of a first output terminal of the differential amplifier, a first bias circuit to control an amount of a reference current flowing in the first branch in response to a voltage of a second output terminal of the differential amplifier, a second bias circuit to control a voltage of the second branch in which a mirror current flows, in response to a voltage of the first output terminal, a second switch connected between the output node and a second power source and switched in response to a voltage of the second branch, and a capacitor connected between the output node and the first output terminal.
Description
CROSS-REFERENCE TO RELATED PATENT
The application enjoys the priority of following application: korean patent application No.10-2007-0013429 that submits in Korea S Department of Intellectual Property on February 8th, 2007 and the korean patent application No.10-2007-0082244 that submits in Korea S Department of Intellectual Property on August 16th, 2007, its whole disclosures are included in this literary composition with way of reference.
Technical field
The present invention openly relates to operational amplifier (operational amplifier, OP AMP), more particularly, relates to the two-stage OP AMP with AB class output stage.
Background technology
Rail-to-rail (rail-to-rail) OP AMP is mainly used in acquisition and is driving general electronic installation for example in the output buffer of the source electrode driver of LCD (LCD) panel, the output voltage that fully changes from the ground voltage to the supply voltage.But,, cause comprising that the size of output buffer of the source electrode driver of a plurality of rail-to-rail OP AMP also increases because the layout dimension (layout size) of rail-to-rail OPAMP is very big.Therefore, along with the trend of the size that reduces source electrode driver, need reduce to be used for the size of OP AMP of the output buffer of source electrode driver.
Although two-stage OP AMP is used to the output buffer of source electrode driver, because the falling characteristic of two-stage OP AMP is relatively poor, therefore, between the signal of source electrode driver output, producing deviation.Therefore, because these deviations can produce vertical pattern or waveform patterns in LCD panel image shows.In addition, when two-stage OP AMP replaces rail-to-rail OP AMP, when being used to the output buffer of source electrode driver, can make the falling characteristic or the rising characteristic deterioration of the output voltage of output buffer.
Because the output stage of rail-to-rail OP AMP is according to the operation of AB class, therefore rail-to-rail OP AMP can operate its output loading according to AB class (or recommending class).Because output stage one side of two-stage OP AMP, for example the pull-up circuit of being realized by PMOSFET moves as commonsource amplifier, and opposite side, for example the pull-down circuit of being realized by NMOSFET moves as current source, therefore, be difficult to the output loading of the two-stage OP AMP of operation A category-B (or recommending class).Therefore, need layout dimension little and can improve the OP AMP of falling characteristic or rising characteristic.
Summary of the invention
In order to solve above-mentioned and/or other problems, exemplary embodiments of the present invention provides two-stage OP AMP, and its layout dimension is little, has improved falling characteristic or rising characteristic, and can move as rail-to-rail amplifier.
According to exemplary embodiments of the present invention, a kind of operational amplifier comprises: differential amplifier comprises active load; Current mirror comprises first branch road and second branch road; First switch is connected between first power supply and the output node, and in response to the voltage of first output of differential amplifier and switch; First biasing circuit in response to the voltage of second output of differential amplifier, is controlled the reference current amount that flows through in first branch road; Second biasing circuit in response to the voltage of first output, is controlled the voltage of second branch road that flows through image current; Second switch is connected between output node and the second source, and, switch in response to the voltage of second branch road; And capacitor is connected between the output node and first output.
Current mirror is the NMOSFET current mirror, and first power source voltage is higher than the voltage of second source, and first switch is PMOSFET, and second switch is NMOSFET.Current mirror is the PMOSFET current mirror, and first power source voltage is lower than the voltage of second source, and first switch is NMOSFET, and second switch is PMOSFET.
According to exemplary embodiments of the present invention, a kind of operational amplifier comprises: first current mirror is connected between first power supply and first Control Node, and comprises reference current branch road and image current branch road; Second current mirror is connected between the second source and second Control Node; The first transistor is connected between first power supply and the output node, and in response to the voltage of first Control Node conduction and cut-off; Transistor seconds is connected between output node and the second source, and in response to the voltage of second Control Node conduction and cut-off; Transistor is right, is connected to second source by a current source, and, comprise that its drain electrode is connected to the 3rd transistor of reference current branch road and the 4th transistor that its drain electrode is connected to the image current branch road; Biasing circuit is connected between first Control Node and second Control Node, and, in response to a plurality of biasing control voltages, bias voltage is provided for the first transistor and transistor seconds; And capacitor is connected between image current branch road and the output node.
First power source voltage is higher than the voltage of second source, and first current mirror is PMOSFET cascade (cascode) current mirror, and second current mirror is the NMOSFET current mirror, and the first transistor is PMOSFET, and second, third and the 4th transistor are NMOSFET.
First power source voltage is lower than the voltage of second source, and first current mirror is the NMOSFET common-source common-gate current mirror, and second current mirror is the PMOSFET current mirror, and the first transistor is NMOSFET, and second, third and the 4th transistor are PMOSFET.Operational amplifier is the unity gain buffer that is connected to output node and the 3rd transistorized grid.Operational amplifier is implemented as the part of display drive apparatus.
Description of drawings
According to the description of carrying out below in conjunction with accompanying drawing, can understand exemplary embodiments of the present invention in more detail, wherein:
Fig. 1 is what show according to exemplary embodiments of the present invention, comprises the block diagram of the display unit of source electrode driver;
Fig. 2 is the block diagram of the source electrode driver that uses in the device of Fig. 1;
Fig. 3 is the circuit diagram of the output buffer that uses in the driver of Fig. 2;
Fig. 4 is according to exemplary embodiments of the present invention, has the circuit diagram of the OP AMP of NMOSFET input stage;
Fig. 5 is according to exemplary embodiments of the present invention, has the circuit diagram of the OP AMP of PMOSFET input stage;
Fig. 6 is according to exemplary embodiments of the present invention, has the circuit diagram of the OP AMP of NMOSFET input stage; And
Fig. 7 is according to exemplary embodiments of the present invention, has the circuit diagram of the OP AMP of PMOSFET input stage.
Embodiment
Hereinafter, by reference description of drawings exemplary embodiments of the present invention, describe the present invention in detail.In the accompanying drawings, identical label is represented identical key element.
Fig. 1 is what show according to exemplary embodiments of the present invention, comprises the block diagram of the display unit of source electrode driver.With reference to Fig. 1, flat display apparatus 50 such as LCD (LCD) device, PDP (plasma display) device or OLED (organic light emitting diode, Organic Light Emitting Diode) device and so on comprises LCD panel 100, source electrode driver 200 and gate drivers 300.LCD panel 100 comprises many gate lines G 1-Gm (wherein, " m " is natural number), many source electrode line S1-Sn (wherein, " n " is natural number) and a plurality of pixel (not shown).
Fig. 2 is the block diagram of the source electrode driver 200 of Fig. 1.With reference to Fig. 2, comprise controller 205, polarity control circuit 210, latch cicuit 220, digital to analog converter (DAC) 230 and output buffer 240 as the source electrode driver 200 of display drive apparatus.According to the type of display unit, can within the source electrode driver 200 or outside realize controller 205.Controller 205 generates polarity control signal CSP and latch signal LS.
When a plurality of liquid crystal of giving LCD panel 100 provided constant voltage continuously, liquid crystal hardened and deterioration probably.Therefore, in order to prevent the liquid crystal sclerosis of LCD panel 100, polarity control circuit 210 is the polarity of control figure view data DATA in response to polarity control signal CSP.Polarity controlled refer to,, make the phase overturn (reversing) of DID DATA according to the common electric voltage that in one-period, offers LCD panel 100.
Latch cicuit 220 latchs the DID DATA from polarity control circuit 210 outputs in response to latch signal LS.DAC 230 will be converted to a plurality of aanalogvoltage Vang from the DID DATA of latch cicuit 220 outputs.Can make the phase place of each aanalogvoltage Vang anti-phase in one-period according to common electric voltage.
According in the exemplary embodiments of the present invention shown in Fig. 4-Fig. 7, output buffer 240 comprises a plurality of OPAMP.Among 240 couples of aanalogvoltage Vang of output buffer each is amplified or buffer memory, and the voltage of each amplification is outputed to one corresponding among the source electrode line S1-Sn.Output buffer 240 in the source electrode driver 200 comprises a plurality of rail-to-rail OP AMP, is used for the voltage of amplification or buffer memory is outputed to each bar of S1-Sn.
But, output buffer 240 according to exemplary embodiments does not use general rail-to-rail OP AMP, but comprise the two-stage OP AMP 260 of Fig. 4 or Fig. 6 and the two-stage OP AMP 270 of Fig. 5 or Fig. 7, wherein, two-stage OP AMP 260 has the NMOSFET input stage that is used to improve falling characteristic, and two-stage OP AMP 270 has the PMOSFET input stage that is used to improve rising characteristic.
Fig. 3 is the circuit diagram of output buffer shown in Figure 2.In Fig. 3, for ease of explanation, output buffer 240 comprises first switch unit 250, two the two- stage OP AMP 260 and 270 and second switch units 280.Two- stage OP AMP 260 and 270 output voltage OUT1 and OUT2 are fed back to each negative input end (-) respectively, thereby play unity gain buffer.
Many incoming line INL1 and INL2 receive a plurality of analog signal Vang1 and Vang2 respectively, and in one-period, for example in the cycle of polarity control signal, the phase place of Vang1 and Vang2 is by anti-phase.The polarity of each among hypothetical simulation voltage Vang1 and the Vang2 is anti-phase by complementation.
The first aanalogvoltage Vang1 that is input to the first incoming line INL1 is for outputing to the aanalogvoltage of the first source electrode line Sx by an OP AMP 260.The second aanalogvoltage Vang2 that is input to the second incoming line INL2 is for outputing to the aanalogvoltage of the second source electrode line Sy by the 2nd OPAMP 270.
The one OP AMP 260 with the phase place among aanalogvoltage Vang1 and the Vang2 not by anti-phase any of being cached among source electrode line Sx and the Sy.Here, " x " and " y " is greater than 1 and less than the natural number of " n ", and " y " is bigger by 1 than " x ".The 2nd OPAMP 270 with the phase place among aanalogvoltage Vang1 and the Vang2 by anti-phase any of being cached among source electrode line Sx and the Sy.
In the output buffer 240 of present embodiment, an OP AMP 260 is for having the two-stage OP AMP of the NMOSFET input stage that is used to improve falling characteristic, and the 2nd OP AMP 270 is for having the two-stage OP AMP of the PMOSFET input stage that is used to improve rising characteristic.
In response to a plurality of first switch-over control signal CTRL1 in the one-period, first switch unit 250 is connected the first incoming line INL1 with the first input end (+) of an OP AMP 260, the second incoming line INL2 is connected with the first input end (+) of the 2nd OP AMP 270.In addition, in response to the first switch-over control signal CTRL1 in this cycle, first switch unit 250 is with first input end (+) interconnection of the first incoming line INL1 and the 2nd OP AMP 270, with first input end (+) interconnection of the second incoming line INL2 and an OP AMP260.
In response to a plurality of second switch-over control signal CTRL2 in the one-period, second switch unit 280 is connected the output of an OP AMP 260 with the first source electrode line Sx, and the output of the 2nd OP AMP 270 is connected with the second source electrode line Sy.In addition, in response to the second switch-over control signal CTRL2 in this cycle, second switch unit 280 is with the output and the second source electrode line Sy interconnection of an OP AMP 260, with the output and the first source electrode line Sx interconnection of the 2nd OPAMP 270.
In addition, in response to a plurality of the 3rd switch-over control signal CTRL2 in the one-period, second switch unit 280 is connected the first source electrode line Sx with the second source electrode line Sy, to carry out electric charge shared (charge sharing) operation.
In the output buffer 240 of Fig. 3, the aanalogvoltage that is had noninverting phase place by 260 couples of OP AMP carries out buffer memory, improving falling characteristic, and carries out buffer memory by the aanalogvoltage that 270 couples of the 2nd OP AMP have an inverted phases, to improve rising characteristic, vice versa.
For example, handover operation according to first switch unit 250, when the first aanalogvoltage Vang1 has noninverting phase place, and the second aanalogvoltage Vang2 is when having inverted phases, the first incoming line INL1 is connected to the first input end of an OP AMP 260, and the second incoming line INL2 is connected to the first input end of the 2nd OPAMP 270.In this case, according to the handover operation of second switch unit 280, the output of an OP AMP 260 is connected to the first source electrode line Sx, and the output of the 2nd OP AMP 270 is connected to the second source electrode line Sy.
But, handover operation according to first switch unit 250, when the first aanalogvoltage Vang1 has inverted phases, and the second aanalogvoltage Vang2 is when having noninverting phase place, the first incoming line INL1 is cross connected to the first input end of the 2nd OP AMP 270, and the second incoming line INL2 is cross connected to the first input end of an OP AMP 260.In this exemplary embodiments, according to the handover operation of second switch unit 280, the output of an OP AMP 260 is cross connected to the second source electrode line Sy, and the output of the 2nd OP AMP 270 is cross connected to the first source electrode line Sx.
Fig. 4 is according to exemplary embodiments of the present invention, has the circuit diagram of the OP AMP of NMOSFET input stage.With reference to Fig. 4, the OP AMP 260 with NMOSFET input stage 261 comprises current mirror 263, first biasing circuit 265, second biasing circuit 267 and the output stage 269 with compensation condenser C1.
Comprise that the first collapsible cascade OP AMP circuit of NMOSFET input stage 261, current mirror 263, first biasing circuit 265 and second biasing circuit 267 can improve the falling characteristic of output voltage OUT1.NMOSFET input stage 261 comprises being connected to by current source 3 provides for example a plurality of NMOSFET 1 and 2 and a plurality of PMOSFET 4 and 5 of constituting current mirror of the power supply of ground voltage VSS of second electric power, wherein, NMOSFET input stage 261 is also referred to as differential amplifier or the current mirror type differential amplifier with active load, and current source 3 is controlled by biasing control voltage VB1.
NMOSFET 1 and 2 and current source 3 constituted differential amplifier.When an OP AMP 260 was used as unity gain buffer, as Fig. 3 finding, the output N0 and second input (-) interconnected.This differential amplifier amplifies the difference between the first input voltage INP1 and the second input voltage INN1, thereby generates differential output current.The current mirror 263 that comprises NMOSFET 6 and 7 comprises first branch road and second branch road, wherein, flows through reference current in first branch road, flows through in second branch road by reference current being carried out the image current that mirror image obtained (mirror current).
With reference to Fig. 3 and Fig. 4, the operation of an OP AMP260 that is used to improve the falling characteristic of output voltage OUT1 is described as follows.At first, when the voltage level of first input signal INP1 high level or the VDD voltage level for example when low level or VSS that is higher than the second input signal INN1 for example, the NMOSFET1 conducting, and NMOSFET 2 ends.Therefore, the voltage level conversion of the first output ODA1 is a low level, and the voltage level conversion of the second output ODA2 is a high level.Therefore, because PMOSFET 12 conductings of output stage 269, the output voltage OUT1 of output N0 is converted to high level.
When the voltage level conversion of the first input signal INP1 was high level, the major part of the first bias current I1 by current source 3 flow through NMOSFET 1.In addition, along with the voltage level increase of the second output ODA 2, source electrode-grid voltage of the PMOSFET 10 of first biasing circuit 265 also increases.Along with source electrode-drain current increase of PMOSFET 10, drain electrode-source current of the NMOSFET 7 of first branch road of current mirror 263 is that reference current also increases.By current mirror, drain electrode-source current of the NMOSFET 6 of second branch road of current mirror 263 is that image current increases.
But when the voltage level of the second output ODA 2 increased, source electrode-grid voltage of PMOSFET 5 also reduced, and therefore, source electrode-drain current of PMOSFET 5 is that reference current reduces.By current mirror, source electrode-drain current of the PMOSFET 4 of current mirror 263 is that image current reduces.The result, along with by from the magnitude of current that flows through NMOSFET 1 and the magnitude of current sum that flows through PMOSFET 4, deducting the corresponding electric charge of electric current that the magnitude of current that flows through NMOSFET 6 obtains to compensation condenser C1 charging, form forward transition (forward slew).In this exemplary embodiments, forward transition can refer to change to the situation of 0.75VDD or change to the situation of VDD from 0.75VDD from 0.5VDD.
Along with making the voltage OUT1 of output N0 increase sooner, formed the forward transition of output voltage OUT1 by the charging charge among electric current or the compensation condenser C1.Therefore, the OP AMP 260 according to this exemplary embodiments has good rising characteristic.In addition, when the voltage level of the first output ODA1 reduced, source electrode-grid voltage of the PMOSFET 8 of second biasing circuit 267 reduced, so source electrode-drain current of PMOSFET 8 reduces.
But, because according to current mirror, drain electrode-source current of the NMOSFET 6 of second branch road of current mirror 263 is that image current must be constant, therefore needs drain electrode-source current of the NMOSFET 9 of increase second biasing circuit 267.Owing to need the grid-source voltage of the NMOSFET9 of increase second biasing circuit 267, so the voltage of first node ND1 reduces.
When the voltage level of first node ND1 reduced, NMOSFET 13 was ended rapidly, and the electric current that flows to second source from output node N0 is cut off rapidly, had therefore further improved the rising characteristic of output voltage OUT1.The voltage level of the first output ODA1 increases with the voltage level of first node ND1 or reduces.
Secondly, when the voltage level of the first input signal INP1 low level voltage level for example during high level that is lower than the second input signal INP1 for example, NMOSFET 1 ends, and NMOSFET 2 conductings.Therefore, the voltage level conversion of the first output ODA1 is a high level, and the voltage level conversion of the second output ODA2 is a low level.Therefore, the PMOSFET 12 of output stage 269 ends, and the NMOSFET13 conducting.As a result, the voltage OUT1 of output N0 is converted to ground voltage VSS.
At this moment, the major part of bias current I1 flows through NMOSFET 2.Therefore, along with the voltage level of the second output ODA 2 reduces, source electrode-grid voltage of the PMOSFET 10 of first biasing circuit 265 reduces.Therefore, along with source electrode-drain current of PMOSFET 10 reduces, drain electrode-source current of the NMOSFET 7 of first branch road of current mirror 263 is that reference current reduces.According to current mirror, the drain electrode-source current of second branch road of current mirror 263 is that image current reduces.
But along with the voltage level of the second output ODA 2 reduces, the source electrode of the PMOSFET 5 of the current mirror of differential amplifier-grid voltage increases, and therefore, source electrode-drain current of PMOSFET 5 is that reference current increases.According to current mirror, drain electrode-source current of the PMOSFET 4 of the current mirror of differential amplifier is that image current increases.As a result, must flow to compensation condenser C1 from the first output ODA1 corresponding to the magnitude of current of the PMOSFET 4 of the current mirror that flows through differential amplifier and the magnitude of current that flows through the difference between the magnitude of current of NMOSFET 6 of current mirror 263.
Therefore,, form the reverse transition (reverse slew) of output voltage OUT1, therefore improved the falling characteristic of output voltage OUT1 along with the output voltage OUT1 of output N0 reduces rapidly.Oppositely transition can refer to that first voltage changes to the situation of 0.75 VDD or changes to the situation of 0.5 VDD from 0.75 VDD from VDD.In addition, when the voltage level of the first output ODA1 increased, the source electrode of the PMOSFET 8 of second biasing circuit 267-grid voltage increased, and therefore, the source electrode of PMOSFET 8-drain current increases.
But based on current mirror, drain electrode-source current of the NMOSFET 6 of second branch road of current mirror 263 is that image current must be constant.Therefore drain electrode-source current of the NMOSFET 9 of second biasing circuit 267 need reduce.Because the grid-source voltage of the NMOSFET 9 of second biasing circuit 267 need reduce, so the voltage of first node ND1 increases.The voltage level of the first output ODA1 increases with the voltage level of first node ND1.
Because the voltage level of the first output ODA1 increases, PMOSFET 12 is ended rapidly, therefore, is cut off rapidly to the electric current that output node N0 provides from first power supply.In addition, because the voltage level of first node ND1 increases, NMOSFET 13 is switched on, so the voltage level of output node N0 is reduced to first power source voltage, for example ground voltage VSS.Therefore, further improved according to the falling characteristic of the output voltage OUT1 of the OP AMP 260 of this exemplary embodiments.
As described above with reference to Figure 4, because the grid voltage of the NMOSFET 13 of output stage 269 and the grid voltage of PMOSFET 12 increase together or reduce, can as for example rail-to-rail OP AMP of AB class OP AMP, carry out the operation of AB class as an OP AMP 260 according to the two-stage OPAMP of this exemplary embodiments.
Fig. 5 is according to exemplary embodiments of the present invention, has the circuit diagram of the OP AMP of PMOSFET input stage.With reference to Fig. 5, the 2nd OP AMP 270 with PMOSFET input stage 271 comprises current mirror 273, first biasing circuit 275, second biasing circuit 277 and the output stage 279 with compensation condenser C2.
Comprise that the second collapsible cascade OP AMP circuit of PMOSFET input stage 271, current mirror 273, first biasing circuit 275 and second biasing circuit 277 can improve the rising characteristic of output voltage OUT1.PMOSFET input stage 271 comprises a plurality of PMOSFET 14 and 15 and a plurality of NMOSFET 17 and 18 of constituting current mirror that are connected to first power supply by current source 16, wherein, PMOSFET input stage 271 is also referred to as differential amplifier or the current mirror type differential amplifier with active load, and current source 16 is setovered controls the control of voltage VB6.
First biasing circuit 275 is connected between the second output ODA4 and the 4th node ND4 of differential amplifier, and the 4th node ND4 is connected to first branch road of current mirror 273.First biasing circuit 275 comprises PMOSFET 23 and the NMOSFET 24 that is connected in parallel between the second output ODA4 and the 4th node ND4, and, in response to the voltage of biasing control voltage VB9 and the VB10 and the second output ODA4, the reference current amount that flows through in first branch road is regulated.
With reference to Fig. 3 and Fig. 5, the operation that is used to improve the falling characteristic of the 2nd OP AMP 270 is described as follows.At first, when the voltage level of the first input signal INP2 low level voltage level for example during high level that is lower than the second input signal INN2 for example, PMOSFET 14 conductings of differential amplifier, PMOSFET15 ends.Therefore, because the voltage level conversion of the first output ODA3 is a high level, most of bias current I2 flows through PMOSFET 14, so NMOSFET 15 conductings.Because the voltage level conversion of the 3rd node ND3 is a high level, so PMOSFET 26 ends.Therefore, the voltage level OUT2 of output N0 is converted to low level.
When the voltage level of the first output ODA3 increased, the grid-source voltage of the NMOSFET22 of second biasing circuit 277 reduced.Therefore, drain electrode-source current of NMOSFET 22 reduces.In addition, because the voltage level of the second output ODA4 reduces, make the grid-source voltage of NMOSFET 18 of first branch road of current mirror of differential amplifier reduce, therefore, drain electrode-source current of NMOSFET 18 is that reference current reduces.By current mirror, drain electrode-source current of the NMOSFET 17 of the current mirror of differential amplifier is that image current reduces.
With flow to compensation condenser C2 by from the magnitude of current sum of the magnitude of current of the PMOSFET 14 that flows through differential amplifier and the current mirror that flows through differential amplifier, deducting the corresponding magnitude of current of the magnitude of current that the magnitude of current that flows through current mirror 273 obtains from the first output ODA3.
So the output voltage OUT2 of output N0 reduces rapidly, therefore form the reverse transition of output voltage OUT2.Therefore, the 2nd OP AMP 270 according to this exemplary embodiments has good falling characteristic.In addition, when the ODA4 of second output voltage level reduced, the grid-source voltage of the NMOSFET 24 of first biasing circuit 275 increased, thereby the drain electrode of NMOSFET 24-source current increases.Therefore, the image current of current mirror 273 and reference current increase.
Because the voltage level of the first output ODA3 increases, therefore drain electrode-source current of the NMOSFET 22 of second biasing circuit 277 reduces.Because the image current of current mirror 273 must be a steady state value always, so need increase as voltage source voltage, the 3rd node ND 3 of the PMOSFET 21 of second biasing circuit 277.Along with the voltage increase of the 3rd node ND 3, PMOSFET 26 ends rapidly, and therefore the electric current that provides from first power supply is cut off rapidly.Therefore, further improved rising characteristic according to the 2nd OP AMP 270 of this exemplary embodiments.
Secondly, when the voltage level conversion of the first input signal INP2 is a high level, and the voltage level conversion of the second input signal INN2 is when being low level, and PMOSFET 14 ends, and PMOSFET 15 conductings.Because the voltage level conversion of the first output ODA3 is a low level, so NMOSFET 25 ends.Because the voltage level conversion of the 3rd node ND 3 is a low level, so PMOSFET 26 conductings.Therefore, the output voltage OUT2 of output N0 is converted to high level, i.e. the first power source voltage level.
In this exemplary embodiments, the major part of bias current I2 flows through PMOSFET 15.Along with the voltage level conversion of the first output ODA3 is a low level, the grid-source voltage of the NMOSFET 22 of second biasing circuit 277 increases.Therefore, the drain electrode of NMOSFET 22-source current increases.Along with the voltage level increase of the second output ODA4, the grid-source voltage of the NMOSFET 18 of the current mirror of differential amplifier also increases, so the drain electrode of NMOSFET 18-source current increases.Because current mirror, the drain electrode of NMOSFET 17-source current increases.
Along with corresponding to the magnitude of current of the NMOSFET 17 of the current mirror that flows through differential amplifier and the magnitude of current that flows through the difference between the magnitude of current of PMOSFET 19 of current mirror 273 to compensation condenser C2 charging, form forward transition.Therefore, improved the rising characteristic of output voltage OUT2.Along with the voltage level of the first output ODA3 reduces, NMOSFET 25 is ended rapidly.Therefore, along with the electric current that flows to second source from output node N0 is cut off rapidly, further improved rising characteristic according to the voltage OUT2 of the 2nd OP AMP 270 of this exemplary embodiments.
As above described with reference to Fig. 5, because the grid voltage of NMOSFET 25 and the grid voltage of PMOSFET26 change along equidirectional, therefore the 2nd OP AMP as two-stage OP AMP can carry out the operation of AB class as AB class OP AMP.
Fig. 6 is according to exemplary embodiments of the present invention, has the circuit diagram of the OP AMP of NMOSFET input stage.With reference to Fig. 6, the two-stage OP AMP 260 with NMOSFET input stage 261 ' comprises first current mirror 262, second current mirror 264, biasing circuit 266, output stage and compensation condenser C1.
NMOSFET input stage 261 ' with differential amplifier structure comprises by NMOSFET N3 and is connected to differential NMOSFET N1 and the N2 that second source promptly provides the power supply of ground voltage VSS.According to biasing control voltage VB1, the NMOSFET N3 of current source function is carried out in control.
Differential amplifier amplifies the difference between input voltage INP1 and the INN1, and exports differential output current.When an OP AMP 260 was used as unity gain buffer, as shown in Figure 3, output voltage OUT1 was fed back to second input (-) of an OP AMP 260.That is, the drain electrode of NMOSFETN1 is connected to the image current branch road of first current mirror 262, for example, wherein flows through the branch road of source electrode-drain current of PMOSFETP7.The drain electrode of NMOSFET N2 is connected to the reference current branch road, for example, wherein flows through the branch road of source electrode-drain current of PMOSFET P5.
Can be connected first power supply by first current mirror 262 that the PMOSFET common-source common-gate current mirror is realized for example provides between the power supply and the first Control Node PU of supply voltage VDD, and comprises reference current branch road and image current branch road.That is, realize first current mirror 262 by a plurality of PMOSFET P4, P5, P6 and P7, reference current flows through the reference current branch road, flows through the image current branch road by the image current that reference current is carried out the mirror image acquisition.
Can be connected between the second source and the second Control Node PD by second current mirror 264 that the NMOSFET current mirror is realized.Second current mirror 264 comprises: wherein flow through the reference current branch road of reference current, for example wherein flow through the branch road of drain electrode-source current of NMOSFET N5; And, wherein flow through the image current branch road of image current, for example wherein flow through the branch road of drain electrode-source current of NMOSFET N7.
Output stage comprises and is connected the first transistor P10 between the first power vd D and the output node NO and is connected transistor seconds N10 between output node NO and the second source.The first transistor P10 can be realized by PMOSFET, and transistor seconds N10 can be realized by NMOSFET.Biasing circuit 266 is connected between first current mirror 262 and second current mirror 264, and, in response to biasing control voltage VB7 and the voltage of VB8, the first Control Node PU and the voltage of the second Control Node PD, bias voltage is provided among the first and second transistor P10 and the N10 each.
The first biasing circuit 266A is called floating current source.The second biasing circuit 266B provides bias voltage among the first and second transistor P10 and the N10 each, makes the first and second transistor P10 and N10 to move according to the AB class.In response to the voltage of the first Control Node PU, the first transistor P10 conduction and cut-off.In response to the voltage of the second Control Node PD, transistor seconds N10 conduction and cut-off.Compensation condenser C1 is connected between the image current branch road and output node NO of first current mirror 262.
Fig. 7 is according to exemplary embodiments of the present invention, has the circuit diagram of the OP AMP of PMOSFET input stage.With reference to Fig. 7, the two-stage OP AMP 270 with PMOSFET input stage 271 ' comprises first current mirror 272, second current mirror 274, biasing circuit 276, output stage and compensation condenser C2.
PMOSFET input stage 271 ' with differential amplifier structure comprises by PMOSFET P3 and is connected to differential PMOSFET P1 and the P2 that first power supply promptly provides the power supply of supply voltage VDD.According to biasing control voltage VB2, the PMOSFET P3 of current source function is carried out in control.
Differential amplifier amplifies the difference between input voltage INP2 and the INN2, and exports differential output current.When the 2nd OP AMP 270 is used as unity gain buffer, output voltage OUT2 is provided for second input (-) of the 2nd OP AMP270.That is, the drain electrode of PMOSFET P1 is connected to the image current branch road of first current mirror 272.The drain electrode of PMOSFET P2 is connected to the reference current branch road.
Can be connected second source by first current mirror 272 that the NMOSFET common-source common-gate current mirror is realized for example provides between the power supply and the second Control Node PD of ground voltage VSS, and comprises reference current branch road and image current branch road.That is, realize first current mirror 272 by a plurality of NMOSFET N4, N5, N6 and N7, reference current flows through the reference current branch road, and image current promptly flows through the image current branch road by the electric current that reference current is carried out the mirror image acquisition.
Can be connected between first power supply and the first Control Node PU by second current mirror 274 that the PMOSFET current mirror is realized.Second current mirror 274 comprises: wherein flow through the reference current branch road of reference current, for example the branch road that is connected to of the 8th node ND8; And, wherein flow through the image current branch road of image current, for example the branch road that is connected to of the first Control Node PU.
Output stage comprises and is connected the first transistor P10 between first power supply and the output node NO and is connected transistor seconds N10 between output node NO and the second source.The first transistor P10 can be realized that transistor seconds N10 can be realized by NMOSFET by PMOSFET.
The first biasing circuit 276A is called floating current source.The second biasing circuit 276B provides bias voltage among the first and second transistor P10 and the N10 each, makes the first and second transistor P10 and N10 to move according to the AB class.In response to the voltage of the first Control Node PU, the first transistor P10 conduction and cut-off.In response to the voltage of the second Control Node PD, transistor seconds N10 conduction and cut-off.Compensation condenser C2 is connected between the image current branch road and output node NO of first current mirror 272.
As above described with reference to Fig. 6 and Fig. 7, the grid voltage of the grid voltage of PMOSFET P10 and NMOSFET N10 changes along equidirectional, can carry out the operation of AB class as the OPAMP 260 of two-stage OP AMP or the 2nd OP AMP 270 as AB class OP AMP.For convenience of explanation, first power supply, second source, first switch and the second switch that use have in the above description exemplarily been provided.OP AMP according to exemplary embodiments has played falling characteristic or the rising characteristic of improving output voltage, reduces the effect of layout area simultaneously.
Although the present invention specifically illustrates and describes with reference to its exemplary embodiments, but, persons skilled in the art should be appreciated that, under the situation that does not break away from the spirit and scope of the present invention that limit as claims, can carry out various modifications to it in form and details.
Claims (9)
1. operational amplifier comprises:
Differential amplifier comprises active load;
Current mirror comprises first branch road and second branch road;
First switch is connected between first power supply and the output node, and in response to the voltage of first output of described differential amplifier and switch;
First biasing circuit in response to the voltage of second output of described differential amplifier, is controlled the reference current amount that flows through in described first branch road;
Second biasing circuit in response to the voltage of described first output, is controlled the voltage of described second branch road that flows through image current;
Second switch is connected between described output node and the second source, and, switch in response to the voltage of described second branch road; And
Capacitor is connected between described output node and described first output.
2. operational amplifier as claimed in claim 1, wherein, described current mirror is the NMOSFET current mirror, and described first power source voltage is higher than the voltage of described second source, and described first switch is PMOSFET, and described second switch is NMOSFET.
3. operational amplifier as claimed in claim 1, wherein, described current mirror is the PMOSFET current mirror, and described first power source voltage is lower than the voltage of described second source, and described first switch is NMOSFET, and described second switch is PMOSFET.
4. operational amplifier comprises:
First current mirror is connected between first power supply and first Control Node, and, comprise reference current branch road and image current branch road;
Second current mirror is connected between the second source and second Control Node;
The first transistor is connected between described first power supply and the output node, and, the conduction and cut-off in response to the voltage of described first Control Node;
Transistor seconds is connected between described output node and the described second source, and, the conduction and cut-off in response to the voltage of described second Control Node;
Transistor is right, is connected to described second source by current source, and comprises that its drain electrode is connected to the 3rd transistor of described reference current branch road and the 4th transistor that its drain electrode is connected to described image current branch road;
Biasing circuit is connected between described first Control Node and second Control Node, and, in response to a plurality of biasing control voltages, bias voltage is provided for described the first transistor and described transistor seconds; And
Capacitor is connected between described image current branch road and the described output node.
5. operational amplifier as claimed in claim 4, wherein, described first power source voltage is higher than the voltage of described second source, described first current mirror is the PMOSFET common-source common-gate current mirror, described second current mirror is the NMOSFET current mirror, described the first transistor is PMOSFET, and described second, third and the 4th transistor are NMOSFET.
6. operational amplifier as claimed in claim 4, wherein, described first power source voltage is lower than the voltage of described second source, described first current mirror is the NMOSFET common-source common-gate current mirror, described second current mirror is the PMOSFET current mirror, described the first transistor is NMOSFET, and described second, third and the 4th transistor are PMOSFET.
7. operational amplifier as claimed in claim 4 is unity gain buffer, and wherein, described output node is connected with the described the 3rd transistorized grid.
8. operational amplifier as claimed in claim 1 is implemented as the part of display drive apparatus.
9. operational amplifier as claimed in claim 4 is implemented as the part of display drive apparatus.
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| KR20070013429 | 2007-02-08 | ||
| KR13429/07 | 2007-02-08 | ||
| KR82244/07 | 2007-08-16 | ||
| KR1020070082244A KR101330751B1 (en) | 2007-02-08 | 2007-08-16 | Two-stage operational amplifier with class AB output stage |
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| CN101242160A true CN101242160A (en) | 2008-08-13 |
| CN101242160B CN101242160B (en) | 2012-06-27 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101727861B (en) * | 2008-10-27 | 2012-08-29 | 奇景光电股份有限公司 | Source driving circuit with output buffer |
| CN103326670A (en) * | 2012-03-22 | 2013-09-25 | 联咏科技股份有限公司 | Output stage circuit |
| TWI420473B (en) * | 2009-02-05 | 2013-12-21 | Himax Tech Ltd | Output buffer and source driver using the same |
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| JP3520418B2 (en) | 2002-02-04 | 2004-04-19 | セイコーエプソン株式会社 | Operational amplifier circuit, drive circuit, and control method of operational amplifier circuit |
| KR100450171B1 (en) * | 2002-08-27 | 2004-09-30 | 학교법인 한양학원 | Low Quiescent Current and High Slew-Rate OP-AMP for Flat Panel Display |
| KR100560413B1 (en) * | 2003-10-13 | 2006-03-14 | 삼성전자주식회사 | Class-AB Rail-to-Rail Operational Amplifier |
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2007
- 2007-08-16 KR KR1020070082244A patent/KR101330751B1/en active IP Right Grant
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Also Published As
| Publication number | Publication date |
|---|---|
| KR101330751B1 (en) | 2013-11-18 |
| KR20080074689A (en) | 2008-08-13 |
| CN101242160B (en) | 2012-06-27 |
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