KR101330751B1 - Two-stage operational amplifier with class AB output stage - Google Patents

Abstract

An operational amplifier is disclosed. The operational amplifier comprises a differential amplifier comprising an active load, a current mirror comprising a first branch and a second branch, a first power supply and an output node and in response to a voltage at a first output terminal of the differential amplifier. A first bias circuit for adjusting an amount of a reference current flowing through the first branch in response to a first switch to be switched, a voltage at a second output terminal of the differential amplifier, and a voltage in response to a voltage of the first output terminal A second bias circuit for controlling a voltage of the second branch through which mirror current flows, a second switch connected between the output node and a second power supply and switched in response to the voltage of the second branch, and the output And a capacitor connected between the node and the first output terminal.

Operational Amplifiers, Rail-to-Rail Amplifiers, Two-Stage Amplifiers

Description

Two-stage operational amplifier with class AB output stage

The present invention relates to operational amplifiers, and more particularly to two-stage operational amplifiers having a class AB output stage.

Rail-to-rail to obtain a full swing output voltage from the ground voltage to the supply voltage in the output buffer of a source driver for driving a typical electronic device, such as a liquid crystal display panel. to-rail op amps are commonly used.

However, since the layout area of the rail-to-rail operational amplifier is quite large, the size of the output buffer of the source driver including a plurality of rail-to-rail operational amplifiers is also large. Therefore, under the tendency to reduce the size of the source driver, it is necessary to reduce the size of the operational amplifier used for the output buffer of the source driver.

Although a two-stage operational amplifier is used for the output buffer of the source driver, since the polling characteristic of the two-stage operational amplifier is bad, deviations occur between signals output from the source driver. Therefore, vertical stripes or waves may occur in the LCD panel for displaying an image due to the deviations.

In addition, when using a two-stage operational amplifier instead of a rail-to-rail operational amplifier as an output buffer of the source driver, a falling characteristic or a rising characteristic of the output voltage of the output buffer may be deteriorated.

Since the output stage of a rail-to-rail operational amplifier operates in class AB, the rail-to-rail operational amplifier applies the output load of the rail-to-rail operational amplifier to class AB (or push-push). -pull)). However, since one side of the output stage of a two-stage operational amplifier (e.g., a pull-up circuit implemented with a PMOSFET) operates as a common source amplifier and the other side (e.g., a pull-down circuit implemented with an NMOSFET) operates as a current source. The two-stage operational amplifier is difficult to operate the output load of the two-stage operational amplifier in class AB (or push-pull). Therefore, there is a need for an operational amplifier having a small layout area and capable of improving polling or rising characteristics.

Accordingly, the technical problem to be achieved by the present invention is to provide an operational amplifier which has a small layout area and improves polling or rising characteristics, and which can operate as a rail-to-rail amplifier while being a two-stage operational amplifier.

In order to achieve the above technical problem, an operational amplifier includes a differential amplifier including an active load, a current mirror including a first branch and a second branch, a first power supply and an output node, and connected to a first output terminal of the differential amplifier. A first switch switched in response to a voltage, a first bias circuit for adjusting an amount of a reference current flowing through the first branch in response to a voltage of a second output terminal of the differential amplifier, and a voltage of the first output terminal A second bias circuit for controlling a voltage of the second branch in response to a mirror current, a second switch connected between the output node and a second power supply and switched in response to the voltage of the second branch; A capacitor connected between an output node and the first output terminal.

The current mirror is an NMOSFET current mirror, the voltage of the first power supply is higher than the voltage of the second power supply, the first switch is a PMOSFET, and the second switch is an NMOSFET.

The current mirror is a PMOSFET current mirror, the voltage of the first power supply is lower than the voltage of the second power supply, the first switch is an NMOSFET, and the second switch is a PMOSFET. The operational amplifier is a two-stage operational amplifier.

In order to achieve the above technical problem, an operational amplifier includes a first current mirror connected between a first power supply and a first control node and a first current mirror including a reference current branch and a mirror current branch, and a second current connected between a second power supply and a second control node. A second current mirror, a first transistor connected between the first power supply and the output node and on / off in response to a voltage of the first control node, connected between the output node and the second power supply and the second control node A second transistor turned on / off in response to a voltage of the third transistor; a third transistor having a drain connected to the second power supply through a current source and connected to the reference current branch; and a drain having a drain connected to the mirror current branch. A transistor pair comprising four transistors, the first transistor connected between the first control node and the second control node and responsive to a plurality of bias control voltages; It comprises a capacitor connected between a bias circuit for the bias of the second transistor, and with the first current mirror branch, the output node.

The voltage of the first power supply is higher than the voltage of the second power supply, the first current mirror is a PMOSFET cascode current mirror, the second current mirror is an NMOSFET current mirror, the first transistor is a PMOSFET, The second transistor, the third transistor, and the fourth transistor are NMOSFETs.

Alternatively, the voltage of the first power supply is lower than the voltage of the second power supply, the first current mirror is an NMOSFET cascode current mirror, the second current mirror is a PMOSFET current mirror, and the first transistor is an NMOSFET, The second transistor, the third transistor, and the fourth transistor are PMOSFETs.

The operational amplifier is a unit gain buffer in which the output node and the gate of the third transistor are connected to each other. The operational amplifier is implemented as part of a display drive device.

The operational amplifier according to the embodiment of the present invention has the effect of reducing the layout area while improving the polling or rising characteristics of the output voltage.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings, which illustrate preferred embodiments of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail with reference to the preferred embodiments of the present invention with reference to the accompanying drawings. Like reference symbols in the drawings denote like elements.

1 is a block diagram of a display device including a source driver according to an exemplary embodiment of the present invention. Referring to FIG. 1, a flat panel display device 50 such as a liquid crystal display (LCD), a plasma display panel (PDP) device, or an organic light emitting diode (OLED) device may include an LCD panel 100 and a source driver 200. , And gate driver 300. The LCD panel 100 includes a plurality of gate lines (G1 to Gm; m is a natural number), a plurality of source lines (S1 to Sn; n is a natural number), and a plurality of pixels (not shown).

The source driver 300, also called a data line driver, drives a plurality of source lines S1 to Sn in response to the digital image data DATA, and the gate driver 300 includes a plurality of gate lines G1 to Gm. To drive. The plurality of pixels displays a desired image based on the operation of the source driver 200 and the gate driver 300.

FIG. 2 is a block diagram of the source driver shown in FIG. 1. Referring to FIG. 2, the source driver 200, which is a display driving device, includes a controller 205, a polarity control circuit 210, a latch circuit 220, and a digital-to-analog converter 230. ), And an output buffer 240. According to an implementation example, the controller 205 may be implemented inside or outside the source driver 200.

The controller 205 generates the polarity control signal CSP and the latching signal LS.

When a constant voltage is continuously supplied to the plurality of liquid crystals of the LCD panel 100 illustrated in FIG. 1, the plurality of liquid crystals may be cured. Therefore, in order to prevent hardening of the plurality of liquid crystals of the LCD panel 100, the polarity control circuit 210 controls the polarity of the digital image data DATA in response to the polarity control signal CSP. Here, controlling the polarity means reversing the phase of the digital image data DATA based on a common voltage supplied to the LCD panel 100 at regular intervals.

The latch circuit 220 latches the digital image data DATA output from the polarity control circuit 210 in response to the latching signal LS. The DAC 230 converts the digital image data DATA output from the latch circuit 220 into a plurality of analog voltages Vang. The phase of each of the plurality of analog voltages Vang may be inverted at regular intervals based on the common voltage.

Embodiments of the present invention, that is, the output buffer 240 including a plurality of operational amplifiers illustrated in FIGS. 4 to 7 amplifies (or buffers) each of a plurality of analog voltages Vang, and amplifies (or buffers) each. ) Are output to the corresponding source line among the plurality of source lines S1 to Sn. The output buffer 240 in the general source driver 200 includes a plurality of rail-to-rail operational amplifiers to output a voltage amplified (or buffered) to each of the plurality of source lines S1 to Sn.

However, instead of using a typical rail-to-rail operational amplifier, the output buffer 240 according to an embodiment of the present invention includes a two-stage operational amplifier (N FIG. 4 or FIG. 4) that includes an NMOSFET input stage to improve polling characteristics. 260 of FIG. 6 and a two-stage operational amplifier (270 of FIG. 5 or 7) including a PMOSFET input stage to improve the rising characteristics.

FIG. 3 is a circuit diagram of the output buffer shown in FIG. 2. 3 illustrates a first switching unit 250, two two-stage operational amplifiers 260 and 270, and a second switching unit 280 for convenience of description. Each output voltage OUT1 and OUT2 is fed back to its respective negative input terminal-so that each of the two two-stage operational amplifiers 260 and 270 can function as a unity gain buffer.

Each of the plurality of input lines INL1 and INL2 receives a plurality of analog voltages Vang1 and Vang2 whose phases are inverted every predetermined period (eg, the period of the polarity control signal). It is assumed that the polarities of each of the pair of analog voltages Vang1 and Vang2 are inverted complementarily to each other.

The first analog voltage Vang1 input to the first input line INL1 is an analog voltage to be output to the first source line Sx through the first buffer 260, and is input to the second input line INL2. The second analog voltage Vang2 is an analog voltage to be output to the second source line Sy through the second buffer 270.

The first operational amplifier 260 buffers the analog voltage whose phase is not inverted among the plurality of analog voltages Vang1 and Vang2 to any one of the plurality of source lines Sx and Sy. Where x and y are natural numbers greater than 1 and less than n, and y is 1 greater than x.

The second operational amplifier 270 buffers the analog voltage whose phase is inverted among the plurality of analog voltages Vang1 and Vang2 to one of the plurality of source lines Sx and Sy.

The first operational amplifier 260 of the output buffer 240 according to an embodiment of the present invention is a two-stage operational amplifier having an NMOSFET input stage in order to improve the polling characteristic, and the second operational amplifier 270 provides a rising characteristic. To improve it is a two-stage op amp with a PMOSFET input stage.

The first switching unit 250 in response to the plurality of first switching control signals CTRL1 at regular intervals, the first input terminal (+) of the first input line INL1 and the first operational amplifier 260. Is connected to the first input terminal (+) of the second input line (INL2) and the second operational amplifier (270). In addition, the first switching unit 250 in response to the plurality of first switching control signals CTRL1 at every predetermined period, the first input of the first input line INL1 and the second operational amplifier 270. Cross-connect the (+) terminal and cross-connect the first input (+) terminal of the second input line INL2 and the first operational amplifier 260.

The second switching unit 280 connects the output terminal of the first operational amplifier 260 and the first source line Sx in response to the plurality of second switching control signals CTRL2 at regular intervals, and then, the second switching unit 280 connects the second source switching signal Sx. The output terminal of the operational amplifier 270 is connected to the second source line Sx. In addition, the second switching unit 280 may connect the output terminal and the second source line Sy of the first operational amplifier 260 in response to the plurality of second switching control signals CTRL2 at every predetermined period. Cross-connect and cross-connect the output terminal of the second operational amplifier 270 and the first source line Sx.

In addition, the second switching unit 280 connects the first source line Sx and the second source line Sy to each other in response to the plurality of third switching control signals CTRL3 at regular intervals, thereby sharing charge. (charge sharing) operation may be performed.

In the output buffer 240, the analog voltage whose phase is not inverted is buffered by the first operational amplifier 260 to improve the polling characteristic, and the analog voltage whose phase inverted is the second operational amplifier to improve the rising characteristic. Buffered by 270. However, the reverse can be buffered.

For example, when the first analog voltage Vang1 has a non-inverted phase and the second analog voltage Vang2 has an inverted phase, the switching of the first switching unit 250 is performed. In operation, the first input line INL1 is connected to the first input terminal of the first operational amplifier 260, and the second input line INL2 is connected to the first input terminal of the second operational amplifier 270. In this case, according to the switching operation of the second switching unit 280, the output terminal of the first operational amplifier 260 is connected to the first source line Sx, and the output terminal of the second operational amplifier 270 is connected to the second. It is connected to the source line Sy.

However, when the first analog voltage Vang1 has an inverted phase and the second analog voltage Vang2 has an inverted phase, the first input line INL1 may operate according to the switching operation of the first switching unit 250. Is cross-connected to the first input terminal of the second operational amplifier 270 and the second input line INL2 is cross-connected to the first input terminal of the first operational amplifier 260.

In this case, according to the switching operation of the second switching unit 280, the output terminal of the first operational amplifier 260 is cross-connected to the second source line Sy and the output terminal of the second operational amplifier 270 is It is cross-connected to the first source line Sx.

4 is a circuit diagram of a first operational amplifier having an NMOSFET input stage according to an embodiment of the present invention. Referring to FIG. 4, the first operational amplifier 260 having the NMOSFET input stage 261 includes a current mirror 263, a first bias circuit 265, a second bias circuit 267, an output stage 269, and the like. And a compensation capacitor C1.

The first folded cascode operational amplifier circuit including the NMOSFET input stage 261, the current mirror 263, the first bias circuit 265, and the second bias circuit 267 has a polling characteristic of the output voltage OUT1. Can be improved.

NMOSFET input stage 261, also referred to as a differential amplifier with active load, or current mirror type differential amplifier, is second through a current source 3 controlled by a bias control voltage VB1. A plurality of NMOSFETs 1 and 2 connected to a power supply, for example a power supply for supplying the ground voltage VSS, and a plurality of PMOSFETs 4 and 5 constituting a current mirror.

Multiple NMOSFETs 1, 2, and 3 constitute a differential amplifier. When the first operational amplifier 260 is used as a unit gain buffer, the output terminal NO and the second input terminal − are connected to each other. The differential amplifier amplifies a difference between the first input voltage INP1 and the second input voltage INN1 to generate differential output currents.

The current mirror 263 including the NMOSFETs 6 and 7 includes a first branch through which the reference current flows and a second branch through which the mirror current, that is, the current mirrored by the reference current flows.

The first bias circuit 265 is connected between the second output terminal ODA2 of the differential amplifier and the second node ND2 connected to the first branch of the current mirror 263. The first bias circuit 265 includes a PMOSFET 10 and an NMOSFET 11 connected in parallel between the second output terminal ODA2 and the second node ND2, and the bias control voltages VB4 and VB5. The amount of reference current flowing through the first branch is adjusted in response to the voltage of the second output terminal ODA2.

The second bias circuit 267 is connected between the first output terminal ODA1 of the differential amplifier and the first node ND1 connected to the second branch of the current mirror 263. The second bias circuit 267 includes a PMOSFET 8 and an NMOSFET 9 connected in parallel between the first output terminal ODA1 and the first node ND1, and the bias control voltages VB2 and VB3. In response to the voltage of the first output terminal ODA1, the voltage of the first branch, that is, the voltage of the node ND1 is adjusted.

The output stage 269 is connected between a first switch 12 connected between an output node NO and a power supply for supplying a first power supply, for example, a power supply voltage VDD, and between the output node NO and a second power supply. It comprises a second switch 13 to be. The first switch 12 is turned on / off in response to the voltage of the first output terminal ODA1 of the differential amplifier, and the second switch 13 is turned on / off in response to the voltage of the first node ND1. The first switch 12 may be implemented as a PMOSFET, and the second switch 13 may be implemented as an NMOSFET. The compensation capacitor C1 is connected between the first output terminal ODA1 and the output node NO.

3 and 4, the operation of the first operational amplifier 260 for improving the polling characteristic of the output voltage OUT1 will be described below.

First, when the voltage level (eg, high level or VDD) of the first input signal INP1 is higher than the voltage level (eg, low level or VSS) of the second input signal INN1, the NMOSFET 1 It is turned on and the NMOSFET 2 is turned off. Therefore, the voltage level of the first output terminal ODA1 becomes the low level, and the voltage level of the second output terminal ODA2 becomes the high level.

Therefore, since the PMOSFET 12 of the output stage 267 is turned on, the output voltage OUT1 of the output terminal NO becomes high level.

When the voltage level of the first input signal INP1 rises to a high level, most of the first bias current I1 by the bias transistor 3 flows to the NMOSFET 1.

In addition, since the voltage level of the second output terminal ODA2 increases, the source-gate voltage of the PMOSFET 10 of the first bias circuit 265 increases. Since the source-drain current of the PMOSFET 10 increases, the drain-source current of the NMOSFET 7 of the first branch of the current mirror 263, that is, the reference current, increases. By current mirroring, the drain-source current of the NMOSFET 6 of the second branch of the current mirror 263, that is, the mirror current, also increases.

However, when the voltage level of the second output terminal ODA2 rises, the source-gate voltage of the PMOSFET 5 of the current mirror of the differential amplifier decreases, so that the source-drain current of the PMOSFET 5, that is, the reference current decreases. do. By current mirroring, the source-drain current, that is, the mirror current, of the PMOSFET 4 of the current mirror is also reduced.

As a result, a forward slew is charged while the electric charge corresponding to the amount of current minus the amount of current flowing through the NMOSFET 6 from the sum of the amount of current flowing through the NMOSFET 1 and the amount of current flowing through the PMOSFET 4 is charged. Is formed. Here, the forward slew may also mean a case of changing from 0.5VDD to 0.75VDD or from 0.75VDD to VDD.

The voltage OUT1 of the output terminal NO rises faster by a current or charge charged in the capacitor C1, and a forward slew of the output voltage OUT1 is formed. Therefore, the first operational amplifier 260 according to the embodiment of the present invention has excellent rising characteristics.

Further, when the voltage level of the first output terminal ODA1 is lowered, the source-gate voltage of the PMOSFET 8 of the second bias circuit 267 is lowered, so that the source-drain current of the PMOSFET 8 decreases.

However, since the drain-source current of the NMOSFET 6 of the second branch of the current mirror 263, ie the mirror current, must always be constant based on the current mirroring, the drain of the NMOSFET 9 of the second bias circuit 267. Source current must increase. Since the gate-source voltage of the NMOSFET 9 of the second bias circuit 267 needs to increase, the voltage of the first node ND1 drops.

When the voltage level of the first node ND1 falls, the NMOSFET 13 is quickly turned off and the current flowing from the output node NO to the second power supply is quickly cut off, so that the rising characteristic of the output voltage OUT1 is further reduced. Is improved. At this time, the voltage level of the first output terminal ODA1 and the voltage level of the first node N1 increase or decrease together.

Second, when the voltage level (eg, low level) of the first input signal INP1 is lower than the voltage level (eg, high level) of the second input signal INN1, the NMOSFET 1 is turned off, NMOSFET 2 is turned on. Therefore, the voltage level of the first output terminal ODA1 becomes high level, and the voltage level of the second output terminal ODA2 becomes low level.

Therefore, the PMOSFET 12 of the output stage 269 is turned off and the NMOSFET 13 is turned on. Therefore, the voltage OUT1 of the output terminal NO becomes the ground voltage VSS.

At this time, most of the bias current I1 flows to the NMOSFET 2. Therefore, since the voltage level of the second output terminal ODA2 is lowered, the source-gate voltage of the PMOSFET 10 of the first bias circuit 265 is lowered. Therefore, since the source-drain current of the PMOSFET 10 decreases, the drain-source current of the NMOSFET 7 of the first branch of the current mirror 263, that is, the reference current, decreases. Based on the current mirroring, the drain-source current of the NMOSFET 6 of the second branch of the current mirror 266, that is, the mirror current, also decreases.

However, as the voltage level of the second output terminal ODA2 falls, the source-gate voltage of the PMOSFET 5 of the current mirror of the differential amplifier increases, so that the source-drain current of the PMOSFET 5, that is, the reference current Increases. Based on the current mirroring, the drain-source current of the PMOSFET 4 of the current mirror of the differential amplifier, that is, the mirror current, also increases.

As a result, the amount of current corresponding to the difference between the amount of current flowing through the PMOSFET 4 of the current mirror of the differential amplifier and the amount of current flowing through the NMOSFET 6 of the current mirror 263 is measured at the first output terminal ODA1. Should flow into C1).

Therefore, while the output voltage OUT1 of the output terminal NO falls rapidly, reverse slew of the output voltage OUT1 is formed, so that the polling characteristic of the output voltage OUT1 is improved. In this case, the reverse may mean that the first voltage is changed from VDD to 0.75VDD or from 0.75VDD to 0.5VDD.

Further, when the voltage level of the first output terminal ODA1 increases, the source-gate voltage of the PMOSFET 8 of the second bias circuit 267 increases, so that the source-drain current of the PMOSFET 8 increases.

However, the drain-source current of the NMOSFET 6 of the second branch of the current mirror 263, ie the mirror current, must always be constant based on the current mirroring. Therefore, the drain-source current of the NMOSFET 9 of the second bias circuit 267 should be reduced. Since the gate-source voltage of the NMOSFET 9 of the second bias circuit 267 must be lowered, the voltage of the first node ND1 increases. The voltage level of the first output terminal ODA1 and the voltage level of the first node ND1 rise together.

Since the voltage level of the first output terminal ODA1 rises, the PMOSFET 12 is quickly turned off, so that the current supplied from the first power source to the output node NO is quickly cut off. In addition, since the voltage level of the first node ND1 increases, the NMOSFET 13 is turned on, so that the voltage level of the output node NO is lowered to the voltage of the first power supply, for example, the ground voltage VDD. Therefore, the polling characteristic of the output voltage OUT1 of the first operational amplifier 260 according to the embodiment of the present invention is further improved.

As described above with reference to FIG. 4, the voltage of the gate of the NMOSFET 13 of the output stage 269 and the voltage of the gate of the PMOSFET 12 are increased or decreased together. The first operational amplifier 260, which is a stage operational amplifier, may perform a class AB operation like a class AB operational amplifier, such as a rail-to-rail operational amplifier.

5 is a circuit diagram of a second operational amplifier having a PMOSFET input stage according to an embodiment of the present invention. Referring to FIG. 5, the second operational amplifier 270 having the PMOSFET input stage 271 includes a current mirror 273, a first bias circuit 275, a second bias circuit 277, an output stage 279, And a compensation capacitor C2.

The second folded cascode operational amplifier circuit including the PMOSFET input stage 271, the current mirror 273, the first bias circuit 275, and the second bias circuit 277 has a rising characteristic of the output voltage OUT1. To improve.

A PMOSFET input stage 271, also called a differential amplifier with an active load, or a current mirror type differential amplifier, includes a plurality of PMOSFETs connected to a first power source through a current source 16 controlled by a bias control voltage VB6. 14 and 16, and a plurality of NMOSFETs 17 and 18 that make up the current mirror.

Multiple PMOSFETs 14, 15, and 16 constitute a differential amplifier. When the second operational amplifier 270 is used as a unit gain buffer, the output terminal NO and the second input terminal − are connected to each other. The differential amplifier amplifies a difference between the first input voltage INP2 and the second input voltage INN2 to generate differential output currents.

The current mirror 273 including the PMOSFETs 19 and 20 includes a first branch through which the reference current flows and a second branch through which the mirror current, that is, the mirrored current flows.

The first bias circuit 275 is connected between the second output terminal ODA4 of the differential amplifier and the fourth node ND4 connected to the first branch of the current mirror 273. The first bias circuit 275 includes a PMOSFET 23 and an NMOSFET 24 connected in parallel between the second output terminal ODA4 and the fourth node ND4, and the bias control voltages VB9 and VB10. The amount of reference current flowing through the first branch is adjusted in response to the voltage of the second output terminal ODA4.

The second bias circuit 277 is connected between the first output terminal ODA3 of the differential amplifier and the third node ND3 connected to the second branch of the current mirror 273. The second bias circuit 277 includes a PMOSFET 21 and an NMOSFET 22 connected in parallel between the first output terminal ODA3 and the third node ND3, and the bias control voltages VB7 and VB8. In response to the voltage of the first output terminal ODA3, the voltage of the first branch, that is, the voltage of the third node ND3 is adjusted.

The output stage 279 includes a first switch 25 connected between the second power supply and the output node NO, and a second switch 26 connected between the output node NO and the first power supply.

The first switch 25 is turned on / off in response to the voltage of the first output terminal ODA3 of the differential amplifier, and the second switch 26 is connected to the voltage of the second branch, that is, the voltage of the third node ND3. On / off in response. The first switch 25 may be implemented as an NMOSFET, and the second switch 26 may be implemented as a PMOSFET. The compensation capacitor C2 is connected between the first output terminal ODA3 and the output node NO.

3 and 5, the operation for improving the polling characteristic of the second operational amplifier 270 will be described.

First, when the voltage level (eg, low level) of the first input signal INP2 is lower than the voltage level (eg, high level) of the second input signal INN2, the PMOSFET 14 of the differential amplifier is turned on. On and the PMOSFET 15 is turned off. Thus, most of the bias current I2 flows into the PMOSFET 14.

Since the voltage level of the first output terminal ODA3 is at a high level, the NMOSFET 25 is turned on and the voltage level of the third node ND3 is at a high level, so the PMOSFET 26 is turned off. Therefore, the voltage level OUT2 of the output terminal NO goes low.

When the voltage level of the first output terminal ODA3 rises, the gate-source voltage of the NMOSFET 22 of the second bias circuit 277 drops. Thus, the drain-source current of the NMOSFET 22 decreases.

In addition, since the voltage level of the second output terminal ODA4 falls, the gate-source voltage of the NMOSFET 18 of the first branch of the current mirror of the differential amplifier decreases, so that the drain-source current of the NMOSFET 18, namely The reference current decreases. By current mirroring, the drain-source current of the NMOSFET 17 of the current mirror of the differential amplifier, that is, the mirror current, is also reduced.

The amount of current obtained by subtracting the amount of current flowing through the current mirror 273 from the sum of the amount of current flowing through the PMOSFET 14 of the differential amplifier and the amount of current flowing through the current mirror of the differential amplifier is compensated from the first output terminal ODA3. Flow to capacitor C2.

Then, while the output voltage OUT2 of the output terminal NO is rapidly decreased, a reverse slew of the output voltage OUT2 is formed, so that the second operational amplifier 270 according to the embodiment of the present invention is excellent. Has polling properties.

Also, as the voltage level of the second output terminal ODA4 decreases, the gate-source voltage of the NMOSFET 24 of the first bias circuit 275 increases, so that the drain-source current of the NMOSFET 24 increases. . Thus, the reference current and mirror current of the current mirror 273 increase.

Since the voltage level of the first output terminal ODA3 rises, the drain-source current of the NMOSFET 22 of the second bias circuit 277 decreases. Since the mirror current of the current mirror 276 must always be constant, the voltage of the third node ND3, which is the source voltage of the PMOSFET 21 of the second bias circuit 277, must increase. As the voltage of the third node ND3 rises, the PMOSFET 26 is quickly turned off so that the current supplied from the first power supply is quickly cut off, so that the polling of the second operational amplifier 270 according to the embodiment of the present invention is performed. The property is further improved.

Second, when the voltage level of the first input signal INP2 rises to the high level and the voltage level of the second input signal INN2 falls to the low level, the PMOSFET 14 is turned off and the PMOSFET 15 is turned on. -It's on.

Since the voltage level of the first output terminal ODA3 is at a low level, the NMOSFET 25 is turned off, and the voltage level of the third node ND3 is at a low level, so that the PMOSFET 26 is turned on. Therefore, the output voltage OUT2 of the output terminal NO is at the high level (that is, the voltage level of the first power supply).

In this case, most of the bias current I2 flows into the PMOSFET 15. As the voltage level of the first output terminal ODA3 falls to the low level, the gate-source voltage of the NMOSFET 22 of the second bias circuit 277 increases. Thus, the drain-source current of the NMOSFET 22 increases.

As the voltage level of the second output terminal ODA4 increases, the gate-source voltage of the NMOSFET 18 of the current mirror of the differential amplifier increases, so that the drain-source current of the NMOSFET 18 also increases. By current mirroring, the drain-source current of the NMOSFET 17 also increases.

A forward slew is formed while the amount of current corresponding to the difference between the amount of current flowing through the NMOSFET 17 of the current mirror of the differential amplifier and the amount of current flowing through the PMOSFET 19 of the current mirror 273 is charged to the compensation capacitor C2. Therefore, the rising characteristic of the output voltage OUT2 is improved.

As the voltage level of the first output terminal ODA3 falls, the NMOSFET 25 is quickly turned off. Therefore, since the current flowing from the output node NO to the second power supply is quickly cut off, the rising characteristic of the output voltage OUT2 of the second operational amplifier 270 according to the embodiment of the present invention is further improved.

As described above with reference to FIG. 5, since the voltage of the gate of the NMOSFET 25 and the voltage of the gate of the PMOSFET 26 move in the same direction, the second operational amplifier, which is a two-stage operational amplifier, is a class AB operational amplifier. You can perform class AB operations as well.

6 is a circuit diagram of an operational amplifier having an NMOSFET input stage according to another embodiment of the present invention. Referring to FIG. 6, a two-stage operational amplifier 260 including an NMOSFET input stage 261 ′ may include a first current mirror 262, a second current mirror 264, a bias circuit 266, an output stage, And a compensation capacitor C1.

The NMOSFET input stage 261 ′ having the structure of a differential amplifier includes differential NMOSFETs N1 and N2 connected to a power supply for supplying a second power supply, for example, a ground voltage VSS, through the NMOSFET N3. The NMOSFET N3, which performs the function of the current source, is controlled based on the bias control voltage VB1.

The differential amplifier amplifies the difference between the input voltages INP1 and INN1 and outputs differential output currents. When the first operational amplifier 260 is used as a unit gain buffer, the output voltage OUT1 is fed back to the second input terminal (−) of the first operational amplifier 260.

That is, the drain of the NMOSFET N1 is connected to the mirror current branch of the first current mirror 262, for example, the branch through which the source-drain current of the PMOSFET P7 flows, and the drain of the NMOSFET N2 is a reference current branch, For example, it is connected to a branch through which the source-drain current of the PMOSFET P5 flows.

The first current mirror 262, which may be implemented as a PMOSFET cascode current mirror, is connected between a first power supply, for example a power supply for supplying a power supply voltage VDD, and a first control node PU, and includes a reference current branch and a mirror. It includes a current branch. That is, the first current mirror 262 is implemented with a plurality of PMOSFETs P4, P5, P6, and P7, and the reference current flows through the reference current branch, and the mirror current, that is, the current in which the reference current is mirrored. Flows through the mirror current branch.

The second current mirror 264, which may be implemented as an NMOSFET current mirror, is connected between the second power supply and the second control node PD. The second current mirror 264 includes a reference current branch through which the reference current flows, for example, a branch through which the drain-source current of the NMOSFET N5 flows, and a drain-source current through a mirror current branch, such as the NMOSFET N7 through which the mirror current flows. It includes a flowing branch.

The output stage includes a first transistor P10 connected between the first power supply and the output node NO and a second transistor N10 connected between the output node NO and the second power supply. The first transistor P10 may be implemented with a PMOSFET, and the second transistor N10 may be implemented with an NMOSFET.

The bias circuit 266 is connected between the first current mirror 262 and the second current mirror 264 and includes a plurality of bias control voltages VB7 and VB8, a voltage of the first control node PU, and In response to the voltage of the second control node PD, each of the first transistor P10 and the second transistor N10 is biased.

The bias circuit 266 includes a first bias circuit 266A and a second bias circuit 266B, and the first bias circuit 266A is connected in parallel between the fifth node ND5 and the sixth node ND6. PMOSFET P8 and NMOSFET N8 to be connected are included. The second bias circuit 266B includes a PMOSFET P9 and an NMOSFET N9 connected in parallel between the first control node PU and the second control node PD. The bias control voltage VB7 biases the PMOSFETs P8 and P9, and the bias control voltage VB8 biases the NMOSFETs N8 and N9.

The first bias circuit 266A is called a floating current source. The second bias circuit 266B biases each of the first transistor P10 and the second transistor N10 so that the first transistor P10 and the second transistor N10 can operate as a class AB. .

The first transistor P10 is turned on / off in response to the voltage of the first control node PU, and the second transistor N10 is turned on / off in response to the voltage of the second control node PD.

The compensation capacitor C1 is connected between the mirror current branch of the first current mirror 262 and the output node NO.

7 is a circuit diagram of an operational amplifier having a PMOSFET input stage according to another embodiment of the present invention. Referring to FIG. 7, a two-stage operational amplifier 270 including a PMOSFET input stage 271 ′ may include a first current mirror 272, a second current mirror 274, a bias circuit 276, an output stage, And a compensation capacitor C2.

The PMOSFET input stage 271 ′ having the structure of the differential amplifier includes differential PMOSFETs P1 and P2 connected to a power supply for supplying a first power supply, for example, a power supply voltage VDD, through the PMOSFET P3. The PMOSFET P3, which performs the function of the current source, is controlled based on the bias control voltage VB2.

The differential amplifier amplifies the difference between the input voltages INP2 and INN2 and outputs differential output currents. When the second operational amplifier 270 is used as the unit gain buffer, the output voltage OUT2 is supplied to the second input terminal (−) of the second operational amplifier 270.

That is, the drain of the PMOSFET P1 is connected to the mirror current branch of the first current mirror 272, and the PMOSFET P2 is connected to the reference current branch.

The first current mirror 272, which may be implemented as an NMOSFET cascode current mirror, is connected between a second power supply supplying a second power supply, for example a ground voltage VSS, and the second control node PD, and the reference current branch and the mirror. It includes a current branch. That is, the first current mirror 272 is implemented with a plurality of NMOSFETs N4, N5, N6, and N7, the reference current flows through the reference current branch, and the mirror current, that is, the current in which the reference current is mirrored. Flows through the mirror current branch.

The second current mirror 274, which may be implemented as a PMOSFET current mirror, is connected between the first power supply and the first control node PU. The second current mirror 274 is connected to a reference current branch through which the reference current flows (for example, a branch to which the eighth node ND8 is connected) and a mirror current branch through which the mirror current flows (for example, the first control node PU). Branch).

The output stage includes a first transistor P10 connected between the first power supply and the output node NO and a second transistor N10 connected between the output node NO and the second power supply. The first transistor P10 may be implemented with a PMOSFET, and the second transistor N10 may be implemented with an NMOSFET.

The bias circuit 276 is connected between the first current mirror 272 and the second current mirror 274, a plurality of bias control voltages (VB7 and VB8), the voltage of the first control node (PU), and In response to the voltage of the second control node PD, each of the first transistor P10 and the second transistor N10 is biased.

The bias circuit 276 includes a first bias circuit 276A and a second bias circuit 276B, and the first bias circuit 276A is parallel between the seventh node ND7 and the eighth control node ND8. PMOSFET P8 and NMOSFET N8 connected to each other. The second bias circuit 276B includes a PMOSFET P9 and an NMOSFET N9 connected in parallel between the first control node PU and the second control node PD. The bias control voltage VB7 biases the PMOSFETs P8 and P9, and the bias control voltage VB8 biases the NMOSFETs N8 and N9.

The first bias circuit 276A is called a floating current source. The second bias circuit 276B biases each of the first transistor P10 and the second transistor N10 so that the first transistor P10 and the second transistor N10 can operate as a class AB. .

The first transistor P10 is turned on / off in response to the voltage of the first control node PU, and the second transistor N10 is turned on / off in response to the voltage of the second control node PD. The compensation capacitor C1 is connected between the mirror current branch of the first current mirror 272 and the output node NO.

As described above with reference to FIGS. 6 and 7, since the voltage of the gate of the PMOSFET P10 and the voltage of the gate of the NMOSFET N10 move in the same direction, the second operational amplifier 260 which is a two-stage operational amplifier. Alternatively, the second operational amplifier 270 may perform a class AB operation like a class AB operational amplifier. As used herein, the first power source, the second power source, the first switch, the second switch, and the like are provided by way of example for convenience.

An embodiment according to the present invention has been described with reference to an embodiment shown in the drawings, but this is only an example, and those skilled in the art may make various modifications and other equivalent embodiments therefrom. Will understand. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS A brief description of each drawing is provided to more fully understand the drawings recited in the description of the invention.

1 is a block diagram of a display device including a source driver according to an exemplary embodiment of the present invention.

FIG. 2 is a block diagram of the source driver shown in FIG. 1.

FIG. 3 is a circuit diagram of the output buffer shown in FIG. 2.

4 is a circuit diagram of an operational amplifier having an NMOSFET input stage according to an embodiment of the present invention.

5 is a circuit diagram of an operational amplifier having a PMOSFET input stage according to an embodiment of the present invention.

6 is a circuit diagram of an operational amplifier having an NMOSFET input stage according to another embodiment of the present invention.

7 is a circuit diagram of an operational amplifier having a PMOSFET input stage according to another embodiment of the present invention.

Claims (8)

A differential amplifier comprising an active load; A current mirror including a first branch and a second branch; A first switch connected between a first power supply and an output node and switched in response to a voltage at a first output terminal of the differential amplifier; A first bias circuit for adjusting an amount of a reference current flowing through the first branch in response to a voltage of a second output terminal of the differential amplifier; A second bias circuit for controlling the voltage of the second branch through which mirror current flows in response to the voltage of the first output terminal; A second switch connected between the output node and a second power supply and switched in response to the voltage of the second branch; And And a capacitor coupled between the output node and the first output terminal. The operational amplifier of claim 1, wherein the current mirror is an NMOSFET current mirror, a voltage of the first power supply is higher than a voltage of the second power supply, the first switch is a PMOSFET, and the second switch is an NMOSFET. The operational amplifier of claim 1, wherein the current mirror is a PMOSFET current mirror, the voltage of the first power supply is lower than the voltage of the second power supply, the first switch is an NMOSFET, and the second switch is a PMOSFET. A first current mirror connected between the first power supply and the first control node, the first current mirror including a reference current branch and a mirror current branch; A second current mirror connected between the second power supply and the second control node; A first transistor connected between the first power supply and an output node and turned on / off in response to a voltage of the first control node; A second transistor connected between the output node and the second power supply and turned on / off in response to a voltage of the second control node; A transistor pair connected to said second power source via a current source, said transistor pair comprising a third transistor having a drain connected to said reference current branch and a fourth transistor having a drain connected to said mirror current branch; A bias circuit connected between the first control node and a second control node, the bias circuit for biasing the first transistor and the second transistor in response to a plurality of bias control voltages; And And a capacitor coupled between the mirror current branch and the output node. 5. The method of claim 4, wherein the voltage of the first power supply is higher than the voltage of the second power supply, wherein the first current mirror is a PMOSFET cascode current mirror, the second current mirror is an NMOSFET current mirror, and the first The transistor is a PMOSFET, and the second transistor, the third transistor, and the fourth transistor is an NMOSFET. 5. The method of claim 4, wherein the voltage of the first power supply is lower than the voltage of the second power supply, the first current mirror is an NMOSFET cascode current mirror, the second current mirror is a PMOSFET current mirror, and the first transistor. Is an NMOSFET, and the second transistor, the third transistor, and the fourth transistor are PMOSFETs. 5. The operational amplifier of claim 4, wherein the operational amplifier is a unity gain buffer in which the output node and the gate of the third transistor are connected to each other. 5. The operational amplifier of claim 1 or 4, wherein said operational amplifier is implemented as part of a display driving device.

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