TWI420473B - Output buffer and source driver using the same - Google Patents

Description

Output buffer and source driver to which the output buffer is applied

The present invention relates to an output buffer and a source driver using the same, and more particularly to an output buffer which can increase the driving capability of the source driver for charging and discharging without requiring additional power consumption. .

The source driver is a very important component in a liquid crystal display. The source driver mainly includes a shift register, a digital analog converter, an output buffer, and an output multiplexer. The Displacement Register controls the data latch to receive digital video signals from the data bus by timing control. The digital analog converter is used to convert the digital video signal into an analog drive signal. The output buffer boosts the drive capability of the drive signal. The output multiplexer outputs a drive signal to the pixels on the display panel to display the image.

Figure 1 is a circuit diagram of the output buffer of a conventional source driver. Referring to FIG. 1 , the output buffer 100 includes an input stage 110 , a charge output stage 120 , and a discharge output stage 130 . The input stage 110 controls the charge output stage 120 and the discharge output stage 130 according to the signals of the input terminals Vi+, Vi-, wherein the output buffer 100 is a single gain buffer having an input terminal Vi-coupled to its output terminal Vout. When the signal of the input terminal Vi+ is greater than the signal of the input terminal Vi-, the induced current I1 is reduced to conduct the transistors M6, M8. The turned-on transistor M6 forms a charging path to increase the voltage at the output terminal Vout, and the turned-on transistor M8 increases the gate voltage of the transistor M10 so that the transistor M10 does not conduct. In addition, when the input Vi+ signal is smaller than the input At the end of the Vi-signal, the induced current I1 is increased to make the transistors M6, M8 non-conductive. At the same time, the transistor M9 turned on by the bias voltage Vb pulls down the gate voltage of the transistor M10, and conducts the crystal M10 to form a discharge path to reduce the voltage of the output terminal Vout.

As the operating frequency increases, the source driver may not have enough time to charge and discharge the voltage of the output terminal Vout to a predetermined target value, and it is too late to transmit a predetermined voltage to the corresponding pixel on the display panel to control the liquid crystal molecules. turn around. Therefore, the output buffer 100 should increase the driving ability of charging and discharging to increase the slew rate of the driving signal. However, the designer can increase the width-to-length ratio of the transistor to increase the charge and discharge current of the output buffer 100, but this requires more power consumption and layout area. In order to increase the drive capability of charge and discharge, the output buffer requires an appropriate circuit design.

In view of this, the present invention provides an output buffer and a source driver to which the output buffer is applied, and the output buffer can increase the driving capability of the source driver for charging and discharging without requiring additional power consumption.

The present invention provides an output buffer that is suitable for application to a source driver. The output buffer includes an input stage module, a first output stage module, a second output stage module and a first control module. The first input end and the second input end of the input stage module respectively receive a driving signal and an output signal, and the first connection end of the input stage module generates a first bias signal according to the driving signal and the output signal. First output stage module and second output stage module The first connection end is coupled to the input stage module. The first output stage module generates an output signal according to the first bias signal, and outputs the output signal to the display panel through one output end of the output buffer. The second output stage module generates a second bias signal according to the first bias signal, and outputs a second bias signal through a second connection output signal. The second output stage module includes a first switch having a first end coupled to the output of the output buffer and a second end coupled to a first voltage. The first switch determines whether to conduct according to the second bias signal. The first control module is coupled between the output end of the output buffer and the second connection end of the second output stage module. The first control module selectively connects a first current source to the output end of the output buffer or the second connection end of the second output stage module according to an indication signal.

The present invention provides a source driver adapted to drive a display panel. The source driver includes the output buffer of the present invention, and an output multiplexer. The output multiplexer turns on the output of the output buffer and the display panel according to a switching signal.

In an embodiment of the invention, the input stage module includes a differential pair, a current mirror circuit, and a second current source. The differential pair includes a first transistor and a second transistor. The first transistor has a gate that receives the driving signal and is coupled to one of the first source/drain of the current mirror circuit. The second transistor has a gate receiving the output signal, a first source/drain coupled to the current mirror circuit, and a second source/drain connected to the second source/drain of the first transistor The first source/drain is used to generate a first bias signal. The current mirror circuit provides a first bias current and a second bias current to the first source/drain of the first transistor and the first source/drain of the second transistor, respectively. Second current One of the first ends of the source is coupled to the second source/drain of the first transistor, and the second end of the second current source is coupled to the first voltage.

In an embodiment of the invention, the output buffer further includes a second control module. The second control module is coupled between the second source/drain of the first transistor and the output of the output buffer for selectively connecting a third current source to the first transistor according to the indication signal The output of the two source/drain or output buffer.

In an embodiment of the invention, the second control module includes a second switch and a third switch. The first end and the second end of the second switch are respectively coupled to the second source/drain and the third current source of the first transistor, wherein the second switch determines whether to conduct according to the indication signal. The first end and the second end of the third switch are respectively coupled to the second source/drain of the second transistor and the output of the output buffer, wherein the third switch determines whether to conduct according to the reverse indication signal.

In an embodiment of the invention, the first control module includes a fourth switch and a fifth switch. The first end and the second end of the fourth switch are respectively coupled to the output end of the output buffer and the first current source, wherein the fourth switch determines whether to conduct according to a reverse indication signal. The first end and the second end of the fifth switch are respectively coupled to the second end of the fourth switch and the second end of the second output stage module, wherein the fifth switch determines whether to conduct according to the indication signal.

The output buffer provided by the present invention and the source driver using the output buffer selectively connect the first current source to the first output stage module or the second output stage module by using the first control module, so that Adjustable rectification The current of an output stage module and the current flowing through the second output stage module to increase the driving capability of the source driver. In addition, the second control module selectively connects the third current source to the input stage module or the first output stage module, so that the tail current of the input stage module can be adjusted and flow through the first output stage The current of the module.

The above described features and advantages of the present invention will be more apparent from the following description.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiments of the present invention will be described in detail with reference to the drawings.

2 is a circuit diagram of an output buffer in accordance with an embodiment of the present invention. Referring to FIG. 2 , the output buffer 200 includes an input stage module 210 , a first output stage module 220 , a second output stage module 230 , and a first control module 240 . The input stage module 210 controls the operations of the first output stage module 220 and the second output stage module 230 according to the signals Vin+, Vin- at the input end. In this embodiment, the output buffer 200 is coupled to the input terminal Vin-one single gain buffer, so the input stage module 210 receives a driving signal through the input terminal Vin+, and receives the driving signal through the input terminal Vin- One of the output signals from the output terminal Vout1.

The input stage module 210 includes a differential pair 211 composed of transistors T1, T2, a current mirror circuit 212 composed of transistors T3, T4, and a second current source implemented by transistor T5. The transistor T5 biased by the bias voltage Vb1 provides a bias current Ib to drive the differential For the 211, the current mirror circuit 212 generates a first bias current Ib1 and a second bias current Ib2 to the differential pair 211 according to the signals Vin+, Vin- at the input end, wherein the first bias current Ib1 and the second bias voltage The sum of the currents Ib2 is approximately equal to the bias current Ib. The input stage module 210 generates a first bias signal and controls the operation of the first output stage module 220 and the second output stage module 230 through the first connection end N1.

The first output stage module 220 includes transistors T6 and T7. The conduction states of the transistors T6 and T7 are respectively determined by the first bias signal and the bias voltage Vb1 from the first connection terminal N1. The first output stage module 220 generates an output signal according to the first bias signal from the first connection terminal N1 through the output terminal Vout1. When the driving signal of the input terminal Vin+ is greater than the output signal of the input terminal Vin-, the voltage of the first connecting terminal N1 (ie, the first bias signal) is reduced to conduct the conductive crystal T6, and the conductive transistor T6 forms a charging path. Pull the voltage of the output terminal Vout1 (ie, the output signal). In this embodiment, the output buffer 200 further includes a capacitor C1 coupled between the first connection terminal N1 and the output terminal Vout1 for compensating for a phase margin of the output buffer 200.

The second output stage module 230 includes transistors T8 and T9 and a switch implemented by the transistor T10. The conduction states of the transistors T8 and T9 are respectively determined by the first bias signal and the bias voltage from the first connection terminal N1. Voltage Vb1. The second output stage module 230 generates a second bias signal through the second connection terminal N2 according to the first bias signal from the first connection terminal N1. When the driving signal of the input terminal Vin+ is smaller than the output signal of the input terminal Vin-, the voltage of the first connecting terminal N1 (ie, the first bias signal) is increased to cause electricity. The crystals T6 and T8 are not turned on. At the same time, the transistor T9 turned on by the bias voltage Vb1 pulls down the voltage of the second connection terminal N2 (ie, the second bias signal), and conducts the transistor T10 to form a discharge path to pull down the voltage of the output terminal Vout1. (ie output signal).

Referring to FIG. 1 , in general, the aspect ratio of the transistor M7 is generally designed to be larger than the aspect ratio of the transistor M9 to reduce the leakage current induced by the transistor M7 and to make the conduction state of the transistor M10 easier. control. For example, in the prior art, the width to length ratio of the transistor M7 is five times that of the transistor M9. If the width to length ratio of the transistor M9 is also designed to be large, a relatively large bias voltage Vb is required in order to conduct the transistor M9. However, due to the limitation of the width to length ratio of the transistor M9, the discharge capacity of the output buffer 100 is also limited. Therefore, in the embodiment, the output buffer 200 uses the first control module 240 to adjust the current flowing through the first output stage module 220 and the current flowing through the second output stage module 230 to increase the output buffer. 200 drive capability.

The first control module 240 includes switches S4, S5 and a current source implemented by the transistor T11. The first control module 240 selectively connects the current source realized by the transistor T11 to the first output stage module 220 or the second output stage module 230 according to an indication signal HDR, wherein the switches S4 and S5 are respectively reversed. Controlled by the indication signal HDRB and the indication signal HDR. In the present embodiment, the current generated by the transistor T11 is part of the first output stage module 220. For example, the sum of the width-to-length ratio of the transistors T7 and T11 is five times the sum of the width-to-length ratio of the transistors T5 and T9, and the aspect ratio of the transistor T11 is the sum of the width-to-length ratio of the transistors T5, T7, and T9. Times.

When the indication signal HDR is de-asserted, the current source realized by the transistor T11 is connected to the output terminal Vout1 through the switch S4 which is turned on by the reverse indication signal HDRB, wherein the reverse indication signal HDRB is indicated by the indication signal HDR reverse income. At the same time, the output buffer 200 operates as usual, that is, when the output buffer 200 is in a state of charge, the transistor T6 forms a charging path to pull up the voltage of the output terminal Vout1. In addition, when the indication signal HDR is asserted, the second output stage module 230 is borrowed by the first output stage module 220 by the transistor T11 through the switch S5 that is turned on by the indication signal HDR. Battery. At the same time, the voltage of the second connection terminal N2 is rapidly lowered to conduct the transistor T10, and when the output buffer 200 is in a discharge state, the voltage of the output terminal Vout1 is pulled low. Therefore, by the operation of the first control module 240, the slew rate of the output signal can be increased to improve the driving capability of the output buffer 200. Since the current source implemented by the transistor T11 is from the first output stage module 220, the output buffer 200 does not require additional power consumption and layout area.

It is worth noting that during the transition from the charge and discharge state to the discharge state, the transistors T6, T10 may be turned on at the same time. Output buffer 200 should be maintained in a high impedance state during conversion to ensure proper operation. For example, during the conversion, an output multiplexer (not shown) coupled between the output terminal Vout1 and the display panel is inactivated by the switching signal to disconnect the output buffer 200 from the display panel.

3A-3C are timing diagrams of the first control module according to FIG. 2. Referring to FIG. 3A, when the switching signal TP is triggered to keep the output buffer 200 high impedance, the indication signal HDR is triggered to be the first input. The output module 220 introduces a current source realized by the transistor T11, and after the switching signal TP is idle, idles the indication signal HDR to return the current source realized by the transistor T11 to the first output stage module 220. , wherein the reverse indication signal HDRB is obtained by inverting the indication signal HDR. Referring to FIG. 3B, when the switching signal TP is triggered, the indication signal HDR is triggered, and when the switching signal TP is idle, the indication signal HDR is idle. Referring to FIG. 3C, when the switching signal TP is idle, the indication signal HDR is idle for a preset period, and the indication signal is idle before the scanning signal is ignored for one of the scanning lines.

4 is a circuit diagram of an output buffer in accordance with another embodiment of the present invention. The difference between the embodiment of FIG. 2 and FIG. 4 is that the output buffer 400 further includes a first connection end N1 coupled to the input stage module 410 and an output end Vout1 of the output buffer 400. The second control module 450. The second control module 450 includes switches S2, S3 and a current source implemented by the transistor T12. The second control module 450 selectively connects the current source realized by the transistor T12 to the input stage module 410 or the first output stage module 420 according to the indication signal HDR, wherein the switches S2 and S3 are respectively indicated by the indication signal HDR and the reverse Controlled by the indication signal HDRB. In the present embodiment, the current generated by the transistor T12 is part of the first output stage module 420. For example, the sum of the width-to-length ratio of the transistors T7, T11, and T12 is five times the sum of the width-to-length ratio of the transistors T5 and T9, and the sum of the width-to-length ratio of the transistors T11 and T12 is the width of the transistors T5, T7, and T9. It is twice as long as the sum.

In this embodiment, the second control module 450 can also operate according to the timing control of FIG. 3A to FIG. 3C. When the indication signal HDR is idle, the current source realized by the transistor T12 is transmitted by the reverse indication signal HDRB. The turned-on switch S3 is connected to the output terminal Vout1. At the same time, the output buffer 400 operates as usual, that is, when the output buffer 400 is in a state of charge, the transistor T6 forms a charging path to pull up the voltage of the output terminal Vout1. In addition, when the indication signal HDR is triggered, the input stage module 410 introduces the current source realized by the transistor T12 from the first output stage module 420 through the switch S2 that is turned on by the indication signal HDR. At the same time, the tail current of the input stage module 410 can be increased by the operation of the second control module 450 to improve the driving capability of the output buffer 400. Since the current source implemented by the transistor T12 is from the first output stage module 420, the output buffer 400 does not require additional power consumption and layout area.

It is well known that polarity inversion is commonly used to drive pixels on a display panel. In order to save power consumption, the source driver typically includes an output buffer that enhances the drive signals with different polarities, such as positive polarity and negative polarity. FIG. 5 illustrates a source driver in accordance with an embodiment of the present invention. Referring to FIG. 5, the source driver 500 includes an output buffer BUF1 that positively enhances the driving signal Vp, an output buffer BUF2 that is one of the negative polarity enhancement driving signals Vn, and a data line that transmits the driving signals Vp and Vn to the display panel. One of D1 and D2 outputs a multiplexer 510, wherein the output multiplexer 510 is turned on according to the switching signal TP. The output buffer BUF1 can be implemented with the output buffer 200 or the output buffer 400 of the embodiment, since the output buffers 200, 400 include an N-type differential pair that can receive the drive signal Vp with a high voltage level. The underlying embodiment will teach anyone of ordinary skill in the art to implement output buffer BUF2.

6 is a circuit diagram of an output buffer in accordance with another embodiment of the present invention. please Referring to FIG. 4 and FIG. 6, the difference between the embodiment of FIG. 4 and FIG. 6 is that the input stage module 610 of the output buffer 600 includes a P-type differential pair, wherein the output buffer 600 is an input terminal Vip-coupled to the output. One of the terminals Vout2 is a single gain buffer. The operation of output buffer 600 is similar to the operation of output buffer 400. When the signal of the input terminal Vip+ is greater than the signal of the input terminal Vip-, the voltage of the first connection terminal E1 of the input stage module 610 is reduced to cause the transistors P6, P8 to be non-conductive. At the same time, the transistor P9 turned on by the bias voltage Vb2 increases the voltage of the second connection terminal E2 of the second output stage module 630, and the conductive transistor P10 pulls up the voltage of the output terminal Vout2. In addition, when the signal of the input terminal Vip+ is smaller than the signal of the input terminal Vip-, the voltage of the first connection terminal E1 is increased to conduct the transistors P6, P8. At the same time, the turned-on transistor P6 forms a discharge path to reduce the voltage of the output terminal Vout2, and the turned-on transistor P8 increases the voltage of the second connection terminal E2 so that the transistor P10 does not conduct.

In this embodiment, the first control module 640 selectively connects the current source realized by the transistor P11 to the first output stage module 620 or the second output stage module 630 according to the indication signal HDR. In addition, the second control module 650 selectively connects the current source implemented by the transistor P12 to the first output stage module 620 or the input stage module 610 according to the indication signal HDR. Therefore, the driving capability of the output buffer 600 can be improved by the operation of the first control module 640 and/or the second output stage module 630.

In summary, in the embodiment, the output buffer and the source driver applying the output buffer selectively connect the first current source to the first output stage module or the first control module by using the first control module The second output stage module is such that the current of the first output stage module is adjustable and rectified and flows through the second output stage module The current is increased to drive the charge and discharge of the source driver. In addition, the second control module selectively connects the third current source to the input stage module or the first output stage module, so that the tail current of the input stage module and the current flowing through the first output stage module can be adjusted. .

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100, 200, 400, 600, BUF1, BUF2‧‧‧ output buffers

110‧‧‧Input level

120‧‧‧Charging output stage

130‧‧‧Discharge output stage

210, 410, 610‧‧‧ input level modules

211, 411‧‧‧Differential pair

212, 412‧‧‧current mirror circuit

220, 420, 620‧‧‧ first output stage module

230, 430, 630, ‧ ‧ second output stage module

240, 440, 640‧‧‧ first control module

450, 650‧‧‧ second control module

500‧‧‧Source Driver

510‧‧‧ Output multiplexer

Vi+, Vi-, Vin+, Vin-, Vip+, Vip-‧‧‧ inputs

Vout, Vout1, Vout2‧‧‧ output

M1~M10, T1~T12, P1~P11‧‧‧O crystal

C, C1‧‧‧ capacitor

Vb, Vb1, Vb2‧‧‧ bias voltage

I1‧‧‧Induction current

Ib‧‧‧ bias current

Ib1‧‧‧First bias current

Ib2‧‧‧second bias current

N1, E1‧‧‧ first connection

N2, E2‧‧‧ second connection

S2~S5‧‧‧ switch

HDR‧‧‧ indication signal

HDRB‧‧‧reverse indication signal

TP‧‧‧Switch signal

Vp, Vn‧‧‧ drive signals

D1, D2‧‧‧ data line

Figure 1 is a circuit diagram of the output buffer of a conventional source driver.

2 is a circuit diagram of an output buffer in accordance with an embodiment of the present invention.

3A-3C are timing diagrams of the first control module according to FIG. 2.

4 is a circuit diagram of an output buffer in accordance with another embodiment of the present invention.

FIG. 5 illustrates a source driver in accordance with an embodiment of the present invention.

6 is a circuit diagram of an output buffer in accordance with another embodiment of the present invention.

200‧‧‧Output buffer

210‧‧‧Input level module

211‧‧‧Differential pair

212‧‧‧current mirror circuit

220‧‧‧First output stage module

230‧‧‧Second output stage module

240‧‧‧First Control Module

Vin+, Vin-‧‧‧ input

Vout1‧‧‧ output

T1~T11‧‧‧O crystal

C1‧‧‧ capacitor

Vb1‧‧‧ bias voltage

Ib‧‧‧ bias current

Ib1‧‧‧First bias current

Ib2‧‧‧second bias current

N1‧‧‧ first connection

N2‧‧‧ second connection

S4, S5‧‧‧ switch

HDR‧‧‧ indication signal

HDRB‧‧‧reverse indication signal

Claims (19)

A source driver is adapted to drive a display panel, comprising: an output buffer, comprising an input stage module, having a first input end for receiving a driving signal, a second input end for receiving an output signal, and a basis The driving signal and the output signal generate a first connection end of a first bias signal; a first output stage module coupled to the first connection end of the input stage module for The output signal is generated by the output of the output buffer to the display panel; and a second output stage module is coupled to the first connection end of the input stage module for The first bias signal generates a second bias signal through a second connection end of the second output stage module, and the second output stage module includes: a first switch coupled to the output a first end of the output end of the buffer, and coupled to a second end of a first voltage, wherein the first switch determines whether to conduct according to the second bias signal; and a first control module Directly coupled to the output buffer Between the output end and the second connection end of the second output stage module, for selectively and directly connecting a first current source to the output end or the second output of the output buffer according to an indication signal The second connection end of the level module; and an output multiplexer coupled between the output end of the output buffer and the display panel for turning on the output buffer according to a switching signal The output is connected to the display panel. The source driver of claim 1, wherein the input stage module comprises: a differential pair comprising: a first transistor having a gate receiving the driving signal, a first source/ a drain and a second source/drain; and a second transistor having a gate receiving the output signal as a first source of the first connection for generating the first bias signal/ a drain and a second source/drain coupled to the second source/drain of the first transistor; and a current mirror circuit coupled to the first source/drain of the first transistor And the first source/drain of the second transistor for respectively providing a first bias current and a second bias current to the first source/drain and the second of the first transistor The first source/drain of the transistor; and a second current source having a first end of the second source/drain coupled to the first transistor and coupled to the first voltage A second end. The source driver of claim 2, wherein the current mirror circuit comprises: a third transistor having a gate coupled to a first source/drain of the second voltage and coupled a second source/drain to the gate and the first source/drain of the first transistor; and a fourth transistor having a gate coupled to the gate of the third transistor The first source/drain is coupled to one of the second voltages and the second source/drain of the first source/drain is coupled to the second transistor. The source driver of claim 2, wherein the second current source comprises a fifth transistor, the fifth transistor having a gate coupled to a bias voltage, coupled to the first A first source/drain of the second source/drain of a transistor and a second source/drain of the first voltage. The source driver of claim 2, further comprising: a second control module directly coupled to the second source/drain of the first transistor and the output of the output buffer Between the third current source and the second source/drain of the first transistor or the output of the output buffer, selectively and directly connected according to the indication signal. The source driver of claim 5, wherein the second control module comprises: a second switch having a first end of the second source/drain coupled to the first transistor And being coupled to the second end of the third current source, wherein the second switch determines whether to conduct according to the indication signal; and a third switch having the second end coupled to the second switch a first end, and a second end of the output coupled to the output buffer, wherein the third switch determines whether to conduct according to a reverse indication signal. The source driver of claim 1, wherein the first output stage module comprises: a sixth transistor having a gate coupled to the first connection end of the input stage module, a first source/drain coupled to one of the second voltages and a second source/drain as the output of the output buffer; a seventh transistor having a gate coupled to a bias voltage, a first source/drain coupled to the second source/drain of the sixth transistor, and coupled to the first One of the voltages is the second source/dip. The source driver of the first aspect of the invention, wherein the second output stage module further comprises: an eighth transistor having a gate coupled to the first connection end of the input stage module And a first source/drain coupled to a second voltage and a second source/drain according to the first bias signal and the second bias via the second connection; and a first a nine-electrode having a gate coupled to a bias voltage, coupled to the first source/drain of the second source/drain of the eighth transistor, and coupled to the first voltage A second source / bungee. The source driver of claim 1, wherein the first control module comprises: a fourth switch having a first end of the output directly coupled to the output buffer, and coupled a second end of the first current source, wherein the fourth switch determines whether to conduct according to a reverse indication signal; and a fifth switch having one of the second ends coupled to the fourth switch An end of the second connection end coupled to the second output end of the second output stage module, wherein the fifth switch determines whether to conduct according to the indication signal. The source driver of claim 1, further comprising: a capacitor having the first connection end coupled to the input stage module a first end, and a second end of the output coupled to the output buffer. The source driver of claim 1, wherein the first switch comprises: a tenth transistor having a gate coupled to the second connection of the second output stage module; One of the output terminals connected to the output buffer is coupled to the second source/drain of the first voltage, wherein the gate is configured to receive the second bias signal. The source driver of claim 1, wherein when the switching signal is triggered, the indication signal is triggered, and after the switching signal is idle, the indication signal is idle. The source driver of claim 1, wherein the indication signal is triggered when the switching signal is triggered, and the indication signal is idle when the switching signal is idle. The source driver of claim 1, wherein when the switching signal is idle, the indication signal is triggered, and the indication signal is idle before a scanning signal associated with one of the scanning lines is idle. An output buffer adapted to be applied to a source driver, comprising: an input stage module having a first input receiving a driving signal, receiving a second input of an output signal, and according to the driving signal The output signal generates a first connection end of the first bias signal; a first output stage module is coupled to the first connection end of the input stage module for borrowing according to the first bias signal Lost by one of the output buffers And outputting the output signal to the display panel; and a second output stage module coupled to the first connection end of the input stage module for the second bias signal according to the second a second connection end of the output stage module generates a second bias signal, the second output stage module includes: a first switch having a first end coupled to the output end of the output buffer And being coupled to a second end of a first voltage, wherein the first switch determines whether to conduct according to the second bias signal; and a first control module directly coupled to the output buffer Between the output end and the second connection end of the second output stage module, for selectively and directly connecting a first current source to the output end or the second output of the output buffer according to an indication signal The second connection end of the level module. The output buffer of claim 15, wherein the input stage module comprises: a differential pair comprising: a first transistor having a gate receiving the driving signal, a first source/ a drain and a second source/drain; and a second transistor having a gate receiving the output signal as a first source of the first connection for generating the first bias signal/ a drain and a second source/drain coupled to the second source/drain of the first transistor; and a current mirror circuit coupled to the first source/drain of the first transistor And the first source/drain of the second transistor for respectively providing a first bias current and a second bias current to the first source/汲 of the first transistor And the first source/drain of the second transistor; and a second current source having a first end of the second source/drain coupled to the first transistor, and coupled to One of the first ends of the first voltage. The output buffer of claim 16, further comprising: a second control module directly coupled to the second source/drain of the first transistor and the output of the output buffer Between the third current source and the second source/drain of the first transistor or the output of the output buffer, selectively and directly connected according to the indication signal. The output buffer of claim 17, wherein the second control module comprises: a second switch having a first end of the second source/drain coupled to the first transistor And being coupled to the second end of the third current source, wherein the second switch determines whether to conduct according to the indication signal; and a third switch having the second end coupled to the second switch a first end, and a second end of the output coupled to the output buffer, wherein the third switch determines whether to conduct according to a reverse indication signal. The output buffer of claim 15, wherein the first control module comprises: a fourth switch having a first end of the output directly coupled to the output buffer, and coupling a second end of the first current source, wherein the fourth switch determines whether to conduct according to a reverse indication signal; and a fifth switch having one of the second ends coupled to the fourth switch One end, and the second connection end coupled to the second output stage module a second end, wherein the fifth switch determines whether to conduct according to the indication signal.