TWI478496B - Driver circuit - Google Patents

Description

Drive circuit

The present disclosure is directed to a circuit driving technique, and more particularly to a driving circuit.

Electronic products have become an integral part of modern life. In a wide variety of electronic devices, semiconductor components that can be used in these devices are needed. The characteristics of a semiconductor component are primarily determined by the process of making the component. Since semiconductor components are often complicated, the process is also subject to change. A variety of transistors having different characteristics (especially different operating voltages) are required in semiconductor components. High-voltage piezoelectric crystals are designed to meet the requirements of high-voltage operation.

In general, high voltage transistors can withstand voltages of up to 10 volts, which is quite different from the 3.3 volts or 5 volts that a typical transistor can withstand. For area and component speed considerations, some technologies have designed high-voltage transistors such that only the source and drain can withstand high voltages, while the gates withstand the voltages that a typical transistor can withstand (eg, 5 volts). However, under such a design, simply driving a general low-voltage transistor and a driving circuit for driving a high-voltage transistor alone cannot thereby drive the above-described high-voltage transistor element with an appropriate voltage.

Therefore, how to design a new driving circuit to drive the above-mentioned high-voltage transistor components is an urgent problem to be solved in the industry.

Therefore, one aspect of the present disclosure is to provide a driving circuit for driving a power metal-oxide semiconductor (MOS) transistor, including: a first driving branch, a second driving branch, and a capacitor string . The first driving branch includes: a first switching N-type MOS transistor, a current source, and a first clamping P-type MOS transistor. The first switch N-type MOS transistor has a first switching gate for receiving the switching signal. The first clamp P-type MOS transistor has a first clamp gate for receiving a reference voltage, wherein the first clamp drain of the first clamp P-type MOS transistor is connected to the first switch N The first switching drain of the MOS transistor, the first clamp source of the first clamp P-type MOS transistor is connected to the current source. The second driving branch comprises: a second switch N-type MOS transistor, a current supply P-type MOS transistor, and a second clamp P-type MOS transistor. The second switch N-type MOS transistor has a second switch gate for receiving the inverted switching signal. The current supply P-type MOS transistor has a current supply gate connected to the first clamp source and a current supply source connected to the first potential. The second clamp P-type MOS transistor has a second clamp gate for receiving a reference voltage, wherein the second clamp 汲 of the second clamp P-type MOS transistor is connected to the second switch N The second switching drain of the MOS transistor, the second clamp source of the second clamp P-type MOS transistor is connected to the current supply drain of the current supply P-type MOS transistor. The second clamp source outputs a driving voltage to a power gate of the power MOS transistor. The capacitor string comprises a plurality of capacitors connected in series, the first end of the capacitor string is used for receiving the inverted switching signal, and the second end of the capacitor string is connected to the current supply gate of the current supply P-type MOS transistor to The phase switching signal is coupled to the current supply gate.

In accordance with an embodiment of the present disclosure, the first potential is a positive potential.

According to another embodiment of the present disclosure, the power MOS transistor is a high voltage MOS (HVMOS). The voltage difference between the driving voltage and the first potential is less than a specific voltage value. The minimum value of the driving voltage is the sum of the reference voltage and the threshold voltage of the second clamped P-type MOS transistor.

According to still another embodiment of the present disclosure, the reference voltage is a difference between the first potential and the highest withstand voltage of the power gate.

According to still another embodiment of the present disclosure, when the control signal is in the first state, the first switch N-type MOS transistor is turned on and the second switch N-type MOS transistor is turned off, and the capacitor string is inverted. The switching signal is coupled to the current supply gate to cause the current supply P-type MOS transistor to conduct, further turning on the second clamp P-type MOS transistor and raising the driving voltage to turn off the power MOS transistor. When the control signal is in the second state, the first switch N-type MOS transistor is turned off and the second switch N-type MOS transistor is turned on, and the capacitor string couples the inverted switching signal to the current supply gate. The current supply P-type MOS transistor is turned off, further closing the second clamp P-type MOS transistor and the driving voltage is lowered to turn on the power MOS transistor.

Another aspect of the present disclosure is to provide a driving circuit for driving a power MOS transistor, comprising: a first driving branch, a second driving branch, and a capacitor string. The first driving branch includes: a first switch P-type MOS transistor, a current source, and a first clamp N-type MOS transistor. The first switch P-type MOS transistor has a first switch gate for receiving the switching signal. The first clamp N-type gold oxide semi-transistor has a first clamp gate, Receiving a reference voltage, wherein a first clamp drain of the first clamp N-type MOS transistor is connected to the first switch drain of the first switch N-type MOS transistor, the first clamp N-type gold The first clamp source of the oxygen semiconductor is connected to the current source. The second driving branch comprises: a second switch P-type MOS transistor, a current supply N-type MOS transistor, and a second clamp N-type MOS transistor. The second switch P-type MOS transistor has a second switching gate for receiving the inverted switching signal. The current supply N-type MOS transistor has a current supply gate connected to the first clamp source and a current supply source connected to the first potential. The second clamp N-type MOS transistor has a second clamp gate for receiving a reference voltage, wherein the second clamp N of the second clamp N-type MOS transistor is connected to the second switch P The second switching drain of the MOS transistor, the second clamp source of the second clamp N-type MOS transistor is connected to the current supply drain of the current supply N-type MOS transistor. The second clamp source outputs a driving voltage to a power gate of the power MOS transistor. The capacitor string comprises a plurality of capacitors connected in series, the first end of the capacitor string is used for receiving the inverted switching signal, and the second end of the capacitor string is connected to the current supply gate of the current supply N-type MOS transistor to The phase switching signal is coupled to the current supply gate.

In accordance with an embodiment of the present disclosure, the first potential is a negative potential.

According to another embodiment of the present disclosure, the power MOS transistor is a high voltage MOS (HVMOS). The voltage difference between the driving voltage and the first potential is less than a specific voltage value. The maximum value of the driving voltage is the difference between the reference voltage and the threshold voltage of the second clamped P-type MOS transistor.

According to still another embodiment of the present disclosure, wherein the reference voltage is the first power The sum of the highest withstand voltage of the bit and the power gate.

According to still another embodiment of the present disclosure, when the control signal is in the first state, the first switch P-type MOS transistor is turned on and the second switch P-type MOS transistor is turned off, and the capacitor string is inverted. The switching signal is coupled to the current supply gate to cause the current supply N-type MOS transistor to conduct, further turning on the second clamped N-type MOS transistor and lowering the driving voltage to turn off the power MOS transistor. When the control signal is in the second state, the first switch P-type MOS transistor is turned off and the second switch P-type MOS transistor is turned on, and the capacitor string couples the inverted switching signal to the current supply gate. The current supply N-type MOS transistor is turned off, further closing the second clamp N-type MOS transistor and raising the driving voltage to turn on the power MOS transistor.

The advantage of applying the disclosure is that the driving voltage of the driving power MOS transistor can be limited by the design of the driving circuit to avoid exceeding the range that the power MOS transistor can withstand, and easily Achieve the above objectives.

Please refer to Figure 1. FIG. 1 is a circuit diagram of a driving circuit 1 according to an embodiment of the disclosure. The driving circuit 1 is used to drive a power metal-oxide semiconductor (MOS) transistor MP0.

In the present embodiment, the power MOS transistor MPO is a P-type high voltage MOS transistor. High voltage MOS (HVMOS) is a transistor that can withstand high voltage. In one embodiment, it refers to a high voltage that can withstand up to about 10 volts or more, which is different from the common normal withstand voltage ( Such as 3.3 volts or 5 volts). In some semiconductor fabrication techniques, a power MOS transistor having a source and a drain that can withstand high voltages and a gate that can only withstand a small voltage (eg, 5 volts) can be fabricated. The power MOS semi-transistor designed in this way will be able to reduce the on-resistance (R _DS (on)) of the power MOS transistor in a small area, further achieving the power MOS half. The transmission delay of the transistor is reduced, and the rising time and the falling time are reduced. In order to enable the above-mentioned type of power MOS semi-transistor to avoid driving the voltage exceeding the voltage that the gate can load during driving, it is necessary to design a driving circuit capable of limiting the range of the driving voltage to conform to this type of power MOS. The demand for crystals.

The drive circuit 1 includes a first drive branch 10, a second drive branch 12, and a capacitor string 14. The first driving branch 10 includes a first switching N-type MOS transistor MN1, a current source 100, and a first clamping P-type MOS transistor MP1.

The first switch N-type MOS transistor MN1 has a first switching gate G11 for receiving the switching signal IN . The first switch N-type MOS transistor MN1 further has a first switching source S11 to be connected to the second potential VSS.

The first clamp P-type MOS transistor M1 has a first clamp gate G12 for receiving the reference voltage Vm. The first clamped drain D12 of the first clamped P-type MOS transistor M1 is connected to the first switch drain D11 of the first switch N-type MOS transistor MN1, and the first clamp P-type The first clamp source S12 of the MOS transistor MP1 is connected to the current source 100.

The second driving branch 12 includes a second switching N-type MOS transistor MN2, a second clamping P-type MOS transistor M02, and a current supply P-type MOS transistor MP3. The second switch N-type MOS transistor MN2 has a second switch gate G21 for receiving the inverted switching signal .

The current supply P-type MOS transistor MP3 has a current supply gate G3 connected to the first clamp source S12 and a current supply source S3 connected to the first potential VGH. The second clamp P-type MOS transistor MP2 has a second clamp gate G22 for receiving the reference voltage Vm. The second clamped drain D22 of the second clamped P-type MOS transistor is connected to the second switch drain D22 of the second switch N-type MOS transistor MN2, and the second clamped P-type gold The second clamp source S22 of the oxygen semiconductor transistor MP2 is connected to the current supply drain D3 of the current supply P-type MOS transistor MP3. The second clamp source S22 outputs the driving voltage Vp to the power gate G0 of the power MOS transistor MP0.

In one embodiment, the first potential VGH is a positive potential, and the second potential VSS is a potential lower than the first potential VGH. In an embodiment, the second potential VSS can be a ground potential.

The capacitor string 14 includes a plurality of capacitors connected in series, and the first end thereof receives the inverted switching signal The second end is connected to the current supply gate G3 of the current supply P-type MOS transistor MP3 to turn the inverted switching signal Coupled to current supply gate G3.

Therefore, when the switching signal IN is in a high state, the first switching N-type MOS transistor MN1 is turned on and the second switching N-type MOS transistor MN2 is turned off. The conduction of the first switch N-type MOS transistor MN1 will cause the current generated by the current source 100 to be drawn, and its ability to draw current will be greater than the amount of current generated by the current source 100. Therefore, the voltage of the first clamp source S12 of the first clamp P-type MOS transistor M1, that is, the voltage of the current supply gate G3 for controlling the second clamp P-type MOS transistor MP3 will follow It is pulled low to further turn on the second clamp P-type MOS transistor MP3. Moreover, the capacitor string 14 can rapidly couple the inverted switching signal IN (ie, the low signal) to the current supply gate G3 of the second clamp P-type MOS transistor MP3 to speed up the second clamp P-type. The conduction speed of the gold-oxide semi-transistor MP3.

On the other hand, after the second switch N-type MOS transistor MN2 is turned off, since the second clamp P-type MOS transistor MP3 is turned on to supply current to the current supply drain D3, the current supplies the voltage of the drain D3. Will gradually rise. Since the current supply drain D3 is the second clamp source S22 of the second clamp P-type MOS transistor MP2, the voltage of the current supply drain D3 will cause the second clamp P-type MOS semi-transistor MP2 is turned on. The voltage of the current supply drain D3 is also the drive voltage Vp of the power gate G0 of the control power MOS transistor MP0. Therefore, the power MOS transistor MP0 will be turned off at the voltage rise of the current supply drain D3.

When the switching signal IN is in a low state, the first switching N-type MOS transistor MN1 is turned off and the second switching N-type MOS transistor MN2 is turned on. The closing of the first switch N-type MOS transistor MN1 will stop the current source 100, so that the voltage of the first clamp source S12 of the first clamp P-type MOS transistor M1, that is, The voltage of the current supply gate G3 that controls the second clamp P-type MOS transistor MP3 will be pulled up, further closing the second clamp P-type MOS transistor MP3. Moreover, the capacitor string 14 can rapidly couple the inverted switching signal IN (ie, the high-state signal) to the current supply gate G3 of the second clamp P-type MOS transistor MP3, speeding up the second clamp P-type The closing speed of the gold oxide semi-electric crystal MP3.

On the other hand, after the second switch N-type MOS transistor MN2 is turned on, since the second clamp P-type MOS transistor MP3 is turned off, the second switch N-type MOS transistor MN2 will be originally taken by the second The clamped P-type MOS transistor MP3 supplies current to the current supply drain D3, so the voltage of the current supply drain D3 will gradually decrease. Since the current supply drain D3 is the second clamp source S22 of the second clamp P-type MOS transistor MP2, the voltage of the final current supply drain D3 will cause the second clamp P-type MOS semi-electric The crystal MP2 can no longer be turned on and turned off.

However, it should be noted that if the threshold voltage of the second clamp P-type MOS transistor is Vth, since the voltage received by the second clamp gate G22 is the reference voltage Vm, the current is supplied to the drain D3. When the voltage drops to the sum of the reference voltage Vm and the threshold voltage Vth of the second clamp P-type MOS transistor (ie, Vm+Vth), the second clamp P-type MOS transistor MP2 is turned off, and further The second switch N-type MOS transistor MN2 can no longer draw current. Therefore, the voltage of the current supply drain D3 is only reduced to Vm + Vth and can no longer be lowered.

The voltage of the current supply drain D3 is also the drive voltage Vp of the power gate G0 of the control power MOS transistor MP0, so the power MOS transistor MP0 will be turned on at the voltage drop of the current supply drain D3. Since the voltage of the current supply drain D3 is only reduced to Vm+Vth at the lowest, the voltage difference between the driving voltage Vp and the first potential VGH will be less than a specific voltage value. In this embodiment, the specific voltage value is VGH - (Vm + Vth).

In an embodiment, the value of the reference voltage Vm can be set to be the difference between the first potential VGH and the highest withstand voltage of the power gate G0. If the maximum withstand voltage of the power gate G0 is 5 volts, the value of the reference voltage Vm can be set to VGH-5. Therefore, the specific voltage value at which the voltage difference between the driving voltage Vp and the first potential VGH is smaller than VGH-(VGH-5+Vth)=5-Vth. The value of the driving voltage Vp can be clamped to 5 volts or less by the design of the driving circuit 1.

Therefore, the driving circuit 1 for driving the power MOS transistor MPO in the present disclosure can ensure that the value of the driving voltage Vp is limited to the voltage range that the power gate G0 of the power MOS transistor M0 can withstand, The power MOS transistor M0 can be maintained under normal driving operation by the driving circuit 1. Moreover, the arrangement of the capacitor string 14 accelerates the reaction time of the overall driving circuit 1, and the transmission delay time of the driving circuit can be accelerated by less than 100 nanoseconds.

Please refer to Figure 2. FIG. 2 is a circuit diagram of a driving circuit 2 in another embodiment of the disclosure. The driving circuit 2 is used to drive the power MOS transistor MN0. Similarly, in the present embodiment, the power MOS transistor MN0 is an N-type high voltage MOS transistor.

The drive circuit 2 includes a first drive branch 20, a second drive branch 22, and a capacitor string 24. The first driving branch 20 includes a first switch P-type MOS transistor MP1, a current source 200, and a first clamp P-type MOS transistor MN1.

The first switch P-type MOS transistor MP1 has a first switching gate G11 for receiving the switching signal IN . The first switch P-type MOS transistor M1 further has a first switching source S11 to be connected to the second potential VDD.

The first clamp N-type MOS transistor MN1 has a first clamp gate G12 for receiving the reference voltage Vm. The first clamped drain D12 of the first clamped N-type MOS transistor MN1 is connected to the first switch drain D11 of the first switch P-type MOS transistor M1, and the first clamp N-type gold The first clamp source S12 of the oxygen semiconductor MN1 is connected to the current source 200.

The second driving branch 22 includes a second switch P-type MOS transistor MP2, a second clamp N-type MOS transistor MN2, and a current supply N-type MOS transistor MN3. The second switch P-type MOS transistor MP2 has a second switch gate G21 for receiving the inverted switching signal .

The current supply N-type MOS transistor MN3 has a current supply gate G3 connected to the first clamp source S12 and a current supply source S3 connected to the first potential VGL. The second clamp N-type MOS transistor MN2 has a second clamp gate G22 for receiving the reference voltage Vm. The second clamped drain D22 of the second clamp N-type MOS transistor MN2 is connected to the second switch drain D22 of the second switch P-type MOS transistor Q2, and the second clamp N-type gold The second clamp source S22 of the oxygen semiconductor MN2 is connected to the current supply drain D3 of the current supply P-type MOS transistor MN3. The second clamp source S22 outputs the driving voltage Vp to the power gate G0 of the power MOS transistor MN0.

In one embodiment, the first potential VGL is a negative potential, and the second potential VDD is greater than a potential of the first potential VGL.

The capacitor string 24 includes a plurality of capacitors connected in series, and the first end thereof receives the inverted switching signal The second end is connected to the current supply gate G3 of the current supply N-type MOS transistor MN3 to turn the inverted switching signal Coupled to current supply gate G3.

Therefore, when the switching signal IN is in a low state, the first switch P-type MOS transistor M1 is turned on and the second switch P-type MOS transistor MP2 is turned off. The conduction of the first switch P-type MOS transistor MP1 will provide a large current, and its ability to supply current will be greater than the current drawn by current source 200. flow. Therefore, the voltage of the first clamp source S12 of the first clamp N-type MOS transistor MN1, that is, the voltage of the current supply gate G3 for controlling the second clamp N-type MOS transistor MN3 will follow It is pulled up to further turn on the second clamp N-type oxynitride MN3. Moreover, the capacitor string 24 can rapidly couple the inverted switching signal IN (ie, the low signal) to the current supply gate G3 of the second clamp N-type MOS transistor MN3, speeding up the second clamp N-type. The conduction speed of the gold-oxide semi-transistor MP3.

On the other hand, after the second switch P-type MOS transistor MP2 is turned off, since the second clamp N-type MOS transistor MN3 is turned on to draw current to the current supply drain D3, the current supplies the voltage of the drain D3. Will gradually decline. Since the current supply drain D3 is the second clamp source S22 of the second clamp N-type MOS transistor MN2, the voltage of the current supply drain D3 will cause the second clamp N-type MOS semi-transistor MN2 is turned on. The voltage of the current supply drain D3 is also the drive voltage Vp of the power gate G0 of the control power MOS transistor MN0, so the power MOS transistor MN0 will be turned off at the voltage drop of the current supply drain D3.

When the switching signal IN is in a high state, the first switch P-type MOS transistor M1 is turned off and the second switch P-type MOS transistor MP2 is turned on. The closing of the first switch P-type MOS transistor MP1 will stop supplying current, and the current source 100 continues to draw current, so that the first clamp source S12 of the first clamp N-type MOS transistor MN1 will be made. The voltage, that is, the voltage of the current supply gate G3 that controls the second clamp N-type oxynitride MN3, will be pulled down, further closing the second clamped N-type MOS transistor MP3. Moreover, the capacitor string 24 can rapidly couple the inverted switching signal IN (ie, the low signal) to the second clamp N-type MOS transistor. The current supply of the MN3 is supplied to the gate G3 to speed up the closing speed of the second clamp N-type MOS transistor MP3.

On the other hand, after the second switch P-type MOS transistor MP2 is turned on, since the second clamp N-type MOS transistor MN3 is turned off, the second switch P-type MOS transistor M2 will supply current to the supply 汲The pole D3, so the voltage of the current supply drain D3 will gradually rise. Since the current supply drain D3 is the second clamp source S22 of the second clamp N-type MOS transistor MN2, the voltage of the final current supply drain D3 will make the second clamp N-type MOS semi-electric The crystal MN2 can no longer be turned on and turned off.

However, it should be noted that if the threshold voltage of the second clamp N-type MOS transistor MN2 is Vth, since the voltage received by the second clamp gate G22 is the reference voltage Vm, the current is supplied to the drain D3. When the voltage rises to the difference between the reference voltage Vm and the threshold voltage Vth of the second clamp P-type MOS transistor (ie, Vm-Vth), the second clamp P-type MOS transistor MN2 is turned off, and further The second switch N-type MOS transistor MP2 is no longer able to supply current to the current supply drain D3. Therefore, the voltage of the current supply drain D3 can only rise up to Vm-Vth and cannot rise any more.

The voltage of the current supply drain D3 is also the drive voltage Vp of the power gate G0 of the control power MOS transistor MN0, so the power MOS transistor MN0 will be turned on at the voltage rise of the current supply drain D3. Since the voltage of the current supply drain D3 rises up to only Vm-Vth, the voltage difference between the driving voltage Vp and the first potential VGH will be less than a specific voltage value. In this embodiment, the specific voltage value is (Vm - Vth) - VGL.

In one embodiment, the value of the reference voltage Vm can be set to the sum of the first potential VGL and the highest withstand voltage of the power gate G0. Such as power gate G0 The maximum withstand voltage is 5 volts, and the value of the reference voltage Vm can be set to VGL+5. Therefore, the specific voltage value at which the voltage difference between the driving voltage Vp and the first potential VGH is smaller than (VGL + 5 - Vth) - VGL = 5 - Vth. The value of the driving voltage Vp can be clamped to 5 volts or less by the design of the driving circuit 1.

Therefore, the driving circuit 2 for driving the power MOS transistor MN0 in the present disclosure can ensure that the value of the driving voltage Vp is limited to the voltage range that the power gate G0 of the power MOS transistor MN0 can withstand, The power MOS semi-transistor MN0 can be maintained under normal driving by the driving circuit 2. Moreover, the arrangement of the capacitor string 24 accelerates the reaction time of the overall driving circuit 2, and the transmission delay time of the driving circuit can be accelerated by less than 100 nanoseconds.

The present disclosure has been disclosed in the above embodiments, but it is not intended to limit the disclosure, and any person skilled in the art can make various changes and refinements without departing from the spirit and scope of the disclosure. The scope of protection of the disclosure is subject to the definition of the scope of the patent application.

1, 2‧‧‧ drive circuit

10, 20‧‧‧ first drive branch

100, 200‧‧‧ current source

12, 22‧‧‧Second drive branch

14, 24‧‧‧ capacitance string

The above and other objects, features, advantages and embodiments of the present disclosure will become more apparent and understood. 2 is a circuit diagram of a driving circuit in another embodiment of the disclosure.

1‧‧‧Drive circuit

10‧‧‧First drive branch

100‧‧‧current source

12‧‧‧Second drive branch

14‧‧‧Capacitor string

Claims (16)

A driving circuit for driving a power metal-oxide semiconductor (MOS) transistor, comprising: a first driving branch, comprising: a first switching N-type MOS transistor, having a first a switching gate for receiving a switching signal; a current source; and a first clamping P-type MOS transistor having a first clamping gate for receiving a reference voltage, wherein the One of the first clamp P-type MOS transistors is connected to the first switch drain of the first switch N-type MOS transistor, the first clamp P-type MOS half One of the first clamp source of the transistor is connected to the current source; and a second drive branch comprises: a second switch N-type MOS transistor having a second switch gate for receiving the reverse phase The switching signal; a current supply P-type MOS transistor having a current supply gate connected to one of the first clamp source and a current supply source connected to a first potential; and a second Clamping a P-type MOS transistor having a second clamping gate for receiving the reference voltage, One of the second clamped P-type MOS transistors is connected to the second switch drain of the second switch N-type MOS transistor, the second clamp P-type gold One of the oxygen semi-transistors is connected to the second clamp source of the current supply P-type MOS transistor, wherein the second clamp source a pole outputs a driving voltage to a power gate of the power MOS transistor; and a capacitor string comprising a plurality of capacitors connected in series, the first end of the capacitor string is configured to receive the inverted switching signal, A second end of the capacitor string is coupled to the current supply gate of the current supply P-type MOS transistor to couple the inverted switching signal to the current supply gate. The driving circuit of claim 1, wherein the first potential is a positive potential. The driving circuit of claim 1, wherein the power MOS transistor is a high voltage MOS (HVMOS). The driving circuit of claim 3, wherein a voltage difference between the driving voltage and the first potential is less than a specific voltage value. The driving circuit of claim 4, wherein a minimum value of the driving voltage is a sum of the reference voltage and a threshold voltage of the second clamped P-type MOS transistor. The driving circuit of claim 5, wherein the reference voltage is a difference between the first potential and a highest withstand voltage of the power gate. The driving circuit of claim 1, wherein when the control signal is in a first state, the first switch N-type MOS transistor is turned on and the second switch N-type MOS transistor is turned off. The capacitor string couples the inverted switching signal to the current supply gate to turn on the current supply P-type MOS transistor, further turning on the second clamp P-type MOS transistor and enabling the driving The voltage rises to turn off the power MOS transistor. The driving circuit of claim 7, wherein when the control signal is in a second state, the first switch N-type MOS transistor is turned off and the second switch N-type MOS transistor is turned on, The capacitor string couples the inverted switching signal to the current supply gate to turn off the current supply P-type MOS transistor, further turning off the second clamp P-type MOS transistor and enabling the driving The voltage drops to turn on the power MOS transistor. A driving circuit for driving a power MOS transistor, comprising: a first driving branch, comprising: a first switching P-type MOS transistor, having a first switching gate for receiving a a switching signal; a current source; and a first clamped N-type MOS transistor having a first clamping gate for receiving a reference voltage, wherein the first clamping N-type MOS transistor One of the first clamp 汲 is connected to the first switch N type a first switching drain of the MOS transistor, the first clamp source of the first clamp N-type MOS transistor is connected to the current source; and a second driving branch comprising: a first a two-switch P-type MOS transistor having a second switching gate for receiving the inverted switching signal; a current supply N-type MOS transistor having a connection to the first clamping source a current supply gate and a current supply source connected to a first potential; and a second clamp N-type MOS transistor having a second clamp gate for receiving the reference voltage, wherein One of the second clamp N-type MOS transistors is connected to the second switch drain of the second switch P-type MOS transistor, the second clamp N-type gold oxide a second clamp source of the semi-transistor is connected to the current supply drain of one of the current supply N-type MOS transistors, wherein the second clamp source outputs a driving voltage to the power MOS semi-transistor a power gate; a capacitor string comprising a plurality of capacitors connected in series, the first end of the capacitor string being used to receive the opposite Of the switch signal, one terminal of the capacitor is connected to the second string on the current supply metal oxide semiconductor transistor gate of the N-type current supply pole, the switch signal is coupled to the inverting of current supply to the gate. The driving circuit of claim 9, wherein the first potential is a negative potential. The driving circuit of claim 9, wherein the power is golden and half The transistor is a high voltage MOS semi-electrode. The driving circuit of claim 11, wherein a voltage difference between the driving voltage and the first potential is less than a specific voltage value. The driving circuit of claim 12, wherein a maximum value of the driving voltage is a difference between the reference voltage and a threshold voltage of the second clamped N-type MOS transistor. The driving circuit of claim 13, wherein the reference voltage is a sum of the first potential and a highest withstand voltage of the power gate. The driving circuit of claim 9, wherein when the control signal is in a first state, the first switch P-type MOS transistor is turned on and the second switch P-type MOS transistor is turned off. The capacitor string couples the inverted switching signal to the current supply gate to turn on the current supply N-type MOS transistor, further turning on the second clamp N-type MOS transistor and enabling the driving The voltage drops to turn off the power MOS transistor. The driving circuit of claim 15, wherein when the control signal is in a second state, the first switch P-type MOS transistor is turned off and the second switch P-type MOS transistor is turned on, The capacitor string couples the inverted switching signal to the current supply gate to turn on the current supply N-type MOS transistor, and further causes the second clamp N-type MOS semi-electrode The body is turned off and the driving voltage is raised to turn on the power MOS transistor.