CN110212880B - Charge amplifier circuit and time sequence control method thereof - Google Patents
Charge amplifier circuit and time sequence control method thereof Download PDFInfo
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- CN110212880B CN110212880B CN201910597564.0A CN201910597564A CN110212880B CN 110212880 B CN110212880 B CN 110212880B CN 201910597564 A CN201910597564 A CN 201910597564A CN 110212880 B CN110212880 B CN 110212880B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/70—Charge amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
Abstract
The invention discloses a charge amplifier circuit, which comprises a first capacitor Cb, a second capacitor Cf, an operational amplifier U1, a first switch P1, a second switch P2, a third switch P3, a fourth switch P4, a fifth switch P5, a sixth switch P6 and a seventh switch P7. The invention also discloses a time sequence control method of the charge amplifier circuit. According to the charge amplifier circuit and the time sequence control method thereof, the voltage for charging the first capacitor Cb in the first control phase stage and the steady-state voltage of the second polar plate of the first capacitor Cb in the second control phase stage are changed, so that the supportable self-capacitance range of the screen body is enlarged under the condition of a certain first capacitor Cb and a certain second capacitor Cf, the circuit performance is optimized, the physical layout area is reduced, and the cost of a single chip is reduced.
Description
Technical Field
The present invention relates to the field of amplifier circuits, and more particularly, to a charge amplifier circuit and a timing control method thereof.
Background
In recent years, with the rapid popularization of intelligent terminals (smart phones, smart tablets, etc.), touch screen control technology has rapidly developed. The touch screen senses the touch of the finger, converts the touch signal of the finger into a voltage signal, processes the signal and sends the voltage signal to the upper control system, and the upper control system calculates and identifies the action of the finger through an algorithm and gives corresponding feedback. Currently, there are two main types of widely used touch screens: resistive and capacitive screens are becoming dominant as technology advances day by day. In a capacitive screen system, the touch of a finger is a change in capacitance in terms of electrical characteristics, and the capacitance is a circuit basic unit for storing electric charges, so sensing the touch of a finger is essentially sensing the change in electric charges and converting it into the change in voltage. A charge amplifier is a device, circuit or apparatus for converting a charge signal into a voltage signal, and has been widely used in various sensors.
In the field of integrated circuit design, the physical layout area of a circuit directly determines the cost of a single chip, and is an important index of the design. In the prior art of the charge amplifier, to support larger self-capacitance of the screen body, two capacitors which are needed to be used in the charge amplifier are larger, and the large capacitors occupy larger physical layout area, so that the cost of the chip is increased. Therefore, it is necessary to study how to reduce the physical layout area of the charge amplifier circuit without significantly degrading the performance of the circuit.
Disclosure of Invention
The present invention is directed to a charge amplifier circuit and a timing control method thereof, which address the above-mentioned drawbacks of the prior art.
The technical scheme adopted for solving the technical problems is as follows: according to an aspect of the present invention, there is provided a charge amplifier circuit comprising: the first capacitor Cb, the second capacitor Cf, the operational amplifier U1, the first switch P1, the second switch P2, the third switch P3, the fourth switch P4, the fifth switch P5, the sixth switch P6 and the seventh switch P7;
specifically, one end of the first switch P1 and one end of the second switch P2 are both connected with a first polar plate of a self-capacitance Cs of a screen body of the touch screen, the other end of the first switch P1 is grounded, the other end of the second switch P2 is connected with one end of the third switch P3, one end of the fourth switch P4 and the first polar plate of the first capacitance Cb, the other end of the fourth switch P4 is connected with the first reference voltage V1, the second polar plate of the first capacitance Cb is connected with one end of the fifth switch P5 and one end of the sixth switch P6, the other end of the fifth switch P5 is grounded, and the other end of the sixth switch P6 is connected with the first reference voltage V1;
specifically, the other end of the third switch P3 is connected to the inverting input terminal Vn of the operational amplifier U1, the first polar plate of the second capacitor Cf, and one end of the seventh switch P7, the non-inverting input terminal Vp of the operational amplifier U1 is connected to the second reference voltage V2, and the output terminal Vo of the operational amplifier U1 is connected to the second polar plate of the second capacitor Cf and the other end of the seventh switch P7 to form a circuit output terminal Vo3; the first reference voltage V1 is not equal to the second reference voltage V2.
Preferably, the first control phase is when the first switch P1, the fourth switch P4, the fifth switch P5 and the seventh switch P7 are turned on, and the second switch P2, the third switch P3 and the sixth switch P6 are turned off;
when the first switch P1, the fourth switch P4, the fifth switch P5 and the seventh switch P7 are turned off, and the second switch P2, the third switch P3 and the sixth switch P6 are turned on, the phase is controlled.
Preferably, a third control phase stage is also included between the first control phase stage and the second control phase stage;
when the second switch P2 and the fifth switch P5 are turned on, and the first switch P1, the third switch P3, the fourth switch P4, the sixth switch P6 and the seventh switch P7 are turned off, the phase is controlled in a third phase.
Preferably, in the first control phase, the first reference voltage V1 charges the first capacitor Cb, and after the charging is completed, the first plate of the first capacitor Cb has a charge of Q 3 ，Q 3 The calculation formula of (2) is as follows:
Q 3 ＝V1*C b (1)
in the second control phase, the charge of the first plate of the first capacitor Cb is Q 4 ，Q 4 The calculation formula of (2) is as follows:
Q 4 ＝V2*C S +(V2-V O3 )*C f +(V2-V1)*C b (2)
q is according to the law of conservation of charge 3 ＝Q 4 Vo3 is calculated according to the calculation formulas (1) and (2), and the calculation formula of Vo3 is as follows:
according to the calculation formula (3), the calculation formula of the supportable screen self-capacitance Cs is:
preferably, when Vo3 in the calculation formula (4) is equal to the highest voltage in the circuit, cs is the maximum self-capacitance of the screen body that can be supported by the charge amplifier circuit; the highest voltage is the supply voltage Vdda.
Preferably, in the third control phase stage,a part of the electric charge of the first electrode plate of the first capacitor Cb flows to the self-capacitance Cs of the screen body, and when the electric charge is in a steady state, the voltage of the first electrode plate of the first capacitor Cb is V A ，V A The calculation formula of (2) is as follows:
V A *(C b +C S )＝V1*C b (5)
thereby making it
According to another aspect of the present invention, there is provided a timing control method of a charge amplifier circuit for performing timing control of the charge amplifier circuit described above, comprising the steps of:
controlling the charge amplifier circuit to enter a first control phase stage for charging the first capacitor Cb by a first reference voltage V1;
and controlling the charge amplifier circuit to enter a second control phase stage for calculating the output steady-state voltage value of the charge amplifier, so as to reversely calculate the maximum self-capacitance Cs of the screen body which can be supported.
Preferably, the first control phase is when the first switch P1, the fourth switch P4, the fifth switch P5 and the seventh switch P7 are turned on, and the second switch P2, the third switch P3 and the sixth switch P6 are turned off;
when the second switch P2, the third switch P3 and the sixth switch P6 are turned on, and the first switch P1, the fourth switch P4, the fifth switch P5 and the seventh switch P7 are turned off, the second control phase stage is performed.
Preferably, the charge amplifier circuit is controlled to enter a third control phase stage for reducing the steady-state voltage of the first plate of the first capacitance Cb before entering the second control phase stage.
Preferably, the third control phase is performed when the second switch P2 and the fifth switch P5 are turned on, and the first switch P1, the third switch P3, the fourth switch P4, the sixth switch P6 and the seventh switch P7 are turned off.
Implementation of the charge amplification of the present inventionThe technical scheme of the device circuit and the time sequence control method thereof has the following advantages or beneficial effects: the charge amplifier circuit of the present invention applies the first control phase to the first capacitor C by changing the first control phase b The charged voltage and the steady-state voltage of the second polar plate of the first capacitor Cb in the second control phase stage ensure that the supportable maximum self-capacitance of the screen body is increased under the condition of a certain first capacitor Cb and a certain second capacitor Cf, the circuit performance is optimized, the physical layout area is reduced, and the cost of a single chip is reduced.
Drawings
For a clearer description of the technical solutions of embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art, in which:
FIG. 1 is a schematic diagram of a prior art charge amplifier circuit;
FIG. 2 is an equivalent circuit schematic diagram of a first control phase stage of the prior art;
FIG. 3 is an equivalent circuit schematic diagram of a second control phase stage of the prior art;
FIG. 4 is a prior art schematic diagram of a switching sequence;
FIG. 5 is a circuit schematic of an embodiment of a charge amplifier circuit of the present invention;
FIG. 6 is a circuit schematic of a pass gate switch of an embodiment of a charge amplifier circuit of the present invention;
FIG. 7 is an equivalent circuit schematic diagram of a first control phase stage of the present invention;
FIG. 8 is an equivalent circuit schematic diagram of a second control phase stage of the present invention;
FIG. 9 is an equivalent circuit schematic diagram of a third phase control stage of the present invention;
FIG. 10 is a schematic diagram of a switching sequence of a first embodiment of a charge amplifier circuit according to the present invention;
fig. 11 is a schematic diagram of a switching sequence of a charge amplifier circuit according to a second embodiment of the present invention.
Detailed Description
For a better understanding of the objects, technical solutions and advantages of the present invention, reference should be made to the various exemplary embodiments described hereinafter with reference to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration various exemplary embodiments in which the invention may be practiced, and in which like numerals in the various figures designate identical or similar elements unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present disclosure. It is to be understood that they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure as set forth in the appended claims, other embodiments may be utilized, or structural and functional modifications may be made to the embodiments set forth herein, without departing from the scope and spirit of the present disclosure. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
In the description of the present invention, it should be understood that the terms "first," second, "… …," and "seventh" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature of a "first", "second", … …, or "seventh" limitation may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise. It should be noted that the terms "coupled," "connected," and "connected" are to be construed broadly, and may be, for example, electrically connected or may communicate with each other, unless explicitly stated or limited otherwise; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In order to illustrate the technical scheme of the invention, the following description is made by specific examples. Fig. 5-11 show schematic circuit diagrams provided by embodiments of the present invention, and only portions relevant to the embodiments of the present invention are shown for convenience of explanation.
Fig. 1-4 show a schematic circuit diagram and operational timing of a prior art charge amplifier. The charge amplifier principle in the prior art is shown in fig. 1, and the basic working principle of the circuit is as follows: p1 and P2 are switch control signals, which are provided by the clock of the chip, and P1 and P2 can also be called two phase control switches. In the first control phase, the switch controlled by P1 is turned on, the switch controlled by P2 is turned off, and the corresponding equivalent circuit is shown in FIG. 2; in the second control phase, the switch controlled by P1 is turned off, the switch controlled by P2 is turned on, and the corresponding equivalent circuit is shown in fig. 3.
In the first control phase, the charge of the self-capacitance Cs of the panel is reset and cleared, the input and output terminals of the operational amplifier are in reset state, the second reference voltage V2 charges the first capacitance Cb, and after the charging is completed, the charge of the first polar plate of the first capacitance Cb is Q 1 ，Q 1 The calculation formula of (2) is as follows:
Q 1 ＝V2*C b (11)
in the second control phase, the charges on the first plate of the first capacitor Cb are redistributed, a part of the charges charge is charged to the self-capacitance Cs of the panel, and another part of the charges is charged to the second capacitor Cf, and in steady state, the voltages of the first plate and the second plate of the first capacitor Cb are V2, so that the two plates of the first capacitor Cb have no charges. In steady state, the total charge of the first capacitor Cs and the second capacitor Cf is Q 2 ，Q 2 The calculation formula of (2) is as follows:
Q 2 ＝V2*C S +(V2-V O2 )*C f (12)
q is according to the law of conservation of charge 1 ＝Q 2 And according to the calculation formulas (11) and (12), the following steps are obtained:
the calculation formula (13) is the steady-state output voltage of the charge amplifier after the second control phase is stable. When a finger touches the screen, the change of the self-capacitance Cs of the screen body can be equivalently considered to be changed, the charge amplifier converts the change of the self-capacitance Cs of the screen body into the change of voltage according to a calculation formula (13), the voltage is transmitted to the analog-digital converter to convert the analog voltage into digital output, then the digital output is provided for the digital module to be stored, software reads the digital value, whether the finger touches the screen or not is determined, and if the finger touches the screen, the corresponding coordinates of a touch point are given.
Because of the large difference of manufacturing materials, production and manufacturing processes and flows, the self-capacitance difference of the screen body of the touch screen is large, and the capacitance value of the self-capacitance of the screen body of the touch screen commonly used in the market at present is small and only a few picofarads, and the self-capacitance value of the screen body of the touch screen can be as large as hundreds of picofarads. Therefore, an important technical index of the charge amplifier is the range of the self-capacitance of the screen body of the touch screen which can be supported, and the support of the small self-capacitance of the screen body is easy, and the support of the large self-capacitance of the screen body is limited by the cost of the chip. A good charge amplifier must be able to accommodate a wide range of varying screen self-capacitance, and in particular be able to support a sufficiently large screen self-capacitance.
From the calculation formula (13):
cs in the calculation formula (14) when Vo2 is equal to the highest voltage (power supply voltage Vdda) in the circuit is the largest self-capacitance of the screen body that can be supported by the charge amplifier, and Cb and Cf need to be as large as possible in order to support the self-capacitance Cs of the screen body with enough size; cb. Cf is increased, chip layout area is increased, and cost of a single chip is increased. Therefore, a contradiction is generated in terms of chip area (chip cost) and chip performance (the maximum self-capacitance of the screen body of the touch screen that can be supported), and in order to solve the contradiction, the invention provides a novel charge amplifier circuit and a timing control method thereof.
Embodiment one:
fig. 5 shows a schematic circuit diagram of an embodiment of the charge amplifier circuit of the present invention. Unlike the prior art, the circuit of the present invention changes the voltage charged to the first capacitor Cb in the first control phase and the steady-state voltage of the second plate of the first capacitor Cb in the second control phase, and the operation timing thereof remains the same as the prior art.
In this embodiment, the charge amplifier circuit of the present invention includes a first capacitor Cb, a second capacitor Cf, an operational amplifier U1, a first switch P1, a second switch P2, a third switch P3, a fourth switch P4, a fifth switch P5, a sixth switch P6, and a seventh switch P7. Preferably, the first switch P1, the second switch P2, the third switch P3, the fourth switch P4, the fifth switch P5, the sixth switch P6 and the seventh switch P7 are all identical in circuit implementation, and are merely distinguished for convenience of description.
In this embodiment, one end of the first switch P1 and one end of the second switch P2 are both connected to the first plate of the self-capacitance Cs of the touch screen, the other end of the first switch P1 is grounded, the other end of the second switch P2 is connected to one end of the third switch P3, one end of the fourth switch P4 and the first plate of the first capacitance Cb, the other end of the fourth switch P4 is connected to the first reference voltage V1, the second plate of the first capacitance Cb is connected to one end of the fifth switch P5 and one end of the sixth switch P6, the other end of the fifth switch P5 is grounded, and the other end of the sixth switch P6 is connected to the first reference voltage V1; the other end of the third switch P3 is connected with the inverting input end Vn of the operational amplifier U1, the first polar plate of the second capacitor Cf and one end of the seventh switch P7, the non-inverting input end Vp of the operational amplifier U1 is connected with the second reference voltage V2, and the output end Vo of the operational amplifier U1 is connected with the second polar plate of the second capacitor Cf and the other end of the seventh switch P7 to form a circuit output end Vo3; specifically, the first reference voltage V1 is not equal to the second reference voltage V2.
In this embodiment, the method for controlling the timing of the charge amplifier circuit is used for controlling the timing of the charge amplifier circuit, and includes the steps of:
controlling the charge amplifier circuit to enter a first control phase stage for charging the first capacitor Cb by a first reference voltage V1; specifically, when the first switch P1, the fourth switch P4, the fifth switch P5 and the seventh switch P7 are turned on, and the second switch P2, the third switch P3 and the sixth switch P6 are turned off, the phase is the first control phase;
the charge amplifier circuit is controlled to enter a second control phase stage, and the second control phase stage is used for calculating the output steady-state voltage value of the charge amplifier, so that the maximum self-capacitance Cs of the screen body which can be supported is calculated in a back-pushing mode; specifically, the second control phase is performed when the first switch P1, the fourth switch P4, the fifth switch P5, and the seventh switch P7 are turned off, and the second switch P2, the third switch P3, and the sixth switch P6 are turned on.
In the first control phase, the first reference voltage V1 charges the first capacitor Cb, and after the charging is completed, the charge of the first plate of the first capacitor Cb is Q 3 ，Q 3 The calculation formula of (2) is as follows:
Q 3 ＝V1*C b (1)
in the second control phase, the charge of the first plate of the first capacitor Cb is Q 4 ，Q 4 The calculation formula of (2) is as follows:
Q 4 ＝V2*C S +(V2-V O3 )*C f +(V2-V1)*C b (2)
q is according to the law of conservation of charge 3 ＝Q 4 And then calculating according to the calculation formulas (1) and (2) to obtain Vo3, wherein the calculation formula of Vo3 is as follows:
the calculation formula (3) gives the relation between the steady-state output voltage of the new charge amplifier in the second control phase and the self-capacitance Cs of the panel, and according to the calculation formula (3), the calculation formula of the self-capacitance Cs of the panel is:
preferably, when Vo3 in the calculation formula (4) is equal to the highest voltage in the circuit, cs is the maximum self-capacitance of the panel supported by the charge amplifier circuit, and specifically, the highest voltage is typically the power voltage Vdda.
Comparing the calculation formula (4) with the calculation formula (14), the front half part (the part related to Cf) is basically the same, the rear half part (the part related to Cb) is different, and when the second reference voltage V2 is smaller than the first reference voltage V1, the maximum self-capacitance of the screen body which can be supported by the invention is larger than the maximum self-capacitance of the screen body which can be supported by the prior art. In a general circuit, the second reference voltage V2 is half of the power voltage Vdda (i.e. v2=vdda/2), and even lower voltage, the first reference voltage V1 is equal to the power voltage Vdda, and at this time, the self-capacitance of the panel body supported by the present invention is larger.
From circuit principle analysis, compared with the prior art, in the process of switching from a first control phase stage to a second control phase stage, the voltage difference of the two pole plates of the first capacitor Cb has larger abrupt change, the abrupt change amount of the voltage difference of the first capacitor Cb determines the maximum total electric charge amount which can be provided for the screen self-capacitance Cs and the second capacitor Cf in the second control phase stage, and the larger the abrupt change amount is, the larger the total electric charge amount is provided, and the larger the screen self-capacitance Cs can be supported. The switching sequences of the two control phase stages of all switches in fig. 5 are the same as those used in the prior art, as shown in fig. 10, and will not be described here.
In the present embodiment, the voltage of the first plate of the first capacitor Cb easily overshoots to the highest potential (power supply voltage Vdda) in the circuit, and even possibly exceeds the power supply voltage Vdda. In the first control phase, the voltage of the first polar plate of the first capacitor Cb is V1, the voltage of the second polar plate is 0, when the first control phase is switched to the second control phase, the voltage of the second polar plate of the first capacitor Cb is raised to V1 instantaneously, when the charge discharging speed of the point a in the circuit is not fast enough, the voltage of the point a is more likely to be up to exceed the power voltage Vdda, theoretically, if the point a has no charge discharging at this time, the voltage of the first polar plate of the first capacitor Cb will reach 2 x Vdda twice the power voltage at the highest.
Fig. 6 shows a schematic diagram of a specific implementation circuit of a switch in the present invention, including a transmission gate switch TG, where the transmission gate switch TG includes a PMOS tube and an NMOS tube connected in parallel, a substrate of the PMOS tube is connected to a power supply voltage Vdda, and a substrate of the NMOS tube is connected to a common ground GND. Specifically, the substrate of the PMOS transistor is connected to the highest potential (power supply voltage Vdda) of the circuit, and the substrate of the NMOS transistor is connected to the lowest potential GND of the circuit. Under normal conditions, the source-drain voltage of the PMOS tube cannot exceed the power supply voltage Vdda, and the parasitic pn junction formed by the source-drain of the PMOS tube and the substrate and the parasitic pn junction formed by the source-drain of the NMOS tube and the substrate in the transmission gate switch are reverse biased, so that current cannot be formed. When the voltage at point a exceeds the supply voltage Vdda, the parasitic pn junction that was originally reverse biased becomes forward biased, forming a large forward current, and charge is discharged from this path to the supply, resulting in an undesirable change in the output voltage of the charge amplifier. The basic function of the charge amplifier is that the output voltage is required to be capable of reflecting the change of the detected self-capacitance only, and once other factors in the circuit (such as charge leakage caused by voltage overshoot of the first polar plate of the first capacitance Cb) also change the output voltage, the touch signal of the finger may be disturbed, even completely submerged by the leakage phenomenon, so that the charge amplifier cannot work normally.
Embodiment two:
in this embodiment, the charge amplifier circuit principle is substantially the same as that of the first embodiment, and the steady-state output voltage theoretical derivation is indistinguishable from that of the first embodiment, and the steady-state output voltage theoretical expression is the same as that of the calculation formula (3). Unlike the first embodiment, the control phase state of the charge amplifier is increased from the original two to three, and an intermediate phase is added, which is referred to as a third control phase for convenience of comparison with the first embodiment. The corresponding equivalent circuit schematic diagram for each control phase is shown in fig. 7-9. The introduction of the third control phase stage makes the change of the voltage of the first polar plate (point A) of the first capacitor Cb become gentle in the process of switching from the first control phase stage to the second control phase stage, thereby greatly reducing the voltage overshoot of the point A and avoiding the problem of charge leakage caused by overhigh voltage of the point A.
As shown in fig. 11, a switching timing control flowchart of the charge amplifier circuit according to the present invention is used for timing control of the charge amplifier circuit, and includes the steps of:
controlling the charge amplifier circuit to enter a first control phase stage for charging the first capacitor Cb by a first reference voltage V1;
controlling the charge amplifier circuit to enter a third control phase stage for reducing the steady-state voltage of the first plate of the first capacitor Cb before entering the second control phase stage;
and controlling the charge amplifier circuit to enter a second control phase stage for calculating the output steady-state voltage value of the charge amplifier, so as to reversely calculate the maximum self-capacitance Cs of the screen body which can be supported.
More specifically, the first control phase is when the first switch P1, the fourth switch P4, the fifth switch P5 and the seventh switch P7 are turned on, and the second switch P2, the third switch P3 and the sixth switch P6 are turned off.
In the first control phase, the equivalent circuit schematic diagram is shown in fig. 7, and the same working principle as that of the first control phase of the first embodiment is that the first reference voltage V1 is used to charge the first capacitor Cb, and the first control phase of the first embodiment directly enters the second control phase after completion, and the first control phase of the first embodiment enters the third control phase after completion.
When the second switch P2 and the fifth switch P5 are turned on and the first switch P1, the third switch P3, the fourth switch P4, the sixth switch P6 and the seventh switch P7 are turned off, the phase is controlled in the third phase. In the third control phase, as shown in FIG. 8, the charge on the first plate of the first capacitor Cb is redistributed, a part of the charge remains on the first capacitor Cb, a part of the charge flows to the panel self-capacitance Cs, and the charge ratio is dependent on the capacitance ratio of Cb to Cs, specifically, a part of the charge on the first plate of the first capacitor Cb flows to the panel self-capacitance Cs, when the power supply is turned onWhen the load is in a steady state, the voltage of the first polar plate of the first capacitor Cb is V A ，V A The calculation formula of (2) is as follows:
V A *(C b +C S )＝V1*C b (5)
thereby making it
If Cb=Cs, then V A The voltage of the first plate corresponding to the first capacitor Cb is reduced by half from the original V1. If Cb is<Cs will be lower in voltage and V in the third control phase A The voltage will facilitate switching to the second control phase V A The voltage is not too much in overshoot, ensure V A The voltage is not higher than the power supply voltage Vdda, so that the electric leakage of the switch is avoided. The third control phase is switched to the second control phase after stabilization.
The second control phase is when the second switch P2, the third switch P3 and the sixth switch P6 are turned on, and the first switch P1, the fourth switch P4, the fifth switch P5 and the seventh switch P7 are turned off. In the second control phase, as shown in fig. 9, it can be seen that the second control phase of the present embodiment is identical to the first control phase of the first embodiment, and the point a charges on the first plate of the first capacitor Cb are redistributed again, and a part of the charges flow to the second capacitor Cf. The calculation formulas (1), (2) and (3) in the first embodiment are still true in the present embodiment.
In the second control phase, the calculation formula of the circuit output end Vo4 is:
the calculation formulas (7) and (3) are the same, and the maximum self-capacitance of the screen body that can be supported in the second embodiment is the same as that in the first embodiment.
According to the charge amplifier circuit, the voltage for charging the first capacitor Cb in the first control phase stage and the steady-state voltage of the second polar plate of the first capacitor Cb in the second control phase stage are changed, so that the supportable maximum self-capacitance range of the screen body is enlarged under the condition of a certain first capacitor Cb and a certain second capacitor Cf, the circuit performance is optimized, the layout area is reduced, and the cost of a single chip is reduced.
The foregoing is only a preferred embodiment of the invention, and it will be appreciated by those skilled in the art that various changes in the features and embodiments may be made and equivalents may be substituted without departing from the spirit and scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.
Claims (8)
1. A charge amplifier circuit, comprising: a first capacitor (Cb), a second capacitor (Cf), an operational amplifier (U1), a first switch (P1), a second switch (P2), a third switch (P3), a fourth switch (P4), a fifth switch (P5), a sixth switch (P6), and a seventh switch (P7);
one end of the first switch (P1) and one end of the second switch (P2) are connected with a first polar plate of a screen self-capacitance (Cs) of the touch screen, the other end of the first switch (P1) is grounded, the other end of the second switch (P2) is connected with one end of the third switch (P3), one end of the fourth switch (P4) and the first polar plate of the first capacitance (Cb), the other end of the fourth switch (P4) is connected with a first reference voltage (V1), the second polar plate of the first capacitance (Cb) is connected with one end of the fifth switch (P5) and one end of the sixth switch (P6), the other end of the fifth switch (P5) is grounded, and the other end of the sixth switch (P6) is connected with the first reference voltage (V1);
the other end of the third switch (P3) is connected with the inverting input end (Vn) of the operational amplifier (U1), the first polar plate of the second capacitor (Cf) and one end of the seventh switch (P7), the non-inverting input end (Vp) of the operational amplifier (U1) is connected with the second reference voltage (V2), and the output end (Vo) of the operational amplifier (U1) is connected with the second polar plate of the second capacitor (Cf) and the other end of the seventh switch (P7) to form a circuit output end (Vo 3); the first reference voltage (V1) is not equal to the second reference voltage (V2).
2. The charge amplifier circuit of claim 1, wherein the first control phase is when the first switch (P1), the fourth switch (P4), the fifth switch (P5) and the seventh switch (P7) are on, and the second switch (P2), the third switch (P3) and the sixth switch (P6) are off;
when the first switch (P1), the fourth switch (P4), the fifth switch (P5) and the seventh switch (P7) are turned off, and the second switch (P2), the third switch (P3) and the sixth switch (P6) are turned on, the phase is controlled in a second phase.
3. The charge amplifier circuit of claim 2, further comprising a third control phase stage between the first and second control phase stages;
and when the second switch (P2) and the fifth switch (P5) are turned on, and the first switch (P1), the third switch (P3), the fourth switch (P4), the sixth switch (P6) and the seventh switch (P7) are turned off, the phase stage is controlled by the third control phase.
4. A charge amplifier circuit according to claim 2 or 3, wherein in the first control phase, the first reference voltage (V1) charges the first capacitor (Cb), and after charging, the charge of the first plate of the first capacitor (Cb) is Q 3 The Q is 3 The calculation formula of (2) is as follows:
Q 3 ＝V1×C b （1）；
in the second control phase, the charge quantity of the first polar plate of the first capacitor (Cb) is Q 4 The Q is 4 The calculation formula of (2) is as follows:
Q 4 ＝V2×C s +(V2-V O3 )×C f +(V2-V1)×C b （2）；
according to the law of conservation of charge, the Q 3 ＝Q 4 Calculating according to the calculation formulas (1) and (2) to obtain V o3 The V is o3 The calculation formula of (2) is as follows: （3）；
according to the calculation formula (3), the self-capacitance (C s ) The calculation formula of (2) is as follows:
（4）。
5. the charge amplifier circuit of claim 4, wherein when V in the calculation formula (4) o3 When the voltage is equal to the highest voltage in the charge amplifier circuit, the Cs The maximum self-capacitance of the screen body supported by the charge amplifier circuit is obtained; the highest voltage is a power supply voltage (Vdda).
6. A charge amplifier circuit according to claim 3, characterized in that in the third control phase the first capacitance (C b ) A part of the charge of the first plate of (C) flows to the screen self-capacitance (C s ) The first capacitor C when the charge is in a steady state b The voltage of the first polar plate is V A The V is A The calculation formula of (2) is as follows:
V A ×（C b ＋C s ）＝V1×C b （5）；
thereby making it （6）。
7. A method of timing control of a charge amplifier circuit according to any one of claims 3 to 6, comprising the steps of:
controlling the charge amplifier circuit into a first control phase for applying a first reference voltage (V1) to the first capacitor (C b ) Charging;
controlling the charge amplifier circuit to enter a second control phase stage for calculating an output steady-state voltage value of the charge amplifier, thereby countering the calculation of the maximum screen self-capacitance (C s )。
8. The method of timing control of a charge amplifier circuit as set forth in claim 7, wherein said controlling said charge amplifier circuit before entering a second control phase further comprises the steps of:
controlling the charge amplifier circuit to enter a third control phase stage for reducing the first capacitance (C b ) Steady state voltage of the first plate of (c).
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| CN110419562B (en) * | 2019-09-02 | 2022-08-16 | 四川长虹电器股份有限公司 | Radio frequency unfreezing device capable of changing area of access parallel plate |
| CN111404528B (en) * | 2020-06-02 | 2022-02-15 | 芯天下技术股份有限公司 | Reset circuit of charge amplifier and reset time acquisition method |
| CN112332828A (en) * | 2020-09-15 | 2021-02-05 | 南京芯思科技有限公司 | Charging circuit, analog receiving circuit and charging method based on self-capacitance touch screen |
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