CN101241931B - 半导体结构 - Google Patents
半导体结构 Download PDFInfo
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- CN101241931B CN101241931B CN2007101065643A CN200710106564A CN101241931B CN 101241931 B CN101241931 B CN 101241931B CN 2007101065643 A CN2007101065643 A CN 2007101065643A CN 200710106564 A CN200710106564 A CN 200710106564A CN 101241931 B CN101241931 B CN 101241931B
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- 229910052785 arsenic Inorganic materials 0.000 claims abstract description 66
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims abstract description 62
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 229910052698 phosphorus Inorganic materials 0.000 claims description 13
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Abstract
本发明提供一种半导体结构,包括:衬底;第一栅极介电层,在该半导体衬底上;第一栅极层,在该第一栅极介电层上;第一轻掺杂源极及漏极区域,在该半导体衬底中,并邻接该第一栅极介电层,其中该第一轻掺杂源极及漏极区域包含砷元素;及第一深层源极及漏极区域,在该半导体衬底中,并邻接该第一栅极介电层,其中该第一深层源极及漏极区域包含磷元素,其中在该第一深层源极及漏极区域中的第一磷结深与在该第一深层源极及漏极区域中的第一砷结深的比率大于3。本发明能够防止因注入杂质而产生管线效应,从而避免产生结漏电流。
Description
技术领域
本发明涉及一种半导体装置,且特别涉及一种金属氧化物半元件的结构与制造方法。
背景技术
随着集成电路的微缩化,金属氧化物半导体(metal-oxide-semiconductor,MOS)元件变得愈加微小。因此金属氧化物半导体元件的结深也随之缩小。这种缩减化在形成过程中会造成技术上的困难。举例来说,小的金属氧化物半导体元件需要在源极及漏极区域有高掺杂浓度以减少片电阻(sheetresistance)。然而控制注入深度以形成浅的源极及漏极结,并且同时维持高掺杂浓度是有难度的。
在传统上,为了在源极及漏极区域达到高掺杂浓度,以高浓度注入砷元素进源极及漏极区域。因为砷元素有相当低的扩散长度,故能注入至高浓度而不特别影响到短沟道的特性以及结的陡峭度。然而砷原子的原子量重,约为75。因此比起其他N型杂质,例如磷元素,砷元素的注入会造成更大程度的缺陷,例如管线(piping)。
在小尺寸的金属氧化物半导体元件当中,举例来说,利用65纳米或以下的技术所形成的金属氧化物半导体元件,其结是浅的,故由于注入砷元素所造成的管线会延伸至介于源极及漏极区域与半导体衬底之间的结。因此,当在源极及漏极区域上形成金属硅化层时,可沿着管线形成金属硅化物缺陷,而缩短金属硅化层区域以及半导体衬底的距离。此结果明显使漏电流值增加,甚至使元件失效。
因此需要一种新的金属氧化物半导体元件的结构以及制造方法以解决上述的问题。
发明内容
为达成发明的上述目的,本发明提供一种半导体结构,包括:衬底;第一栅极介电层,在该半导体衬底上;第一栅极层,在该第一栅极介电层上;第一轻掺杂源极及漏极区域,在该半导体衬底中,并邻接该第一栅极介电层,其中该第一轻掺杂源极及漏极区域包含砷元素;及第一深层源极及漏极区域,在该半导体衬底中,并邻接该第一栅极介电层,其中该第一深层源极及漏极区域包含磷元素,其中在该第一深层源极及漏极区域中的第一磷结深与在该第一深层源极及漏极区域中的第一砷结深的比率大于3。
上述该半导体结构中,该第一磷结深对该第一砷结深的比率可介于3至6之间。
上述该半导体结构中,该半导体结构在存储器电路中。
上述该半导体结构中,磷元素最高浓度对砷元素最高浓度的比率可大于5。
上述该半导体结构中,该第一栅极层的长度可小于60纳米。
上述该半导体结构,还可包含:第二栅极介电层,在该半导体衬底上;第二栅极层,在该第二栅极介电层上;第二轻掺杂源极及漏极区域,在该半导体衬底中,并邻接该第二栅极介电层,其中该第二轻掺杂源极及漏极区域包含砷元素;第二深层源极及漏极区域,在该半导体衬底中,并邻接该第二栅极介电层,其中该第二深层源极及漏极区域包含砷元素及磷元素,其中在该第二深层源极及漏极区域中的第二砷结深与第二磷结深为近似的深度。
上述半导体结构中,该第二砷结深对该第二磷结深的比率可大于0.5。
上述半导体结构中,在该第二深层源极及漏极区域的砷最高浓度可小于3×1020/cm3。
为达成发明的另一目的,本发明提供一种半导体结构,包括:衬底;第二栅极介电层,在该半导体衬底上;第二栅极层,在该第二栅极介电层上;第二轻掺杂源极及漏极区域,在该半导体衬底中,并邻接该第二栅极介电层,其中该第二轻掺杂源极及漏极区域包含砷元素;第二深层源极及漏极区域,在该半导体衬底中,并邻接该第二栅极介电层,其中该第二深层源极及漏极区域包含砷元素及磷元素,其中在该第二深层源极及漏极区域中的第二砷结深与第二磷结深为可比较的。
本发明能够防止因注入杂质而产生管线效应(piping effect),从而避免产生结漏电流(junction leakage current)。
附图说明
图1至图6为本发明优选实施例的制程剖面图,其中第一和第二元件区的金属氧化物半元件有不同的掺杂分布。
图7和图8分别为在第一元件区域和第二元件区域的掺杂浓度分布图。
图9显示金属硅化层的形成。
图10显示本发明相关实施例的制程剖面图,其中在第一和第二元件区域的金属氧化物半导体元件有相同的掺杂分布。
其中,附图标记说明如下:
20~衬底;24~浅沟槽隔离区域;26~栅极介电层;28~栅极层;50~P型杂质浓度;52~磷元素浓度;54~砷元素浓度;56~磷元素浓度;58~砷元素浓度;100~存储元件区;130~栅极介电层;131~袋形区域;132~栅极层;134~轻掺杂源极及漏极区域;138~光阻;140~栅电极侧壁层;142~深层源极及漏极区域;144~金属硅化层区域;200~逻辑元件区;230~栅极介电层;231~袋形区域;232~栅极层;234~轻掺杂源极及漏极区域;238~光阻;240~栅电极侧壁层;242~深层源极及漏极区域;244~金属硅化层区域
具体实施方式
有关各实施例的制造和使用方式如以下所详述。然而,值得注意的是,本发明所提供的各种可应用的发明概念依具体的各种变化据以实施,且在此所讨论的具体实施例仅是用来显示具体使用和制造本发明的方法,而不用以限制本发明的范围。
以下通过各附图及示例说明本发明优选实施例的制造过程,其中包含了金属氧化物半导体(metal-oxide-semiconductor,MOS)存储元件以及金属氧化物半导体逻辑元件。此外,在本发明各种不同的各种实施例和图示中,相同的符号代表相同或类似的元件。
图1显示衬底20含有用来形成N型金属氧化物半导体存储元件的存储元件区100,以及含有形成逻辑元件的逻辑元件区200。虽然其他常用的结构和材料如绝缘层上覆硅(silicon on insulator,SOI)或硅合金等也可使用,但在本例中,优选为利用块硅材料作为衬底20,且衬底20也可以是轻掺杂的。为便于说明,依序形成的金属氧化物半导体存储元件显示在浅沟槽隔离(shallow trench isolation,STI)区域24之间。然而,本领域技术人员也可了解,可将上述存储单元串联,因此存储单元间可能不会有浅沟槽隔离。可为静态随机存取存储器(static random access memory,SRAM)区、动态随机存取存储器(dynamic random access memory,DRAM)区,或甚至是非易失性存储器区。逻辑元件区200优选为核心元件区域,因此由后续讨论的步骤所形成的金属氧化物半导体元件为核心金属氧化物半导体元件。
请再参考图1,栅极介电层26是在衬底20上形成的。在此优选实施例中,栅极介电层26具有高介电常数(k值),可高于约3.9。栅极介电层26优选的材料包括氧化硅、氮化硅以及金属氧化物,如二氧化铪(HfO2)、锆酸铪氧化合物(HfZrOx)、硅酸铪氧化合物(HfSiOx)、钛酸铪氧化合物(HfTiOx)及铝酸铪氧化合物(HfAlOx)或类似材料。栅极介电层26的厚度以小于约为佳。
栅极层28形成于栅极介电层26上。在一实施例中,栅极层28由多晶硅材料组成,一般也可使用金属、金属氮化物、金属硅化物或类似化合物作为栅极层28的材料。栅极介电层26以及栅极层28优选的形成方法包括化学气相沉积法(chemical vapor deposition,CVD),如低温化学气相沉积(lowtemperature chemical vapor deposition,LTCVD)、低压化学气相沉积(lowpressure chemical vapor deposition,LPCVD)、快热化学气相沉积(rapid thermalchemical vapor deposition,LTCVD)、等离子体化学气相沉积(plasma enhancedchemical vapor deposition,PECVD),也可使用例如溅镀及物理气相沉积(physical vapor deposition,PVD)等一般相似方法。栅极层28的厚度以小于约为佳。
图2显示栅极堆叠层的形成。栅极介电层26及栅极层28被图案化,以在存储区100形成包含栅极介电层130和栅极层132的栅极堆叠层,且在逻辑区200形成包含栅极介电层230和栅极层232的栅极堆叠层。本发明优选实施例的半导体装置以65纳米(nm)或以下的技术来形成。
图3显示轻掺杂源极及漏极(lightly doped source/drain,LDD)区域134及234的形成,其中轻掺杂源极及漏极区域134及234通常也被称作为源极和漏极的延伸区域(extension region)。用注入法(implantation)将N型杂质导入元件区域100及200。虽然也能够采用含有磷元素的砷元素,但在本例中,优选以砷元素作为N型杂质的材料。由于以栅极层132和232作为掩模,故所形成的轻掺杂源极/漏极区域134及234实质上对准栅极层132和232的边缘。袋形区域(pocket region)131及231是以倾斜角度注入P型杂质例如硼和/或铟元素形成的。虽然或许能使用不同的剂量,但在此优选实施例中,以介于大约5×1012/cm2与大约5×1014/cm2之间的剂量来注入N型杂质。
接着形成栅电极侧壁层(gate spacer)140及240,如图4所示。如同现有技术,栅电极侧壁层140及240可通过毯覆式(blanket)沉积一层或更多层的介电层,并除去介电层的水平部分来形成。沉积介电层优选的方法包括等离子体化学气相沉积、低压化学气相沉积及次真空化学气相沉积法(sub-atmospheric chemical vapor deposition,SACVD),或类似的方法。在一具体实施例中,栅电极侧壁层140及240各自包含氧化物衬垫层及其上的氮化硅层。栅电极侧壁层140及240的最终厚度以小于约45纳米为最佳。
接着,优选以掺杂N型杂质的方式形成深层源极及漏极(deepsource/drain)区域142及242。本发明的第一实施例以图5及图6显示。图5说明深层源极及漏极区域142的形成。形成光阻238以遮蔽元件区域200,并以注入方式将N型杂质注入元件区域100中。在此优选实施例中,所注入的杂质包括不含砷元素的磷元素。在其他实施例中,所注入的杂质同时包含砷元素与磷元素。然而,砷元素的剂量特别小于磷元素的剂量。砷元素剂量优选小于磷元素剂量的约百分之三十,更优选小于磷元素剂量的约百分之二十。被注入的磷元素优选在接近源极及漏极区域142的表面处为高浓度,而在源极及漏极区域142的深层处为低浓度。为完成上述设计,可使用多重注入法。在一具体实施例中,其中一种注入法以介于约1×1015/cm2(即1×E15/cm2)与约6×1015/cm2(即6×E15/cm2)的高剂量,且介于约0.5keV与约10keV的低能量注入。另一种注入法是以介于约5×1013/cm2与约1×1015/cm2的低剂量,且介于约1keV与约30keV的高能量注入。可用垂直或倾斜的角度完成每次磷元素的注入。倾斜角度一般为小于约15度。
图6显示深层源极及漏极区域242的形成。形成光阻138以遮蔽元件区域100,并以注入方式将N型杂质注入元件区域200中。在此优选实施例中,所注入的杂质包含砷元素。而磷元素也有可能会伴随着砷元素被注入,其中磷元素的剂量小于或实质上最多等于砷元素的剂量。在一具体实施例中,砷元素与磷元素均以介于约1×1015/cm2与约5×1015/cm2之间的剂量注入。砷元素的最终最高浓度(peak concentration)以小于约3×1020/cm3为最佳。
图7与图8分别图示说明在深层源极及漏极区域142及242的掺杂浓度分布。图7显示在深层源极及漏极区域142的掺杂浓度和到衬底20内部深度的函数关系,其中在深层源极及漏极区域的掺杂过程仅有磷元素被注入。曲线50、52,及曲线54分别为P型杂质浓度、磷元素浓度,以及砷元素浓度。由于砷元素仅在轻掺杂源极及漏极区域134被掺杂,砷元素与袋形掺杂(pocket implantation)区之间的砷结(arsenic junction)是浅的,其结深(junction depth)D2小于约30纳米。相反地,磷结(phosphorous junction)深度D1特别大于砷结深D2,D1与D2的比率(D1/D2)大于3左右,以介于约3与6之间为更佳。磷元素的最高浓度对砷元素的最高浓度的比值优选为大于5,更优选为大于10。在所有描述当中,砷结以砷元素浓度与P型杂质浓度相同的地方作为定义,磷结以磷元素浓度与P型杂质浓度相同的地方作为定义。
图7中所示杂质分布有许多优点。由于磷元素的原子量约31,特别小于砷元素约为75的原子量,因注入磷元素而对半导体衬底20的晶格结构造成的损坏会远小于注入砷元素时所造成的损害。由此而知,可用磷元素来形成深层源极及漏极区域而不会造成实质的管线效应,从而避免结漏电流的发生。由于砷元素的扩散长度(diffusion length)短,在轻掺杂源极及漏极区域注入磷元素可改进短沟道效应(short channel effect),对于65纳米或以下的技术所形成的金属氧化物半导体元件而言尤其如此。由于存储元件对漏电流特别敏感,故图7所显示的掺杂分布图适合用作存储金属氧化物半导体元件。
图8显示在深层源极及漏极区域242的掺杂浓度与到衬底20内部深度的函数关系,其中砷元素及磷元素以实质相同的剂量进行掺杂以形成源极及漏极区域242。曲线50、56,及曲线58分别代表P型杂质浓度、磷元素浓度,以及砷元素浓度。曲线50与图7中的P型杂质浓度分布相似。由于以相似的剂量在深层源极及漏极区域242注入砷元素与磷元素,砷结深D2’以及磷结深D1’具有较比率D2/D1(参照图7)更大的比率D2’/D1’。若以较低的磷元素剂量注入源极及漏极区域242,比率D2’/D1’可进一步增加。在此优选实施例中,可利用扫描式离子显微镜(scanning ion microscope,SIM)测量掺杂浓度分布,故得结深D1’与D2’为近似的深度。结深比率D2’/D1’以大于约0.5为更佳。
比较图7与图8,很明显地,逻辑金属氧化物半导体元件的砷结厚度D2’特别大于存储金属氧化物半导体元件的砷结厚度D2,其结深比率D2’/D2以大于约2为较佳。在图7所示存储元件的掺杂分布图中,砷结深优选小于约30纳米。在图8所示逻辑元件的掺杂分布图中,砷结深以大于约50纳米为较佳。另外,在逻辑金属氧化物半导体元件中的深层源极及漏极区域242中的砷元素最高浓度(参照图8),以大于在存储金属氧化物半导体元件中的深层源极及漏极区域142的砷元素最高浓度(参照图7)约3倍以上为佳。
对逻辑金属氧化物半导体元件而言,由于有较高的砷元素浓度被注入深层源极及漏极区域242,故逻辑金属氧化物半导体元件的结漏电流值可能会大于存储金属氧化物半导体元件的结漏电流值。然而,逻辑金属氧化物半导体元件的驱动电流(drive current)较高。驱动电流对逻辑金属氧化物半导体元件的关系有益地大于驱动电流对存储金属氧化物半导体元件的关系。
图9显示金属硅化层(silicide)区域144及244的形成。首先沉积金属层(图中未示),其可包含镍(nickel)、钴(cobalt)及铂(platinum)或其组合的材料。接着加热衬底20,造成金属层与其下的硅层发生硅化作用,金属硅化层区域144及244因而形成。接着使用可侵蚀金属层,但不致侵蚀金属硅化层区域144及244的蚀刻剂,以将未反应的金属层除去。
为完成金属氧化物半导体元件的形成,接着形成蚀刻终止层(etch stoplayer,ESL)(图中未示)及层间介电层(inter-layer dielectric,ILD)(图中未示)。由于蚀刻终止层及层间介电层的形成为公知技术,故在此不再重复描述。
图10说明本发明第二实施例,其中存储金属氧化物半导体元件及逻辑金属氧化物半导体元件具有相同的掺杂分布。制造初始阶段及结构实质上与图1到图4所示的内容相同。图10显示深层源极及漏极区域142及242的形成。元件区域100及200均同时暴露在N型杂质注入中,因此存储金属氧化物半导体元件及逻辑金属氧化物半导体元件的最终分布图实质上是相同的。形成深层源极及漏极区域142及242的注入实质上优选与在第一实施例中(参照图5)为形成深层源极及漏极区域142的掺杂相同。在此优选实施例中,所注入的杂质包括不含有砷元素的磷元素。另一替代的实施例中,所注入的杂质同时包含砷元素与磷元素。然而,砷元素剂量远低于磷元素剂量。砷元素剂量优选小于磷元素剂量约百分之三十,更优选小于磷元素剂量约百分之二十。
虽然本发明已用优选实施例揭示如上,然而其并非用以限定本发明,任何本领域技术人员,在不脱离本发明的精神和范围内,当可做改动与修改,因此本发明的保护范围应以所附权利要求范围为准。
Claims (8)
1.一种半导体结构,包括:
衬底;
第一栅极介电层,在该半导体衬底上;
第一栅极层,在该第一栅极介电层上;
第一轻掺杂源极及漏极区域,在该半导体衬底中,并邻接该第一栅极介电层,其中该第一轻掺杂源极及漏极区域包含砷元素;及
第一深层源极及漏极区域,在该半导体衬底中,并邻接该第一栅极介电层,其中该第一深层源极及漏极区域包含磷元素,其中在该第一深层源极及漏极区域中的第一磷结深与在该第一深层源极及漏极区域中的第一砷结深的比率大于3。
2.如权利要求1所述的该半导体结构,其中该第一磷结深对该第一砷结深的比率为介于3至6之间。
3.如权利要求1所述的该半导体结构,其中该半导体结构在存储器电路中。
4.如权利要求1所述的该半导体结构,其中磷元素最高浓度对砷元素最高浓度的比率大于5。
5.如权利要求1所述的该半导体结构,其中该第一栅极层的长度小于60纳米。
6.如权利要求1所述的该半导体结构,还包含:
第二栅极介电层,在该半导体衬底上;
第二栅极层,在该第二栅极介电层上;
第二轻掺杂源极及漏极区域,在该半导体衬底中,并邻接该第二栅极介电层,其中该第二轻掺杂源极及漏极区域包含砷元素;
第二深层源极及漏极区域,在该半导体衬底中,并邻接该第二栅极介电层,其中该第二深层源极及漏极区域包含砷元素及磷元素,其中在该第二深层源极及漏极区域中的第二砷结深与第二磷结深为近似的深度。
7.如权利要求6所述的半导体结构,其中该第二砷结深对该第二磷结深的比率为大于0.5。
8.如权利要求7所述的半导体结构,其中在该第二深层源极及漏极区域的砷最高浓度为小于3×1020/cm3。
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