CN101206162A - System for data acquisition and signal treatment of testing flat wheel - Google Patents
System for data acquisition and signal treatment of testing flat wheel Download PDFInfo
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- CN101206162A CN101206162A CNA2007101448212A CN200710144821A CN101206162A CN 101206162 A CN101206162 A CN 101206162A CN A2007101448212 A CNA2007101448212 A CN A2007101448212A CN 200710144821 A CN200710144821 A CN 200710144821A CN 101206162 A CN101206162 A CN 101206162A
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Abstract
The invention provides a flat wheel detection data acquisition and signal processing system, which consists of seven parts, namely a power module, an AD sampling input front end conditioning module, an AD sampling conversion module, a data program memory module, an interruption management module, a high speed communication module and a reset module. The invention applies a high speed floating point DSP chip, a high speed low consumption double 12-bit parallel A/D converter, a dual-ported RAM chip and a complicated programmable logic device to the flat wheel detection data acquisition and signal processing system, develops a data acquisition and processing system taking the high speed floating point DSP as a core processor, and improves the speed, accuracy and stability of flat wheel detection data acquisition and processing (in addition, the system control, communication and monitoring is handled by ARM-VxWORK, and communication takes a form of network card.), thereby improving the performance index of the whole flat wheel detection system.
Description
(1) technical field
What the present invention relates to is that a kind of flat wheel that is used for the railway system detects data acquisition and signal processing technology.
(2) background technology
It is the important component part of the railway system's flat wheel detection system with signal processing system that flat wheel detects data acquisition, is playing an important role aspect flat stability of taking turns checkout equipment, high efficiency, intelligent, the accuracy.It mainly acts on and is mainly reflected in the following aspects: gather flat analog electrical signal of taking turns the output of detection system front end (1), for flat wheel detection system detection algorithm provides reliable effectively accurate numerical data source.(2) operation for meter, meter axle, detection algorithm realizes providing the hardware carrier of efficient stable.(3) finish and flat real-time Communication for Power and the data transmission that detects control system in the detection system of taking turns.(4) its stability, high efficiency, intelligent, stability, high efficiency, intelligent and accuracy that accuracy has determined the comment detection system.Along with the sustainable development of Chinese national economy, higher requirement is proposed also in transportation by railroad.Along with the perfect success of China railways the sixth time speed-raising, more and more higher requirement is proposed for the stability of the flat wheel of railway detection system, high efficiency, intelligent and accuracy.This also just to flat wheel detect the stability, high efficiency of data acquisition and signal processing system, intelligent, accuracy is had higher requirement.
Recent decades, done unremitting effort for the detection of dynamic that realizes the flat wheel of railway both at home and abroad, studied various detection methods.Yet the realization that does not still have a kind of detection method success so far is to the accurate stabilimeter of flat wheel, meter axle, detection by quantitative.Analyze reason, the success or failure that flat wheel detects data acquisition and signal processing system and method for work are principal elements.The method of work of the flat wheel detection system that has both at home and abroad at present all be by single-chip microcomputer or low speed dsp chip control AD adopt serial communication mode with data acquisition in the peripheral storage of single-chip microcomputer or low speed DSP, serial ports by low speed or PCI or HPI oral instructions are delivered in the PC and then are handled and draw testing result then.Along with improving constantly of transportation by railroad speed, the front end data amount also enlarges markedly, the data acquisition system is proposed higher requirement, and the communication mode of low precision, low velocity and the low speed of single-chip microcomputer, low speed DSP can't satisfy the new demand that the railway system proposes.Study novel flat wheel detection data acquisition and signal processing system and method for work and become the flat important subject of taking turns in the detection system of railway.
(3) summary of the invention
The object of the present invention is to provide a kind of speed, precision and stability that can improve flat wheel detection data acquisition and data processing, thereby the flat wheel that improves the performance index of whole flat wheel detection system detects data acquisition and signal processing system.
The object of the present invention is achieved like this:
It is made up of power module, AD sampling input front end conditioning module, AD sample conversion module, data and program storage block, interrupt management module, high-speed communication module and reseting module seven parts.Power module is supplied with for other six modules provide required numeral or aanalogvoltage; Before AD sample conversion module, add AD sampling input front end conditioning module; AD sample conversion module becomes the digital signal that can handle for DSP with the sample analog signal conversion of input front end conditioning module output of AD, and the digital signal after will being changed by DSP control by data line is stored in the SDRAM in data and the memory module, flash in data and the memory module is connected with the last signal lines of DSP, address wire, control line respectively with the signal wire of SDRAM, address wire, control line, to realize the data transmission of DSP and data and memory module; The interrupt management module mainly links to each other with the external interrupt pin of DSP, realizes the expansion of DSP external interrupt resource is solved the very few defective of external interrupt input pin; The data line of the dual port RAM in the high-speed communication module and address wire respectively with DSP on be connected corresponding of data line with address wire, to realize the data transmission of dsp system and ARM system; The reseting pin of each module of reseting module and other links to each other, for each chip provides reset signal and detects the total system duty in real time.AD sample conversion module, interrupt management module and high-speed communication module control signal corresponding and control register all pass through the VHDL hardware description language to control signal corresponding, address wire and data line realization of decoding on the DSP in CPLD.
Described power module comprises digital power and analog power two large divisions; Digital power is made of input filter network, low pressure drop stabilized voltage supply conversion chip, output filter network, the input of plate external power is as the input of input filter network, the output of input filter network is as the input of low pressure drop stabilized voltage supply conversion chip, the output of low pressure drop stabilized voltage supply conversion chip, be connected to the input end of output filter network, export the output voltage of filter network at last and supply with for the system digits circuit part provides voltage; Analog power is made of input filter network, Voltage stabilizing module, output filter network, the input of plate external power is as the input of input filter network, the output of input filter network is as the input of Voltage stabilizing module, the Voltage stabilizing module output terminal is connected to the input end of output filter network, exports the output voltage of filter network at last and supplies with for the system simulation circuit part provides voltage.
Described AD sampling input front end conditioning module mainly is made up of crystal diode holding circuit and analog computing amplifier circuit; The output that is input as flat wheel detection system front end charge amplifier of crystal diode holding circuit; the output of crystal diode holding circuit is as the input of analog computing amplifier circuit, and the output of analog computing amplifier circuit is as the input of AD sample conversion module.
Described AD sample conversion module mainly is made up of high-speed floating point dsp chip, high-speed parallel ADC chip, decoding scheme and ADC conversion control circuit; High 4 bit address of dsp chip and the address space of DSP are selected the input of signal as decoding scheme, and the output of decoding scheme is connected to the chip selection signal of the chip select pin of ADC chip as ADC; The low 3 bit address lines of dsp chip link to each other successively with the address wire of ADC, and 16 position datawires of DSP link to each other with the data line of ADC and carry out data transmission; The read-write of dsp chip and least-significant byte data line are as the input of ADC conversion control circuit, and the output terminal of ADC conversion control circuit directly links to each other as the input of control signal with the changeover control signal of ADC chip; The enable signal of reading of dsp chip directly links to each other with the enable pin of reading of ADC.
Described data and program storage block are made up of dsp chip TMS320c67xx, Flash chip and SDRAM chip; The data line of DSP links to each other with the data line of SDRAM chip with Flash, and the address wire of dsp chip links to each other with the address wire of Flash and SDRAM, and the reading of the read signal pin of Flash, output enable pin and DSP enables, the output enable pin links to each other; The read-write enable pin of SDRAM directly links to each other with the read-write enable pin of DSP; The different address space base pin selections of DSP select pin to link to each other with the sheet of SDRAM and Flash respectively, as they chip selection signals separately.
Described interrupt management module is made up of dsp chip, code translator, interruption identifier word register and interruption multiplexer; Wherein code translator, interruption identifier word register and interruption multiplexer are realized its function in complex programmable logic device (CPLD) inside by hardware design language VHDL programming; External interrupt directly links to each other with the external interrupt pin of DSP as the external interrupt input of DSP with the input that multiplexer is interrupted in the input of interrupting the identifier word register as interrupting multiplexer; Interrupting the identifier word register root is that every kind of different interruption produces a unique identifier word and is used for DSP and distinguishes each different interruption according to its input signal; The interruption identifier word is transferred to DSP by the least-significant byte data line of DSP; The 1st bit address space base pin selection of DSP and high 4 bit address lines are as the input of code translator, and the output of code translator links to each other as the chip selection signal that interrupts the identifier word register with the sheet choosing of interrupting the identifier word register; The read-write of DSP is connected with the read-write pin that interrupts the identifier word register, and the read-write that the identifier word register is interrupted in control enables.
Described high-speed communication module is made up of DSP, dual port RAM and CPLD control module; The data line of dual port RAM left port, address wire and directly link to each other with DSP and carry out data transmission; The control line of dual port RAM left port directly links to each other with the output of CPLD, and the read-write control of DSP and address space selection wire are as the input of CPLD control module; The address wire of dual port RAM left port, data line and control line address wire, data line and the control line of the detection system of peace wheel detection system respectively are connected.
Described reseting module is made up of the chip that resets that has watchdog function, RC circuit and hello dog pulse producer; Reset signal suitably postpones the reset input of its output of back as the chip that resets as the input RC circuit of RC circuit to reset signal, the output of the chip that resets through on be connected to the reset pin of each chip after drawing; Feeding the dog pulse is produced the CPLD clock division by CPLD inside; As the output of feeding the dog pulse producer, it links to each other with the dog pulse detection port of feeding of the chip that resets; Reset chip the watchdog reset pin through on draw with the NMI pin of DSP and link to each other.
The above-mentioned in addition flat wheel based on DSP detects data Collection ﹠ Processing System and also leaves abundant expansion interface, can expand serial ports, LCD, keyboard, EPROM and timing generator etc., for sufficient preparation has been done in systemic-function upgrading expansion in future.
The main effect of the power module among the present invention provides+5.0V ,+3.3V, the 1.2V digital voltage is supplied with and+5.0V ,-the 5.0V aanalogvoltage supplies with; AD sampling input front end conditioning module mainly contains two effects.The one, the simulating signal that flat wheel detection system front end charge amplifier is transmitted is carried out the amplitude adjustment through the analog computing amplifier circuit to input signal then as input, adjusts in the input range that AD allows.The 2nd, the circuit protection effect.Allow input signal through the crystal diode holding circuit earlier at analog computing amplifier circuit input front end; the voltage strictness is limited in the input allowed band (native system for+5V to-5V); be input to analog computing amplifier then, making the amplifier input voltage surpass its allowed band and damage device because accident is disturbed to prevent.Thereby increase the stability of system, security; The main effect of AD sample conversion control module be according to system requirements according to certain sampling rate with AD sample simulating signal that the input front end conditioning module imports into accurate, real-time transform into the digital signal that DSP can handle; The main effect of data and memory module has: (1) Flash memory stores program code is realized the start self-starting; (2) SDRAM is as the storage space of the digital signal of ADC output; (3) SDRAM provides necessary interim storage space for program run.The main effect of interrupt management module is to realize the expansion of DSP external interrupt resource is solved the very few defective of external interrupt input pin; The main effect of high-speed communication module is to realize that flat wheel detects data acquisition and communicates by letter and exchange visits with the real time high-speed of flat wheel detection system with signal processing system.The main effect of reseting module is: (1) provides reset signal for each chip; (2) whether the watchdog circuit real-time detecting system is working properly, and automatic reset system makes the system recovery operate as normal in the time of abnormal, thereby guaranteed stability, the security of system works.
The method of work that detects data Collection ﹠ Processing System based on the flat wheel of DSP mainly comprises following step:
(1) system power-on reset, the Flash loading procedure of booting, jump to the master routine inlet, in master routine, DSP master controller and peripheral expansion circuit are carried out initialization, carry out System self-test then, system enters the power saving standby mode if system does not have hardware and software failure, waits for outside start look-at-me.If having hardware and software failure, system produces corresponding identifier word according to different faults, deposit in the self-detection result register of dual port RAM, and send look-at-me for the detection system of flat wheel detection system by dual port RAM to allow it come reading system error identification word, make system in the shortest time, recover operate as normal to take the emergency maintenance measure.
(2) be input in the AD sampling input front end conditioning module by the simulating signal of flat wheel detection system front end charge amplifier output step (1) time, be input to AD sample conversion module after the adjustment of simulating signal process amplitude, enter into waiting status, wait for the sample conversion order of DSP.
(3) system enters normal mode of operation from battery saving mode after the external interrupt of DSP detects start magnet steel signal, continues to wait for, the magnet steel signal is opened in wait AD sampling.
(4) the DSP master routine starts the timer internal interruption after the external interrupt of DSP detects the AD sampling to open the magnet steel signal, sets the sample frequency of ADC, and sends the sampling inverted signal for the ADC chip according to sample frequency.And the real-time digital signal with ADC output dumps in the data memory module.
(5) in DSP, realize signal Processing to take turns right form according to the flat wheel detection algorithm numerical data that sampling is exported to ADC.Obtain flat car case number (CN), wheel check mark, left and right sides information and corresponding flat wheel signal waveform of taking turns signal generation place and store in the dual port RAM, and notify the monitoring system of equalling the wheel detection system to come reading of data.Enter waiting status then, come read data, and after providing data and having read the response signal that finishes, DSP proceeds the processing of next group wheel to data up to monitoring system.
Principle of work of the present invention: the simulating signal of flat wheel detection system front end charge amplifier output is input in the AD sampling input front end conditioning module, be input to AD sample conversion module after the adjustment of simulating signal process amplitude, adopt the interruption of work mode to determine accurate sampling rate (20KHz) by DSP then, input signal to AD is sampled, and changes and store in the data memory module.Find the signal and the corresponding speed of a motor vehicle of flat wheel then by the flat wheel of dsp operation detection algorithm.The quantitative relationship of the vibration energy of releasing according to kinetic theory and the flat scar degree of depth draws the accurate size of flat scar then.Draw concrete car case number (CN), wheel check mark and the position, the left and right sides of flat wheel signal correspondence simultaneously according to the magnet steel signalling technique.And by dual port RAM real-time be transferred to detection system the most at last testing result be presented on the PC end man-machine interface.
Superiority of the present invention and technique effect: (1) system core process chip TMS320c67xx adopts high precision, high-speed float-point DSP to replace in the past low speed single-chip microcomputer or low speed dsp chip, highest frequency can reach 200MHz, and arithmetic speed can reach 1600MIPS/s and 1200MFLOPS/s.Improve the speed of data acquisition and detection algorithm, thereby improved precision and efficient that flat wheel detects.(2) adopt two high precision first, multidiameter delay input AD converter, and it is directly expanded on the CE1 space of DSP, the mode of directly visiting its data in the external memory storage mode has replaced employing multi-path serial input AD converter in the past, visits the scheme of its data by the multichannel buffered serial port.Precision and efficient that flat wheel detects have further been improved.(3) characteristic of DSP is combined with the ADC sampling set sampling rate by the timer internal of DSP, produce the commutation pulse signal, compare more accurately with method in the past, flexibly by external hardware circuit clock generator control sampling rate by the software program success.(4) optimize the power module design, adopt special low pressure drop stabilized voltage supply to regulate chip and filter network.This with existing be that the power supply of core design is compared with 1117A, common power conversion chips such as 7805, under complex environment, more can provide stably I/O voltage and core voltage for system.(5) use the interface of dual port RAM chip as communication.When big data quantity, occur the transmission blocking problem when having solved existing system use parallel port, serial ports or HPI communication, unify mutually with the design that system adopts the high-speed floating point processor to carry out high speed algorithm.(6) realize interrupting identifier word register, multichannel interruption multiplexer, decoding scheme, AD switching controller and feed the dog pulse producer with VHDL language in programmable logic device (CPLD) inside, and do not use peripheral components or special chip to realize.Reduce design cost, simplified hardware circuit, improved the dirigibility of design.(7) application of crystal diode holding circuit, AD sampling input front end modulate circuit and watchdog reset circuit has guaranteed the safety and stability of system.(8) circuit board adopts the Anti-interference Design theory.Adopted the 3W principle to come to crosstalk between erasure signal; Adopt the 20H principle to reduce the board edge effect, further guaranteed the stability of circuit working.
(4) description of drawings
What Fig. 1 was involved in the present invention detects the The general frame of data acquisition and signal processing system based on the flat wheel of DSP.
The design concept block diagram of the power module that Fig. 2 is involved in the present invention.
The AD sample conversion Module Design theory diagram that Fig. 3 is involved in the present invention.
The design concept block diagram of the AD sampling input front end conditioning module that Fig. 4 is involved in the present invention.
The interrupt management Module Design theory diagram that Fig. 5 is involved in the present invention.
The high-speed communication Module Design theory diagram that Fig. 6 is involved in the present invention.
The design concept block diagram of data that Fig. 7 is involved in the present invention and program storage block.
The system reset Module Design theory diagram that Fig. 8 is involved in the present invention.
The process flow diagram of the method for work that Fig. 9 is involved in the present invention.
(5) embodiment
For example the present invention is done description in more detail below in conjunction with accompanying drawing:
Flat wheel based on DSP of the present invention detects data acquisition and signal processing system and method for work, and the The general frame of its system as shown in Figure 1.In conjunction with Fig. 1, system is main process chip with high-speed floating point DSP TMS320c67xx, be auxiliary control, process chip with CPLD EPM7xxxS, control cope and drag pattern number converter ADS78xx gathers conversion in real time to 12 road front end simulated datas, and realizes the exchanging visit of native system and monitoring system and the real time high-speed transmission of data with dual port RAM chip id T70Vxx as the interface of the monitoring system of peace wheel detection system.The SDRAM HY57V2816xxHC that TMS320c67xx extends out a slice 8M bit FLASHam291vxxxb and two 16M*8bit is respectively applied for the storage to program and data.System can be divided into power module, AD sampling input front end conditioning module, AD sample conversion module, data and program storage block, interrupt management module, high-speed communication module and reseting module seven parts according to Module Division and form.Being implemented as follows of each several part is described.
The power module of system comprises analog-and digital-two large divisions.Can provide+5.0V ,+3.3V ,+1.2V digital voltage power supply and+5.0V ,-power supply of 5.0V aanalogvoltage.Accompanying drawing 2 is theory diagrams of power module design.In conjunction with Fig. 2, digital power pack mainly constitutes by TPS759xx and two chips of TPS543xx and input, output filter network.They all be TIX specially for the low dropout voltage regulator of chip designs such as DSP, FPGA/CPLD, have the voltage-regulation effect.TPS759xx realization+5.0V digital voltage is to the conversion of+3.3V digital voltage, and transient state is rung fast and should and be had hot turn-off protection and power state detection function, and can open or interrupt its work by software.TPS543xx realization+5.0V digital voltage is to the conversion of+1.2V digital voltage, and transient response is quick, has hot turn-off protection function, but also can its conversion efficiency can be set by the drop-down resistance R that adjusts its RT pin, and relational expression is:
The simulation power pack is directly provided by external power source, by exporting to analog device behind input filter network, Voltage stabilizing module and the output filter network.
Require emphasis a bit be the TMS320c67xx chip require+3.3V and+the 1.2V digital voltage powers simultaneously.If can't guarantee the core voltage power supply earlier of synchronously necessary assurance+1.2V, power behind the I/O voltage of+3.3V.Among the design at+3.3V power voltage supply place bigger electrochemical capacitor in parallel, at+1.2V power voltage supply place less electrochemical capacitor in parallel, the good like this problem that has solved power supply precedence.
Because system will realize 12 road wheel track vibration signals are handled as required.So require AD sample conversion module that 12 acquisition channels will be arranged, sample simultaneously.The ADS78xx that company of Texas Instrument (TI) produces is two 12 A/D converters of quick six passage fully differentials input, it can carry out the sampling of six channel signals simultaneously with the sampling rate of 500kHz, its inner 6 A/D transformation results that fifo register is used to preserve 6 passages help catching faster data.The design extends out two ADS78xx on the outside extending space CE1 of the EMIF of TMS320c67xx, realize AD sample conversion module with the auxiliary control of EMP71xxS.AD sample conversion Module Design theory diagram as shown in Figure 3.Difference decoding output DSP by code translator can the different ADS78xx chip of gating, thereby TMS320c67xx can be as arbitrary ADS78xx of the visit random visit of its external static storer.
The workflow of AD sample conversion module is as follows:
(1) at first TMS320c67xx configures sampling rate (20KHz) by its timer internal, sends the startup conversion command according to this sampling rate control ADCTR then, and this order starts the dedicated tunnel of ADS78xx and finishes conversion work.ADS78xx one has 3 order wires, i.e. HA, HB, HC.They are corresponding A 0, A1 respectively; B0, B1; Three groups of acquisition channels of C0, C1.When becoming when low level 3 groups of acquisition channels by high level, all 3 order wires realize conversion.So because adopted two ADS78xx to have 6 order wires, be used for controlling 6 groups in the native system, totally 12 road acquisition channels carry out analog to digital conversion.
(2) after command signal line is elevated, finish through all passage conversions after a while.Can and read to allow reading of data under the signal controlling this moment by the corresponding ADS78xx of code translator gating.Wherein code translator and ADC control register ADCTR realize with the VHDL language programming in CPLD inside.
The input mode of ADS78xx can adopt the input of single-ended input or difference, requirements+IN end and-scope range of the fluctuation of voltage of IN between holding be ± VREF.Because the signal that flat wheel detection system front end charge amplifier transmits is single-ended bipolar signal.For ADS78xx in the complexity design that reduces circuit has adopted single-ended input mode.Its+input of IN termination signal ,-IN end directly links to each other with the inner 2.5V reference of ADS78xx.The input voltage range that this moment, ADS78xx allowed is 0～5.0V.
Because actual analog input signal does not satisfy this level requirement, so designed AD sampling input front end conditioning module.Its design concept block diagram as shown in Figure 4.Theory according to analogue amplifier in the accompanying drawing 4 has following equation relation to set up:
When so the input voltage range that allows as ADS78xx is 0～5.0V, get R1=2K, R2=10K then the input range of AD sampling input front end conditioning module be-5V～+ 5V.Thereby satisfied system requirements.The crystal diode holding circuit realizes with the BATxxS chip in addition.Guaranteed can not cause damage to system device because the unexpected big amplitude that produces is disturbed.
Detect in data acquisition and the signal processing system based on the flat wheel of DSP and to have 8 exterior interrupt.Wherein have two to be produced by two ADS78xx respectively, notice TMS320c67xx data-switching is finished; There are 4 by outside 4 road magnet steel signals generation (be respectively: start magnet steel, ADC conversion start magnet steel, acquisition zone starting mark magnet steel, acquisition zone end mark magnet steel); 1 is produced by dual port RAM chip id T70Vxx, and notice TMS320c67xx detection system reading finishes; Also have one to be that system reserves the interruption input port, use as the upgrading expansion of system's later stage.And the TMS320c67xx chip has only four available external interrupt input port INT4, INT5, INT6 and INT7.For the drawback of resolution system external interrupt shortage of resources, author designed its principle design block diagram of interrupt management module as shown in Figure 5.After interrupt request is sent in some or several interruptions, there is the interruption multiplexer that interrupt request takes place also will have interrupt request to export to the external interrupt input port of DSP.Simultaneously, produce corresponding interrupt request identifier word in the interrupt request marker register, which kind of external interrupt what be used for representing sending interrupt request is, and has been saved in clear operation always and carries out.In the TMS320c67xx response, have no progeny and at first in the interrupt request marker register, read the interrupt request identifier word, then with the zero clearing of interrupt request marker register, and after carrying out the interrupt function subroutine interrupt request response end of respective interrupt request mark word correspondence, carry out and interrupt returning wait-for-response interrupt request next time.
The high-speed communication module is used for putting down wheel testing result message and corresponding data based on the data Collection ﹠ Processing System of DSP to the monitoring system real time high-speed transmission of flat wheel detection system.This Module Design theory diagram as shown in Figure 6.The core of IDT70Vxx is the dual-port storage array, about two ports can shared this storage array, and have separately control line, when access data separately, identical with common RAM.When reading the data of different storage spaces simultaneously or reading the data in identical data space simultaneously, left and right sides port can carry out simultaneously.At this moment, the BUSY signal of left and right sides port is put height simultaneously.If when same storage space is carried out storage operation simultaneously, the request signal storage of which end occurs earlier, and then the BUSY signal of this end is put height, allows storage.Occur after the storage signal of which end, then this end BUSY signal put low, forbidden storage.It should be noted that the mistiming that two ends, left and right sides access request signal occurs must be greater than 5ns, before not so arbitrated logic can't judge that the access request signal on which limit appears at.If the mistiming that the two ends access request signal occurs is less than the situation of 5ns, arbitrated logic is put height with BUSY signal on one side, the BUSY signal of another side is put low, thereby guarantee that one of two port carry out data storage, data read is carried out in the another port, has avoided conflict.Guaranteed the high-speed real-time transmission of data.
Data and program storage block are made up of data storage cell and program storage unit (PSU).Data storage cell is mainly used in the numerical data of storage ADC output, and the space that necessity is provided for program run.Adopted two HY57V2816xx chips to expand to the CE0 of DSP EMIF respectively in the design and above the CE2, provide the storage space of 16M*8Byte altogether, this space is according to the data volume decision behind the flat wheel signal sampling.Program storage unit (PSU) is mainly used in program code stored.The Flash chip am291vxxxb of sampling 8Mbit in the design.This Module Design theory diagram as shown in Figure 7.
Reseting module design concept block diagram as shown in Figure 8.Mainly form by the chip MAX7xxS that resets, RC circuit, button and hello dog pulse producer.When system's operate as normal, feed to hang down when the dog pulse normally pushes button to calm down a signal input RC circuit and suitably postpone back its and export to the RESET input of the chip that resets, reset chip output through on be connected to the reset pin of each chip after drawing, thereby make each chip reset of system.The chip that resets when system works is undesired can not get normally must feeding the dog pulse, and the chip that resets gets the level reset signal of WDO pin output, because of the watchdog reset pin of the chip that resets through on draw with the NMI pin of DSP and link to each other, restart system so cause DSP to reset.Thereby guaranteed the security of system.
The method of work that detects data Collection ﹠ Processing System based on the flat wheel of DSP mainly comprises following step as shown in Figure 9:
(1) system power-on reset, the am291v8xxb loading procedure of booting, jump to the master routine inlet, in master routine, TMS320C67xx master controller and peripheral expansion circuit are carried out initialization, carry out System self-test then, system enters the power saving standby mode if system does not have hardware and software failure, waits for outside start look-at-me.If having hardware and software failure, system produces corresponding identifier word according to different faults, deposit in the message commands word of preceding 8 bytes of dual port RAM IDT70Vxxx, and send look-at-me for the detection system of flat wheel detection system by dual port RAM to allow it come reading system error identification word, the maintenance measure when taking urgency makes system recover operate as normal in the shortest time.
(2) be input in the AD sampling input front end conditioning module by the simulating signal of flat wheel detection system front end charge amplifier output step (1) time, simulating signal is adjusted to 0～5V through the conditioning amplitude, be input to the input sample port of ADS78xx then, ADS78xx enters into waiting status afterwards, waits for the sample conversion pulse of DSP.
(3) system enters normal mode of operation from battery saving mode after the external interrupt of TMS320C67xx detects start magnet steel signal, continues to wait for, waits for ADS7864 sample conversion unlatching magnet steel signal.
(4) the algorithm master routine starts the interruption of TMS320C67xx timer internal after the external interrupt of TMS320C67xx detects the ADS78xx sample conversion to open the magnet steel signal, set the sample frequency of ADS78xx, and send the sampling inverted signal to ADS78xx according to sample frequency.And the real-time digital signal with ADS78xx output dumps among the HY57V2816xxH of data memory module.
(5) in TMS320C67xx, the data in the data memory module are handled according to flat wheel detection algorithm, the car case number (CN), wheel check mark, left and right sides positional information, flat size of wheel and the corresponding flat wheel signal waveform that obtain flat wheel signal generation place store among the dual port RAM IDT70Vxx, and the flat monitoring system of taking turns detection system of notice is come reading of data.Enter waiting status then, come read data, and after providing data and having read the response signal that finishes, TMS320C67xx proceeds the processing of next group wheel to data up to monitoring system.
Said flat wheel detection algorithm comprises following 8 steps in the said process (5):
(1) the above wheel of 2000Hz shock wave is removed in filtering.
(2) declare the shake point that amplitude is determined possible flat wheel.
(3) method of utilization wavelet decomposition has been asked the time of shake point, judges from the time of shake point which sensor top flat wheel drops on.
(4) relatively whether this sensor is very big in this section amplitude, if greatly it is compensated, otherwise is not flat wheel.
(5) utilization asks the way of this section variance to remove part wheel shock wave, and the absolute value variance of this part wheel shock wave is little.
(6) then the maximum value of the absolute value of utilization judgement signal judges above the quantity of 700 (this program is tentative according to empirical value to be 700, and this value is variable) whether this signal is flat wheel.
(7) if flat wheel utilization method of interpolation is obtained the coefficient that should compensate, this sector data is compensated, ask energy to judge flat wheel size then.
(8) show the particular location that flat wheel occurs (about comprising, car case number (CN), wheel check the number) and size and its corresponding oscillogram at last.
Claims (8)
1. a flat wheel detects data acquisition and signal processing system, it is characterized in that: it is made up of power module, AD sampling input front end conditioning module, AD sample conversion module, data and program storage block, interrupt management module, high-speed communication module and reseting module seven parts; Power module is supplied with for other six modules provide required numeral or aanalogvoltage; Before AD sample conversion module, add AD sampling input front end conditioning module; AD sample conversion module becomes the digital signal that can handle for DSP with the sample analog signal conversion of input front end conditioning module output of AD, and the digital signal after will being changed by DSP control by data line is stored in the SDRAM in data and the memory module, flash in data and the memory module is connected with the last signal lines of DSP, address wire, control line respectively with the signal wire of SDRAM, address wire, control line, to realize the data transmission of DSP and data and memory module; The interrupt management module mainly links to each other with the external interrupt pin of DSP, realizes the expansion of DSP external interrupt resource is solved the very few defective of external interrupt input pin; The data line of the dual port RAM in the high-speed communication module and address wire respectively with DSP on be connected corresponding of data line with address wire, to realize the data transmission of dsp system and ARM system; The reseting pin of each module of reseting module and other links to each other, for each chip provides reset signal and detects the total system duty in real time.AD sample conversion module, interrupt management module and high-speed communication module control signal corresponding and control register all pass through the VHDL hardware description language to control signal corresponding, address wire and data line realization of decoding on the DSP in CPLD.
2. flat wheel according to claim 1 detects data acquisition and signal processing system, and it is characterized in that: described power module comprises digital power and analog power two large divisions; Digital power is made of input filter network, low pressure drop stabilized voltage supply conversion chip, output filter network, the input of plate external power is as the input of input filter network, the output of input filter network is as the input of low pressure drop stabilized voltage supply conversion chip, the output of low pressure drop stabilized voltage supply conversion chip, be connected to the input end of output filter network, export the output voltage of filter network at last and supply with for the system digits circuit part provides voltage; Analog power is made of input filter network, Voltage stabilizing module, output filter network, the input of plate external power is as the input of input filter network, the output of input filter network is as the input of Voltage stabilizing module, the Voltage stabilizing module output terminal is connected to the input end of output filter network, exports the output voltage of filter network at last and supplies with for the system simulation circuit part provides voltage.。
3. flat wheel according to claim 2 detects data acquisition and signal processing system, it is characterized in that: described AD sampling input front end conditioning module mainly is made up of crystal diode holding circuit and analog computing amplifier circuit; The output that is input as flat wheel detection system front end charge amplifier of crystal diode holding circuit; the output of crystal diode holding circuit is as the input of analog computing amplifier circuit, and the output of analog computing amplifier circuit is as the input of AD sample conversion module.
4. flat wheel according to claim 3 detects data acquisition and signal processing system, and it is characterized in that: described AD sample conversion module mainly is made up of high-speed floating point dsp chip, high-speed parallel ADC chip, decoding scheme and ADC conversion control circuit; High 4 bit address of dsp chip and the address space of DSP are selected the input of signal as decoding scheme, and the output of decoding scheme is connected to the chip selection signal of the chip select pin of ADC chip as ADC; The low 3 bit address lines of dsp chip link to each other successively with the address wire of ADC, and 16 position datawires of DSP link to each other with the data line of ADC and carry out data transmission; The read-write of dsp chip and least-significant byte data line are as the input of ADC conversion control circuit, and the output terminal of ADC conversion control circuit directly links to each other as the input of control signal with the changeover control signal of ADC chip; The enable signal of reading of dsp chip directly links to each other with the enable pin of reading of ADC.
5. flat wheel according to claim 4 detects data acquisition and signal processing system, and it is characterized in that: described data and program storage block are made up of dsp chip TMS320c67xx, Flash chip and SDRAM chip; The data line of DSP links to each other with the data line of SDRAM chip with Flash, and the address wire of dsp chip links to each other with the address wire of Flash and SDRAM, and the reading of the read signal pin of Flash, output enable pin and DSP enables, the output enable pin links to each other; The read-write enable pin of SDRAM directly links to each other with the read-write enable pin of DSP; The different address space base pin selections of DSP select pin to link to each other with the sheet of SDRAM and Flash respectively, as they chip selection signals separately.
6. flat wheel according to claim 5 detects data acquisition and signal processing system, it is characterized in that: described interrupt management module is made up of dsp chip, code translator, interruption identifier word register and interruption multiplexer; Wherein code translator, interruption identifier word register and interruption multiplexer are realized its function in complex programmable logic device (CPLD) inside by hardware design language VHDL programming; External interrupt directly links to each other with the external interrupt pin of DSP as the external interrupt input of DSP with the input that multiplexer is interrupted in the input of interrupting the identifier word register as interrupting multiplexer; Interrupting the identifier word register root is that every kind of different interruption produces a unique identifier word and is used for DSP and distinguishes each different interruption according to its input signal; The interruption identifier word is transferred to DSP by the least-significant byte data line of DSP; The 1st bit address space base pin selection of DSP and high 4 bit address lines are as the input of code translator, and the output of code translator links to each other as the chip selection signal that interrupts the identifier word register with the sheet choosing of interrupting the identifier word register; The read-write of DSP is connected with the read-write pin that interrupts the identifier word register, and the read-write that the identifier word register is interrupted in control enables.
7. flat wheel according to claim 6 detects data acquisition and signal processing system, and it is characterized in that: described high-speed communication module is made up of DSP, dual port RAM and CPLD control module; The data line of dual port RAM left port, address wire and directly link to each other with DSP and carry out data transmission; The control line of dual port RAM left port directly links to each other with the output of CPLD, and the read-write control of DSP and address space selection wire are as the input of CPLD control module; The address wire of dual port RAM left port, data line and control line address wire, data line and the control line of the detection system of peace wheel detection system respectively are connected.
8. flat wheel according to claim 7 detects data acquisition and signal processing system, it is characterized in that: described reseting module is made up of the chip that resets that has watchdog function, RC circuit and hello dog pulse producer; Reset signal suitably postpones the reset input of its output of back as the chip that resets as the input RC circuit of RC circuit to reset signal, the output of the chip that resets through on be connected to the reset pin of each chip after drawing; Feeding the dog pulse is produced the CPLD clock division by CPLD inside; As the output of feeding the dog pulse producer, it links to each other with the dog pulse detection port of feeding of the chip that resets; Reset chip the watchdog reset pin through on draw with the NMI pin of DSP and link to each other.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2007101448212A CN101206162B (en) | 2007-12-14 | 2007-12-14 | System for data acquisition and signal treatment of testing flat wheel |
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| CN2007101448212A CN101206162B (en) | 2007-12-14 | 2007-12-14 | System for data acquisition and signal treatment of testing flat wheel |
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| CN101206162B CN101206162B (en) | 2010-11-24 |
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