CN114461142A - Method, system, device and medium for reading and writing Flash data - Google Patents
Method, system, device and medium for reading and writing Flash data Download PDFInfo
- Publication number
- CN114461142A CN114461142A CN202210017456.3A CN202210017456A CN114461142A CN 114461142 A CN114461142 A CN 114461142A CN 202210017456 A CN202210017456 A CN 202210017456A CN 114461142 A CN114461142 A CN 114461142A
- Authority
- CN
- China
- Prior art keywords
- data
- main control
- control chip
- flash memory
- flash
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims description 64
- 230000001360 synchronised effect Effects 0.000 claims abstract description 28
- 238000004590 computer program Methods 0.000 claims description 15
- 230000001960 triggered effect Effects 0.000 claims description 4
- 230000009471 action Effects 0.000 abstract description 14
- 238000012544 monitoring process Methods 0.000 abstract description 8
- 238000012806 monitoring device Methods 0.000 abstract description 7
- 238000004891 communication Methods 0.000 description 13
- 230000008569 process Effects 0.000 description 8
- 238000012545 processing Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 230000005540 biological transmission Effects 0.000 description 4
- 238000007726 management method Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000013473 artificial intelligence Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000013524 data verification Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000010801 machine learning Methods 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 238000009877 rendering Methods 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Read Only Memory (AREA)
Abstract
The CPLD is respectively connected with a main control chip and a Flash memory, receives data sent by the Flash memory and then sends the data to the main control chip, and is used as a monitoring device when the main control chip reads and writes the data in the Flash memory, so as to judge whether the data in the main control chip and the Flash memory are synchronous, if the data in the main control chip and the Flash memory are not synchronous, the CPLD simultaneously sends reset signals to the main control chip and the Flash memory, and the CPLD realizes the monitoring when the main control chip performs read-write action on the Flash memory.
Description
Technical Field
The present application relates to the field of data reading technologies, and in particular, to a method, a system, a device, and a medium for reading and writing Flash data.
Background
Servers are becoming more and more important in the rapidly growing information society as important components of information infrastructure. The design of the server is generally provided with a Flash memory for storing running programs, and when the system is started, the main control chip loads the programs in the Flash memory, so that the configuration of the system and the like are correctly carried out, and the normal running of the server is ensured. In the prior art, a main control chip is directly connected with a Flash memory, when a system is started, the main control chip directly starts to read data in the Flash memory, and after the data is read, the data is loaded into an internal register to configure the register and run a program.
The process that the main control chip reads the data in the Flash memory is uncontrolled, if loading failure occurs in the data loading process, effective positioning analysis cannot be carried out, the Flash memory cannot be reset along with a system in the hardware circuit design of the Flash memory, and the conflict that the address mode of the main control chip is inconsistent with the address mode of the Flash memory after reset exists, so that the data in the Flash memory is damaged and erased.
Therefore, how to enhance the monitoring of the main control chip on the read-write action of the Flash memory is a technical problem to be urgently solved by the person in the art.
Disclosure of Invention
The application aims to provide a method, a system, a device and a medium for reading and writing Flash data.
In order to solve the technical problem, the present application provides a Flash data read-write method, which is applied to a CPLD, wherein the CPLD is respectively connected with a main control chip and a Flash memory, and the method includes:
receiving data sent by the Flash memory;
sending the data to the main control chip and storing the data to a UFM register of the CPLD;
judging whether the data in the main control chip and the Flash memory are synchronous or not;
if not, a reset signal is sent to the main control chip and the Flash memory, and the reset signal is used for controlling the main control chip and the Flash memory to reset simultaneously.
Preferably, in the Flash data read-write method, after the storing the data in the UFM register, the method further includes:
and when the main control chip is restarted or fails to load the data, sending a reset signal to the main control chip and the Flash memory.
Preferably, in the Flash data read-write method, after the storing the data in the UFM register, the method further includes:
and when a signal that the data in the Flash memory and the data in the UFM register are inconsistent, which is sent by the BMC, is received, a reset signal is sent to the main control chip and the Flash memory.
Preferably, in the Flash data read-write method, after the data is sent to the main control chip, the method further includes:
and when the main control chip fails to read the data, storing the current data.
The present application further provides a Flash data read-write system, including:
the main control chip, the CPLD and the Flash memory;
the CPLD includes a UFM register;
the main control chip is connected with the CPLD, the CPLD is connected with the Flash memory,
the CPLD is used for receiving the data sent by the Flash memory, sending the data to the main control chip and storing the data to the UFM register; the CPLD is also used for sending a reset signal to the main control chip and the Flash memory when the data in the main control chip and the Flash memory are asynchronous, and the reset signal is used for controlling the main control chip and the Flash memory to reset simultaneously.
Preferably, the Flash data read-write system further includes: BMC;
the BMC is connected with the CPLD and the Flash memory, and is used for checking whether the data in the Flash memory and the data in the UFM register are consistent or not.
Preferably, in the Flash data read-write system, the main control chip is connected to the CPLD through an SPI bus, the CPLD is connected to the Flash memory through the SPI bus, and the CPLD is connected to the BMC through an IIC bus.
The application also provides a Flash data read-write device, which is applied to a CPLD, wherein the CPLD is respectively connected with a main control chip and a Flash memory, and the device comprises:
the receiving module is used for receiving the data sent by the Flash memory;
the storage module is used for sending the data to the main control chip and storing the data to the UFM register of the CPLD;
the judging module is used for judging whether the data in the main control chip and the Flash memory are synchronous or not; if not, the reset module is triggered.
The reset module is used for sending reset signals to the main control chip and the Flash memory, and the reset signals are used for controlling the main control chip and the Flash memory to reset simultaneously.
And the sending module is used for sending a reset signal to the main control chip and the Flash memory when the main control chip is restarted or fails to load the data.
And the receiving control module is used for sending a reset signal to the main control chip and the Flash memory when receiving a signal which is sent by the BMC and indicates that the data in the Flash memory is inconsistent with the data in the UFM register.
And the error storage module is used for storing the current data when the main control chip fails to read the data.
The present application further provides a Flash data read/write device, including:
a memory for storing a computer program;
and the processor is used for realizing the steps of the Flash data reading and writing method when executing the computer program.
The present application further provides a computer-readable storage medium, on which a computer program is stored, and when being executed by a processor, the computer program implements the steps of the Flash data read-write method as described above.
The method for reading and writing the Flash data is applied to a Complex Programmable Logic Device (CPLD), wherein the CPLD is respectively connected with a main control chip and a Flash memory, and the CPLD receives the data sent by the Flash memory, sends the data to the main control chip and stores the data to a UFM register of the CPLD; the CPLD judges whether the data in the main control chip and the Flash memory are synchronous or not; and if not, sending a reset signal to the main control chip and the Flash memory. The CPLD is used as a monitoring device when the main control chip reads and writes data in the Flash memory, and is used for judging whether the data in the main control chip and the Flash memory are synchronous or not, if the data in the main control chip and the Flash memory are not synchronous, the CPLD simultaneously sends reset signals to the main control chip and the Flash memory, and the CPLD realizes the monitoring when the main control chip performs read-write action on the Flash memory.
In addition, the application also provides a Flash data read-write system, a device and a computer readable storage medium, which correspond to the method and have the same effect.
Drawings
In order to more clearly illustrate the embodiments of the present application, the drawings needed for the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained by those skilled in the art without inventive effort.
Fig. 1 is a flowchart of a Flash data read-write method provided in an embodiment of the present application;
fig. 2 is a structural diagram of a Flash data read-write system provided in an embodiment of the present application;
fig. 3 is a structural diagram of a Flash data read-write device according to an embodiment of the present application;
fig. 4 is a structural diagram of a Flash data read/write device according to another embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without any creative effort belong to the protection scope of the present application.
The core of the application is to provide a method for enhancing monitoring and management of data reading and writing in a Flash memory.
In order that those skilled in the art will better understand the disclosure, the following detailed description will be given with reference to the accompanying drawings.
Fig. 1 is a flowchart of a Flash data read-write method provided in an embodiment of the present application, and is applied to a CPLD22, where the CPLD22 is connected to the main control chip 21 and the Flash memory 24, respectively, and as shown in fig. 1, the Flash data read-write method includes:
s10: receiving data sent by the Flash memory 24;
s11: the UFM register 23 sends data to the main control chip 21 and stores the data to the CPLD 22;
s12: judging whether the data in the main control chip 21 and the Flash memory 24 are synchronous or not;
s13: if not, a reset signal is sent to the main control chip 21 and the Flash memory 24, and the reset signal is used for controlling the main control chip 21 and the Flash memory 24 to reset simultaneously.
The CPLD22 referred to in this embodiment refers to a complex programmable logic device, which is composed of a fully programmable and/or array and a macro cell library. The AND/OR array is reprogrammable AND capable of performing numerous logic functions. Macro cells are functional blocks that perform combinational or sequential logic, while providing more flexibility in outputting true or complement values and feeding back in different paths. In addition, the CPLD22 includes a User Flash Memory (UFM), and the data stored in the UFM register 23 still exists after the CPLD22 is powered off, and cannot be emptied.
The Flash memory 24 is also called a Flash memory, not only has an electrically erasable and programmable performance, but also does not lose data due to power failure, can quickly read data, and is used for storing a BIOS program, a BMC25 program and the like on a server. The main control chip 21 of the server reads the data stored in the Flash memory 24, and after the data is read, the data is loaded into an internal register, the register is configured, and a program is run. In the process of reading data by the main control chip 21, if the main control chip 21 fails to read the data or the main control chip 21 suddenly fails to power down, the main control chip 21 is powered on again, but the Flash memory 24 cannot be reset along with the main control chip 21, so that data is not synchronized between the main control chip 21 and the Flash memory 24.
The CPLD22 mentioned in step S10 receives the data sent by the Flash memory 24, and step S11 sends the data to the main control chip 21, so that the main control chip 21 can read and load the data, in this process, the CPLD22 is only used as an intermediary in the process of reading the data of the Flash memory 24 by one main control chip 21, and the CPLD22 is serially connected to a connection line between the main control chip 21 and the Flash memory 24. In addition, in step S11, the CPLD22 stores data in the UFM register 23 of the CPLD22, or it can be regarded that when the main control chip 21 reads data in the Flash memory 24, the CPLD22 reads data on the communication bus between the main control chip 21 and the Flash memory 24, and stores the data in the UFM register 23. In addition, the data is stored in the UFM register 23, and when the master control chip 21 fails to read the data, the reason for the loading failure of the master control chip 21 can be analyzed by loading the data stored in the CPLD22, so as to solve the error.
Step S12 is to determine whether the data in the main control chip 21 and the Flash memory 24 are synchronous, including determining whether the clock status and the address status of the data in the main control chip 21 and the Flash memory 24 are synchronous, and if the data in the main control chip 21 and the Flash memory 24 are asynchronous, the memory stored in the Flash memory 24 may be damaged because the main control chip 21 and the Flash memory 24 operate in different address modes. Whether the data in the main control chip 21 and the Flash memory 24 are synchronous or not is judged through the step S12, if the data are asynchronous, the step S13 sends a reset signal to the main control chip 21 and the Flash memory 24, the reset signal is used for controlling the main control chip 21 and the Flash memory 24 to reset simultaneously, and the main control chip 21 and the Flash memory 24 reset simultaneously, so that the main control chip 21 and the Flash memory 24 are ensured to work in the same address mode, and the problem that the content of the Flash memory 24 is damaged is avoided.
In addition, the embodiment does not limit the connection mode between the main control chip 21 and the CPLD22, and also does not limit the connection mode between the CPLD22 and the Flash memory 24, and the embodiment is designed according to actual needs; in addition, the present embodiment also does not limit the specific types of the main control chip 21, such as CPU, MCU, PCH, MCH, etc.
By the method provided by the embodiment, the CPLD22 is connected in series between the main control chip 21 and the Flash memory, and the CPLD22 receives the data sent by the Flash memory 24, sends the data to the main control chip 21, and stores the data in the UFM register 23 of the CPLD 22; the CPLD22 judges whether the data in the main control chip 21 and the Flash memory 24 are synchronous or not; if not, a reset signal is sent to the main control chip 21 and the Flash memory 24. The CPLD22 is used as a monitoring device when the main control chip 21 reads and writes data in the Flash memory 24, to determine whether the data in the main control chip 21 and the Flash memory 24 are synchronous, and if the data in the main control chip 21 and the Flash memory 24 are not synchronous, the CPLD22 sends a reset signal to the main control chip 21 and the Flash memory 24 at the same time, so as to ensure the data synchronization in the main control chip 21 and the Flash memory 24, and the CPLD22 monitors the read and write actions of the main control chip 21 on the Flash memory 24.
According to the above embodiment, when the main control chip 21 is restarted due to power failure or other reasons, it is likely that the data in the main control chip 21 and the data in the Flash memory 24 are not synchronized, so this embodiment provides a preferable scheme, and after the step S11 stores the data in the UFM register 23, the method further includes: when the main control chip 21 is restarted or fails to load data, a reset signal is sent to the main control chip 21 and the Flash memory 24.
When the CPLD22 detects that the main control chip 21 is restarted in a power-down mode or fails to load data, the CPLD22 directly sends reset signals to the main control chip 21 and the Flash memory 24, the reset signals are used for controlling the main control chip 21 and the Flash memory 24 to reset simultaneously, and the main control chip 21 and the Flash memory 24 perform reset actions simultaneously, so that the main control chip 21 and the Flash memory 24 are ensured to work in the same address mode, and the problem that the content of the Flash memory 24 is damaged is avoided.
By the method provided by the embodiment, when the main control chip 21 is restarted or data loading fails, the reset signals are sent to the main control chip 21 and the Flash memory 24, and the CPLD22 sends the reset signals to the main control chip 21 and the Flash memory 24 at the same time, so that data synchronization in the main control chip 21 and the Flash memory 24 is ensured, and the CPLD22 monitors the read-write action of the main control chip 21 on the Flash memory 24.
According to the above embodiment, in order to ensure that the CPLD22 reads the data in the Flash memory 24 accurately, this embodiment provides a preferable solution, after the step S11 stores the data in the UFM register 23, the method further includes: when receiving a signal that data in the Flash memory 24 and the UFM register 23 are inconsistent, the signal being sent by a Baseboard Management Controller (BMC 25), a reset signal is sent to the main control chip 21 and the Flash memory 24.
The baseboard management controller BMC25 mentioned in this embodiment is connected to the CPLD22 and the Flash memory 24, and is configured to monitor whether data information stored in the CPLD22 is consistent with data in the Flash memory 24, and check accuracy of the data, and a worker may analyze a problem in data communication between the main control chip 21 and the Flash memory 24 by reading a check result of the BMC 25. When the BMC25 detects that the data stored in the UFM register 23 of the CPLD22 is inconsistent with the data in the Flash memory 24, the BMC25 sends a signal to the CPLD22, and the CPLD22 sends a reset signal to the main control chip 21 and the Flash memory 24, so that the data synchronization in the main control chip 21 and the Flash memory 24 is ensured, and the CPLD22 monitors the read-write action of the main control chip 21 on the Flash memory 24.
By the method provided by the embodiment, the BMC25 participates in the verification of data reading and writing, the safety and reliability of data are improved, and the overall reliability of the system is further improved.
According to the above embodiment, when the main control chip 21 reads the data in the Flash memory 24, there is a possibility of a read failure, and in order to analyze the reason why the main control chip 21 fails to read the data, so as to solve the problem, this embodiment provides a preferable solution, and after the step S11 sends the data to the main control chip 21, the method further includes:
when the main control chip 21 fails to read the data, the current data is stored.
When the master control chip 21 fails to read data, the master control chip 21 may lose the data, the CPLD22 is provided to store the data, and a worker may analyze the reason of the failure to read by checking the type of the data, so as to solve the problem.
An embodiment of the present application further provides a Flash data read-write system, and fig. 2 is a structural diagram of the Flash data read-write system provided in the embodiment of the present application, and as shown in fig. 2, the Flash data read-write system includes:
the main control chip 21, the CPLD22 and the Flash memory 24;
CPLD22 includes UFM register 23;
the main control chip 21 is connected with the CPLD22, the CPLD22 is connected with the Flash memory 24,
the CPLD22 is used for receiving data sent by the Flash memory 24, sending the data to the main control chip 21 and storing the data to the UFM register 23; the CPLD22 is further configured to send a reset signal to the main control chip 21 and the Flash memory 24 when the main control chip 21 and the Flash memory 24 are out of synchronization with each other, where the reset signal is used to control the main control chip 21 and the Flash memory 24 to reset simultaneously.
The CPLD22 stores data in the UFM register 23 of the CPLD22, which can also be regarded as that when the main control chip 21 reads data in the Flash memory 24, the CPLD22 reads data on the communication bus between the main control chip 21 and the Flash memory 24, and stores the data in the UFM register 23. In addition, the data is stored in the UFM register 23, and when the master control chip 21 fails to read the data, the reason for the loading failure of the master control chip 21 can be analyzed by loading the data stored in the CPLD22, so as to solve the error.
When the data in the main control chip 21 and the data in the Flash memory 24 are asynchronous, the CPLD22 sends a reset signal to the main control chip 21 and the Flash memory 24, the reset signal is used to control the main control chip 21 and the Flash memory 24 to reset simultaneously, and the main control chip 21 and the Flash memory 24 reset simultaneously, so that the main control chip 21 and the Flash memory 24 are ensured to work in the same address mode, and the problem that the content of the Flash memory 24 is damaged is avoided.
Through the Flash data read-write system provided by the embodiment, the CPLD22 is connected in series between the main control chip 21 and the Flash memory, and the CPLD22 receives the data sent by the Flash memory 24, sends the data to the main control chip 21, and stores the data in the UFM register 23 of the CPLD 22; the CPLD22 sends a reset signal to the main control chip 21 and the Flash memory 24 when the main control chip 21 and the Flash memory 24 have asynchronous data, the reset signal is used for controlling the main control chip 21 and the Flash memory 24 to reset simultaneously, the CPLD22 is used as a monitoring device when the main control chip 21 reads and writes data in the Flash memory 24, the data synchronization in the main control chip 21 and the Flash memory 24 is ensured, and the CPLD22 realizes the monitoring when the main control chip 21 reads and writes data in the Flash memory 24.
According to the foregoing embodiment, the present application further provides a preferable scheme, where the Flash data read-write system further includes: BMC 25;
the BMC25 is connected with the CPLD22 and the Flash memory 24, and the BMC25 is used for checking whether the data in the Flash memory 24 and the UFM register 23 are consistent.
The baseboard management controller BMC25 is connected with the CPLD22 and the Flash memory 24, and is used for monitoring whether data information stored in the CPLD22 is consistent with data in the Flash memory 24 or not, checking accuracy of the data, and enabling a worker to analyze problems of data communication between the main control chip 21 and the Flash memory 24 by reading a checking result of the BMC 25. When the BMC25 detects that the data stored in the UFM register 23 of the CPLD22 is inconsistent with the data in the Flash memory 24, the BMC25 sends a signal to the CPLD22, and the CPLD22 sends a reset signal to the main control chip 21 and the Flash memory 24, so that the data synchronization in the main control chip 21 and the Flash memory 24 is ensured, and the CPLD22 monitors the read-write action of the main control chip 21 on the Flash memory 24.
According to the above embodiments, the present application also provides a preferred scheme, which is a Flash data read-write system, where the main control chip 21 and the CPLD22 are connected by a Serial Peripheral Interface (SPI) bus, the CPLD22 and the Flash memory 24 are connected by the SPI bus, and the CPLD22 and the BMC25 are connected by an Inter-Integrated Circuit (IIC) bus.
It should be noted that the SPI bus is a high-speed, full-duplex, synchronous communication bus, supports full-duplex communication, and is simple in communication and data transmission rate. The IIC bus is mainly used to connect the whole circuit, and the IIC is a multi-directional control bus, that is, a plurality of chips can be connected to the same bus structure, and each chip can be used as a control source for real-time data transmission. This approach simplifies the signaling bus interface.
The communication connection between the CPLD22 and the main control chip 21 and the Flash memory 24 is realized through the SPI bus, the communication is simple, and the data transmission rate is high; the communication connection between the CPLD22 and the BMC25 is realized through the IIC bus, and the CPLD bus communication device is simple in structure, low in power consumption, strong in anti-interference and long in transmission distance.
In the above embodiments, the Flash data read-write method is described in detail, and the present application also provides an embodiment corresponding to the Flash data read-write apparatus. It should be noted that the present application describes the embodiments of the apparatus portion from two perspectives, one from the perspective of the function module and the other from the perspective of the hardware.
Fig. 3 is a structural diagram of a Flash data read-write device according to an embodiment of the present application, and as shown in fig. 3, the Flash data read-write device includes:
the receiving module 31 is used for receiving data sent by the Flash memory 24;
the storage module 32 is used for sending data to the main control chip 21 and storing the data to the UFM register 23 of the CPLD 22;
the judging module 33 is used for judging whether the data in the main control chip 21 and the Flash memory 24 are synchronous or not; if not, the reset module 34 is triggered.
And the reset module 34 is configured to send a reset signal to the main control chip 21 and the Flash memory 24, where the reset signal is used to control the main control chip 21 and the Flash memory 24 to reset simultaneously.
The Flash data read-write device is applied to a CPLD22, a CPLD22 is respectively connected with a main control chip 21 and a Flash memory 24, a receiving module 31 receives data sent by the Flash memory 24, a storage module 32 sends the data to the main control chip 21 and stores the data to a UFM register 23 of the CPLD22, and a judging module 33 judges whether the data in the main control chip 21 and the Flash memory 24 are synchronous or not; if not, the reset module 34 is triggered to send a reset signal to the main control chip 21 and the Flash memory 24, and the reset signal is used for controlling the main control chip 21 and the Flash memory 24 to reset simultaneously.
The CPLD22 is serially connected between the main control chip 21 and the Flash memory, and is used as a monitoring device when the main control chip 21 reads and writes data in the Flash memory 24, and judges whether the data in the main control chip 21 and the Flash memory 24 are synchronous, if the data in the main control chip 21 and the Flash memory 24 are not synchronous, the CPLD22 sends a reset signal to the main control chip 21 and the Flash memory 24 at the same time, so that the data in the main control chip 21 and the Flash memory 24 are ensured to be synchronous, and the CPLD22 realizes the monitoring when the main control chip 21 performs read and write actions on the Flash memory 24.
The device also includes:
and the sending module is used for sending a reset signal to the main control chip and the Flash memory when the main control chip is restarted or fails to load data.
And the receiving control module is used for sending a reset signal to the main control chip and the Flash memory when receiving a signal that the data in the Flash memory and the UFM register sent by the BMC are inconsistent.
And the error storage module is used for storing the current data when the main control chip fails to read the data.
Since the embodiments of the apparatus portion and the method portion correspond to each other, please refer to the description of the embodiments of the method portion for the embodiments of the apparatus portion, which is not repeated here.
Fig. 4 is a structural diagram of a Flash data read/write device according to another embodiment of the present application, and as shown in fig. 4, the Flash data read/write device includes: a memory 40 for storing a computer program;
and the processor 41 is used for implementing the steps of the Flash data reading and writing method of the embodiment when executing the computer program.
The Flash data read-write device provided by this embodiment may include, but is not limited to, a smart phone, a tablet computer, a notebook computer, or a desktop computer.
Processor 41 may include one or more processing cores, such as a 4-core processor, an 8-core processor, and so forth. The processor 41 may be implemented in at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor 41 may also include a main processor and a coprocessor, where the main processor is a processor for Processing data in an awake state, and is also called a Central Processing Unit (CPU); a coprocessor is a low power processor for processing data in a standby state. In some embodiments, the processor 41 may be integrated with a Graphics Processing Unit (GPU) which is responsible for rendering and drawing the content required to be displayed on the display screen. In some embodiments, processor 41 may also include an Artificial Intelligence (AI) processor for processing computational operations related to machine learning.
Memory 40 may include one or more computer-readable storage media, which may be non-transitory. Memory 40 may also include high speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In this embodiment, the memory 40 is at least used for storing the following computer program 401, wherein after the computer program is loaded and executed by the processor 41, the relevant steps of the Flash data read-write method disclosed in any of the foregoing embodiments can be implemented. In addition, the resources stored in the memory 40 may also include an operating system 402, data 403, and the like, and the storage manner may be a transient storage or a permanent storage. Operating system 402 may include, among other things, Windows, Unix, Linux, and the like. Data 403 may include, but is not limited to, the steps involved in implementing Flash data read-write methods, and the like.
In some embodiments, the Flash data read/write device may further include a display 42, an input/output interface 43, a communication interface 44, a power supply 45, and a communication bus 46.
Those skilled in the art will appreciate that the architecture shown in FIG. 4 does not constitute a limitation of the Flash data read/write device and may include more or fewer components than those shown.
The Flash data read-write device provided by the embodiment of the application comprises a memory and a processor, and when the processor executes a program stored in the memory, the following method can be realized: a Flash data read-write method, the CPLD22 is used as a monitoring device when the main control chip 21 reads and writes data in the Flash memory 24, judges whether the data in the main control chip 21 and the Flash memory 24 are synchronous, if the data in the main control chip 21 and the Flash memory 24 are asynchronous, the CPLD22 sends reset signals to the main control chip 21 and the Flash memory 24 simultaneously, thus ensuring the data synchronization in the main control chip 21 and the Flash memory 24, and the CPLD22 realizes the monitoring when the main control chip 21 performs read-write action on the Flash memory 24.
Finally, the application also provides a corresponding embodiment of the computer readable storage medium. The computer readable storage medium has a computer program stored thereon, and the computer program, when executed by the processor, implements the steps described in the above Flash data read/write method embodiment.
It is to be understood that if the method in the above embodiments is implemented in the form of software functional units and sold or used as a stand-alone product, it can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application may be embodied in the form of a software product, which is stored in a storage medium and executes all or part of the steps of the methods described in the embodiments of the present application, or all or part of the technical solutions. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
The present embodiment provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the method of: the method for reading and writing the Flash data comprises the steps that the CPLD22 is used as a monitoring device when the main control chip 21 reads and writes the data in the Flash memory 24, whether the data in the main control chip 21 and the data in the Flash memory 24 are synchronous or not is judged, if the data in the main control chip 21 and the data in the Flash memory 24 are not synchronous, the CPLD22 sends reset signals to the main control chip 21 and the Flash memory 24 at the same time, so that the data in the main control chip 21 and the data in the Flash memory 24 are synchronous, and the CPLD22 monitors the read and write actions of the main control chip 21 on the Flash memory 24.
The Flash data read-write method, the Flash data read-write system, the Flash data read-write device and the Flash data read-write medium provided by the application are introduced in detail above. The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description. It should be noted that, for those skilled in the art, it is possible to make several improvements and modifications to the present application without departing from the principle of the present application, and such improvements and modifications also fall within the scope of the claims of the present application.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Claims (10)
1. A Flash data read-write method is characterized in that the method is applied to a CPLD, the CPLD is respectively connected with a main control chip and a Flash memory, and the method comprises the following steps:
receiving data sent by the Flash memory;
sending the data to the main control chip and storing the data to a UFM register of the CPLD;
judging whether the data in the main control chip and the Flash memory are synchronous or not;
if not, a reset signal is sent to the main control chip and the Flash memory, and the reset signal is used for controlling the main control chip and the Flash memory to reset simultaneously.
2. The Flash data read-write method according to claim 1, wherein after storing the data in the UFM register, the method further comprises:
and when the main control chip is restarted or fails to load the data, sending a reset signal to the main control chip and the Flash memory.
3. The Flash data read-write method according to claim 1, wherein after storing the data in the UFM register, the method further comprises:
and when a signal that the data in the Flash memory and the data in the UFM register are inconsistent, which is sent by the BMC, is received, a reset signal is sent to the main control chip and the Flash memory.
4. The Flash data read-write method according to claim 1, wherein after the data is sent to the main control chip, the method further comprises:
and when the main control chip fails to read the data, storing the current data.
5. A Flash data read-write system is characterized by comprising:
the main control chip, the CPLD and the Flash memory;
the CPLD includes a UFM register;
the main control chip is connected with the CPLD, the CPLD is connected with the Flash memory,
the CPLD is used for receiving the data sent by the Flash memory, sending the data to the main control chip and storing the data to the UFM register; the CPLD is also used for sending a reset signal to the main control chip and the Flash memory when the data in the main control chip and the Flash memory are asynchronous, and the reset signal is used for controlling the main control chip and the Flash memory to reset simultaneously.
6. The Flash data read-write system according to claim 5, further comprising: BMC;
the BMC is connected with the CPLD and the Flash memory, and is used for checking whether the data in the Flash memory and the data in the UFM register are consistent or not.
7. The Flash data read-write system according to claim 6, wherein the main control chip is connected to the CPLD through an SPI bus, the CPLD is connected to the Flash memory through the SPI bus, and the CPLD is connected to the BMC through an IIC bus.
8. A Flash data read-write device is characterized in that the device is applied to a CPLD, the CPLD is respectively connected with a main control chip and a Flash memory, and the device comprises:
the receiving module is used for receiving the data sent by the Flash memory;
the storage module is used for sending the data to the main control chip and storing the data to the UFM register of the CPLD;
the judging module is used for judging whether the data in the main control chip and the Flash memory are synchronous or not; if not, the reset module is triggered.
The reset module is used for sending reset signals to the main control chip and the Flash memory, and the reset signals are used for controlling the main control chip and the Flash memory to reset simultaneously.
9. A Flash data read-write device is characterized by comprising:
a memory for storing a computer program;
processor for implementing the steps of the Flash data read-write method according to any one of claims 1 to 4 when executing the computer program.
10. A computer-readable storage medium, characterized in that a computer program is stored on the computer-readable storage medium, which computer program, when being executed by a processor, carries out the steps of the Flash data read-write method according to any one of claims 1 to 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210017456.3A CN114461142B (en) | 2022-01-07 | 2022-01-07 | Method, system, device and medium for reading and writing Flash data |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210017456.3A CN114461142B (en) | 2022-01-07 | 2022-01-07 | Method, system, device and medium for reading and writing Flash data |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114461142A true CN114461142A (en) | 2022-05-10 |
| CN114461142B CN114461142B (en) | 2023-08-08 |
Family
ID=81410371
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210017456.3A Active CN114461142B (en) | 2022-01-07 | 2022-01-07 | Method, system, device and medium for reading and writing Flash data |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114461142B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115061532A (en) * | 2022-06-10 | 2022-09-16 | 北京主导时代科技有限公司 | Triggering reset device of safe touch edge |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101206162A (en) * | 2007-12-14 | 2008-06-25 | 哈尔滨工程大学 | System for data acquisition and signal treatment of testing flat wheel |
| CN202424658U (en) * | 2011-12-28 | 2012-09-05 | 天津市亚安科技股份有限公司 | Synchronous resetting circuit for master control chip and video camera |
| CN110187923A (en) * | 2019-05-10 | 2019-08-30 | 杭州迪普科技股份有限公司 | A kind of CPU starting method and apparatus applied to multi -CPU board |
-
2022
- 2022-01-07 CN CN202210017456.3A patent/CN114461142B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101206162A (en) * | 2007-12-14 | 2008-06-25 | 哈尔滨工程大学 | System for data acquisition and signal treatment of testing flat wheel |
| CN202424658U (en) * | 2011-12-28 | 2012-09-05 | 天津市亚安科技股份有限公司 | Synchronous resetting circuit for master control chip and video camera |
| CN110187923A (en) * | 2019-05-10 | 2019-08-30 | 杭州迪普科技股份有限公司 | A kind of CPU starting method and apparatus applied to multi -CPU board |
Non-Patent Citations (2)
| Title |
|---|
| 张成;邓勇;: "基于CPLD的嵌入式系统复位电路设计", 电子技术, no. 02 * |
| 方彬浩;: "嵌入式Nor Flash数据安全存储系统设计", 计算机产品与流通, no. 02 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115061532A (en) * | 2022-06-10 | 2022-09-16 | 北京主导时代科技有限公司 | Triggering reset device of safe touch edge |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114461142B (en) | 2023-08-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20230393841A1 (en) | Pcie switch working mode updating method and related assembly | |
| CN112506745B (en) | Memory temperature reading method and device and computer readable storage medium | |
| CN114461142B (en) | Method, system, device and medium for reading and writing Flash data | |
| CN110569154B (en) | Chip interface function testing method, system, terminal and storage medium | |
| CN108121842B (en) | Method and device for verifying low-power-consumption working mode of multiprocessor system chip | |
| CN113672306B (en) | Server component self-checking abnormity recovery method, device, system and medium | |
| CN113641537A (en) | Starting system, method and medium for server | |
| CN111124780B (en) | UPI Link speed reduction test method, system, terminal and storage medium | |
| CN114996069A (en) | Mainboard test method, device and medium | |
| CN114461286B (en) | Server starting method and device, electronic equipment and readable storage medium | |
| CN112463508B (en) | Server dormancy state testing method, system, terminal and storage medium | |
| CN115904787A (en) | Method, device and medium for determining reason of lost disk | |
| CN115766410A (en) | Method, system, device and medium for switching working states of machine | |
| CN114189429A (en) | System, method, device and medium for monitoring server cluster faults | |
| CN115905072A (en) | Computer system, control method based on PCIe device and related device | |
| CN115454906A (en) | Data communication system, method, device and readable storage medium | |
| CN114153388B (en) | Hard disk system, hard disk configuration information refreshing method, device and medium | |
| CN213182723U (en) | Server system for improving supervision safety | |
| TWI823556B (en) | Memory abnormality detection system, motherboard, electronic device and abnormality detection method | |
| TWI794997B (en) | Method and apparatus and computer program product for debugging solid state disk devices | |
| CN114153303A (en) | Power consumption control system, power consumption control method, power consumption control device and power consumption control medium | |
| US20230161598A1 (en) | System booting method and related computer system | |
| CN114116306A (en) | Data backup method, system, terminal and storage medium under power failure of disk array | |
| CN115858433A (en) | Method, system, device, equipment and storage medium for controlling retimer mode | |
| CN115101112A (en) | Method and device for parameterizable configuration of NAND aging test, computer equipment and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |