CN100517341C - Design method of electric energy quality monitoring application-specific integrated circuits based on soft nucleus CPU technology - Google Patents
Design method of electric energy quality monitoring application-specific integrated circuits based on soft nucleus CPU technology Download PDFInfo
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- CN100517341C CN100517341C CNB2007100190114A CN200710019011A CN100517341C CN 100517341 C CN100517341 C CN 100517341C CN B2007100190114 A CNB2007100190114 A CN B2007100190114A CN 200710019011 A CN200710019011 A CN 200710019011A CN 100517341 C CN100517341 C CN 100517341C
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Abstract
The invention discloses a design method of application specific integrated circuit (ASIC) for power supply quality monitoring based on the soft core CPU technology, wherein, the integrated circuit which is designed through the method completes the main function of power supply quality monitoring through the collaborative work of each functional module; the functional modules are respectively mapped to the hardware resource and the software resource of the ASIC; the ASIC is divided into a user logic area and an in-line CPU soft core; the user logic area which completes functions such as data acquisition and data processing, etc. realizes power supply quality monitoring mainly through a VHDL compile functional module; an in-line soft core CPU-NiosII processor completes complex man-machine interaction function and communication function. The invention which passes the platform verification based on a programmable gate array testifies the correctness and the reasonableness of the whole ASIC used in power supply quality monitoring.
Description
Technical field
The invention belongs to the special IC method for designing of electric energy quality monitoring technical field, particularly a kind of method for designing of the electric energy quality monitoring application-specific integrated circuits based on soft nucleus CPU technology.
Background technology
Along with the continuous increase of all kinds of nonlinear-loads in power system development and the electrical network, the monitoring of the quality of power supply, management and control more and more are subjected to each side and pay close attention to.Electric energy quality monitor is important tool and the means that realize electric energy quality monitoring and management.
Present equipment for monitoring power quality on the market, although form is different, the mode that realizes all is that to adopt with the microprocessor be the circuit of core, and each index of the quality of power supply is sampled and calculated, and reaches the purpose to electric energy quality monitoring.Up to the present, the core of hardware circuit all is a microprocessor, and the precision of monitoring depends on the height of microprocessor performance.
But microprocessor also has some intrinsic deficiencies in performance control advantage, directly influenced the precision of electric energy quality monitoring and the stability of monitor.Subject matter is divided into two classes:
One class is pure technical matters, and as the selection of software design flow process, interface device or the rationality problem of interference protection measure application etc., these problems belong to the row that can solve usually.
Another kind of then directly relevant with microprocessor itself, belong to unsurmountable shortcoming.These shortcoming and defect are mainly reflected in the following aspects:
1) resource utilization is low.Because the index of electric energy quality monitoring is more, and real-time required can run into the inadequate resource that has usually on the microprocessor type selecting than higher, and the situation of the resource redundancy that has.Because input/output signal has diversity, the general purpose I/O that adopts microprocessor to provide handles, and needs to increase a lot of peripheral circuits and cooperates, and has increased the use of discrete component, has increased the area of hardware circuit, and system reliability can reduce;
2) instruction execution efficient is low.What the microprocessor that electric energy quality monitor adopts all adopted is the serial command executive mode, thereby the raising of its operating rate and efficient also is subject to this working method, its speed can not satisfy the requirement that the big data quantity algorithm is handled data, and in order to reach high processing speed, usually need a plurality of processor co-ordinations, increased the complexity of circuit on the one hand, influenced reliability, on the other hand, the coordination of multiprocessor and work allocation and corresponding software development are also complicated, and the space of further improving processing power is limited;
3) program pointer is subject to disturb.In case the microprocessor scheme is established, be exactly to realize function by software.Under strong jamming or certain casual condition, the program pointer of microprocessor may run off normal program circuit, so-called " race flies " state occurs, needs to adopt corresponding software and hardware measure to prevent the generation of fortuitous events such as monitoring unit misoperation in design.
4) the microprocessor hardware system architecture is fixed.Hardware system constitutes scheme in case determine, only task is exactly to programme according to set order set, can be except systemic-function and algorithm by the software change, the performance of system and index have had no way of changing, and the chosen hardware performance in design space defines.
These all belong to general purpose microprocessor intrinsic problem, address these problems the approach that must explore other.Special IC provides a new evolutionary path for the hardware design of electric energy quality monitoring, than universal integrated circuit clearly advantage is arranged all at aspects such as speed, performance, reliability, system flexibility, volume and confidentiality.Research and design has great importance towards the system-level special IC with independent intellectual property right of electric energy quality monitoring.
Summary of the invention
The objective of the invention is to, a kind of method for designing of the electric energy quality monitoring application-specific integrated circuits based on soft nucleus CPU technology is provided.
In order to realize above-mentioned task, the present invention takes following technical solution:
A kind of method for designing of the electric energy quality monitoring application-specific integrated circuits based on soft nucleus CPU technology, it is characterized in that, this method is carried out the design of electric energy quality monitoring application-specific integrated circuits on the power quality monitor design platform that makes up, the hardware circuit of this power quality monitor design platform comprises:
An on-site programmable gate array FPGA is connected with power module, reseting module, adc circuit, system clock, shaping circuit, LCD MODULE, communication module, alarm module and keyboard at the scene on the programmable gate array FPGA; Wherein, adc circuit, shaping circuit are responsible for that electric quantity signal is carried out analog digital and are changed, so that handle; LCD MODULE, keyboard, communication module, alarm module are responsible for man-machine interaction and are communicated by letter; Power module, reseting module are responsible for the power supply of whole platform and are reinitialized;
The design of electric energy quality monitoring application-specific integrated circuits specifically comprises the following steps:
1) electric energy quality monitoring application-specific integrated circuits structural design
Functional requirement according to electric energy quality monitoring application-specific integrated circuits, specified data acquisition function, data processing function, human-computer interaction function and communication function four parts, on-site programmable gate array FPGA is divided into user logic functional area and embedded Nios II data handling system, and is communicated with chip external memory; Wherein, Nios II data handling system comprises Nios II CPU, on-chip memory, serial ports RS-232, keyboard, Liquid Crystal Module are used to realize complicated man-machine interaction, communication, warning, data recording function, give full play to microprocessor and adopt software to realize the superiority of complicated control function; The user logic functional area comprises data acquisition module and data processing module;
2) design of data flow architecture between the electric energy quality monitoring application-specific integrated circuits internal module
Standard integrated circuit internal data flow structure, method of attachment between the design module and work schedule fitting method are with the collaborative work between each processing unit of data-driven;
3) electric energy quality monitoring application-specific integrated circuits related optimization
The purpose of optimal design is under the condition that realizes identical function, reduce the use of resource, the speed of raising system, characteristics according to algorithm have been taked optimized Measures from aspects such as combinational logic, state machine design, global clock design, resources allocations, make design all obtain optimization on the utilization of resources and speed ability;
4) adopt soft nucleus CPU to replace traditional stone microprocessor
According to design, be configured on demand, can the expansion design performance and characteristic satisfy the change of systematic parameter, thereby avoid occurring the out-of-date risk of hardware;
5) at the characteristics of electric energy quality monitoring object, the choose reasonable algorithm is write functional module with Hardware Description Language VHDL, realizes the monitoring to the quality of power supply.
The electric energy quality monitoring application-specific integrated circuits of the present invention's design can replace the core microprocessors in traditional power quality monitor.Replace functional software in the former microprocessor to realize analysis computing by hardware logic electric circuit to power quality parameter, finally finish the monitoring of the on-the-spot operation of electric system parameter with state, realization is to the fault function such as communicate by letter with logout, man-machine interaction and host computer of reporting to the police.Designed electric energy quality monitoring application-specific integrated circuits, finish checking on the testing authentication hardware platform of programmable gate array FPGA (Field Programmable Gate Array) at the scene, proved that whole special integrated circuit is used for the correctness and the rationality of electric energy quality monitoring, carries out seamless conversion by FPGA to ASIC at last.
Description of drawings
Fig. 1 is the hardware circuit diagram of power quality monitor design platform;
Fig. 2 is the structural representation of special IC;
Fig. 3 is a user logic regional structure synoptic diagram in the special IC;
Fig. 4 is an ADC control unit interface block diagram;
Fig. 5 is the data processing module structural drawing;
Fig. 6 is a FFT modular structure block diagram;
Fig. 7 is an each harmonic containing ratio structured flowchart;
Fig. 8 is total percent harmonic distortion structured flowchart;
Fig. 9 is effective value modular structure figure;
Figure 10 is an imbalance of three-phase voltage degree structured flowchart;
Figure 11 is an active power metering modular structure block diagram;
Figure 12 is the control decoding module structured flowchart of Nios II reading;
Figure 13 is Nios II system configuration and address mapping thereof;
Figure 14 is the Nios II system exterior block diagram that design is finished;
Figure 15 is a FPGA hardware pictorial diagram;
For a more clear understanding of the present invention, below in conjunction with the embodiment that accompanying drawing and inventor provide, the present invention is described in further detail.
Embodiment
The method for designing of the electric energy quality monitoring application-specific integrated circuits based on soft nucleus CPU technology of the present invention designs according to the general top-down method for designing of system-level special IC.May further comprise the steps:
1) the power quality monitor function is in the mapping of special IC inside
The function division correctly is mapped on the different soft and hard part resource of special IC, requires the function high, that operand is big to be mapped as an accurate hardware module, have concurrency for real-time; The function less demanding for real-time, that steering logic is complicated is mapped as the task of a specific process, by the soft nuclear of embedded CPU, utilizes software to realize.
Can guarantee that like this special IC that designs had both guaranteed that Core Feature had the advantage of fast operation, stable and reliable operation, have better flexibility again simultaneously, can utilize the software adjustment as required.
2) electric energy quality monitoring application-specific integrated circuits overall system design
According to the built-in function mapping of special IC, special IC is carried out overall design, determine each functional module of system.This special IC is divided into two logic regions with internal circuit: user logic district and the embedded soft nuclear of CPU district.
Wherein the user logic district is responsible for the function of real-time height, fast operation, comprising: data acquisition module, power quality data processing module.Data acquisition module is mainly finished frequency measurement and A/D control; The power quality data processing module comprises the transfinite metering of rate of FFT computing, effective value computing, power measurement, frequency analysis, tri-phase unbalance factor computing, voltage dip and metering break period and voltage.
The soft nuclear of built-in with CPU district makes up the soft nuclear of embedded CPU in special IC, with the man-machine interaction and the communication function of completion logic more complicated.
3) design of data flow architecture between the electric energy quality monitoring application-specific integrated circuits internal module
Because this special IC internal module is many, the frequent data exchange complexity, so standard the IC interior data flow architecture, method of attachment between the design module and work schedule fitting method are with the collaborative work between each processing unit of data-driven.
4) electric energy quality monitoring application-specific integrated circuits related optimization
The purpose of optimal design is under the condition that realizes identical function, reduces the use of resource, improves the speed of system.The present invention has taked optimized Measures according to the characteristics of electric energy quality monitoring algorithm from aspects such as combinational logic, state machine design, global clock design, resources allocations, makes design all obtain optimization on the utilization of resources and speed ability.
5) utilize IP kernel to act on behalf of particular hardware in the electric energy quality monitoring application-specific integrated circuits
In system development, IP Core (Intellectual Property Core, intellectual property core) is the design proposal of most convenient, and it is joined in any standard hardware descriptive language, finishes specific function and does not change original designing program; It does not rely on specific hardware configuration substantially in addition, promptly has the hardware versatility, thereby is easy to upgrade, upgrade.Functional module in this method all is that the IP that adopts hardware description language to write realizes, and in design, utilize the soft nuclear of embedded type CPU---Nios II, substitute traditional stone microprocessor, avoided increasing the additional hardware circuit, the cost of system, the complicacy that has reduced structure and system power dissipation have not only been saved, and avoid being difficult for the expansion of upgrading and function because hardware constraints causes the energy of system single.
6) design of electric energy quality monitoring application-specific integrated circuits verification platform
Electric energy quality monitoring application-specific integrated circuits all needs the support of platform to checking from design, emulation.This platform designs according to the structure of power quality monitor, as core devices, provides standardized peripheral module with programmable special IC, is used to verify the correctness of special IC design.
Below each several part is further described in detail.
1, power quality monitor design platform
The design of carrying out electric energy quality monitoring application-specific integrated circuits must have designs and develops platform accordingly.Shown in Figure 1 is the power quality monitor design platform that the present invention makes up, this power quality monitor design platform is made of the on-site programmable gate array FPGA and the respective peripheral module of the design of checking special IC, wherein on-site programmable gate array FPGA is connected with power module, reseting module, adc circuit, system clock, shaping circuit, LCD MODULE, communication module, alarm module and keyboard at the scene as core on the programmable gate array FPGA; Wherein, adc circuit, shaping circuit are responsible for that electric quantity signal is carried out analog digital and are changed, so that handle; LCD MODULE, keyboard, communication module, alarm module are responsible for man-machine interaction and are communicated by letter; Power module, reseting module are responsible for the power supply of whole platform and are reinitialized; Utilize this platform just can design electric energy quality monitoring application-specific integrated circuits.
2, the structure of special IC
According to the functional requirement of electric energy quality monitoring to special IC, designed its structure, Fig. 2 is a structural representation.According to function, FPGA is divided into two main functional areas: user logic functional areas and the embedded soft nuclear of CPU district (Nios II functional processor district).Data acquisition and data processing module are all realized by the user logic functional areas.Utilize embedded Nios II CPU to realize functions such as complicated man-machine interaction, communication, warning, data recording, give full play to microprocessor and adopt software to realize the superiority of complicated control function.
Shown in Figure 3 is the user logic regional structure, the function of data acquisition, data processing is mainly finished in the user logic zone, that is: frequency measurement and control A/D converter carry out the sampling of simulating signal, give data processing module with the digital signal that converts to then, carry out the transfinite metering of rate of metering of FFT computing, effective value computing, power measurement, frequency analysis, tri-phase unbalance factor computing, voltage dip and break period and voltage, at last operation result is deposited in the sheet in the dual port RAM, wait for the visit of Nios II processor.According to the division of functional module, designed the parallel organization in user logic zone in the electric energy quality monitor, and finished the function in whole zone by some auxiliary control modules.
3, the design of data acquisition module in the integrated circuit
Data acquisition module is the IP kernel of writing by Hardware Description Language VHDL, can finish the analog digital conversion of carrying out at MAX125 that design platform adopts at present, if need to adopt other A/D converter in the actual design, only need the corresponding logic of redesign.
The traditional data acquisition mode all is the controlling of sampling mode that adopts Fixed Time Interval, this mode has certain drawback, we's rule utilizes digital frequency multiplier that the square-wave signal to be measured of following the tracks of mains frequency is carried out digital frequency multiplication, thereby obtains the sampling trigger pulse clko of ADC controller.The coefficient of frequency multiplication module by measured signal weekly the sampling number N of ripple determine that sampling number is ripple 128 points weekly, sampling interval is 156.25us.The A/D converter of selecting for use is MAX125, and this chip is 14 precision, and the single channel slewing rate is the A/D converter of 3us.A slice MAX125 inside has 4 sampling holders, can realize that 4 passages change simultaneously, externally can connect the simulating signal input of 8 passages.The simulating signal of 8 passages is sent into MAX125, and the wait A/D converter is sampled.Effective sampling trigger signal clko of the every output of digital frequency multiplier, ADC controller just finish the once sampling operation of default channel number, stop to wait for the arrival of next trigger pulse then, and the structured flowchart of data acquisition module as shown in Figure 4.
4, the design of data processing module in the special IC
Data processing is the core of electric energy quality monitoring application-specific integrated circuits, and it comprises frequency analysis, effective value, tri-phase unbalance factor, voltage dip and break period, the voltage modules such as rate, power analysis, subsidiary function that transfinite.Fig. 5 is the structural representation of data processing module.
1) frequency analysis module
Frequency analysis is the important content in the electric energy quality monitoring.The frequency analysis module comprises the FFT module, and it is the basis of finishing frequency analysis.
The A.FFT module:
FFT is a kind of fast algorithm of Fourier transform, has become a kind of method of frequency analysis utilization comparative maturity, and the IP kernel that this method is write by VHDL cooperates control module and each harmonic amplitude module to constitute the FFT module.Under the control of FFT_CONTROL module, the FFT_ON_CHIP module is obtained the current data of A/D conversion gained at 128 from dual port RAM, cooperate required control signal to carry out the FFT computing, then gained result's real part, imaginary part and exponential quantity are sent into aftertreatment FFT_AMP module, finally obtain current each harmonic amplitude at 128.This method obtains and the synchronous 100MHz clock signal of global clock by system clock is carried out 2 frequencys multiplication.Under this clock signal, be 12.895 μ s FFT operation time, calculates 8 passage required times and then shorten to 103.16 μ s, and the FFT module just can every once sampling all be carried out a FFT computing to currency like this, obtains being up to 63 times harmonic value.The FFT module as shown in Figure 6.
B. each harmonic containing ratio module:
Each harmonic containing ratio arithmetic core is a division arithmetic, directly utilizes the division module of design voluntarily, cooperates two control modules to read and write control again.Control module 1 provides the clock signal of writing that FFT module output result is write dual port RAM, and control module 2 provides the control signal of reading clock signal, division module and output useful signal and the address signal that reads data in the dual port RAM.When the start signal is effective, for cooperating the clock frequency of FFT module, control module 1 is just sent the result of calculation of 8 passages of FFT module into dual port RAM successively under the 100MHz clock, send the useful signal over of a 50MHz clock period width then, control module 2 detects the over signal when effective, then obtain data under global clock from dual port RAM, the each harmonic containing ratio to 8 passages once calculates successively.Obtain one group of dividend and divisor at every turn and start divider with signal st, after treating that divider calculating finishes, when receiving the done useful signal that divider sends result of calculation is outputed in the dual port RAM of this module-external, obtain next group dividend and divisor once more and carry out next round and calculate.Need to prove, because the each harmonic amplitude result that the FFT module calculates is symmetry status, be that first-harmonic to the 63 subharmonic and the 64th subharmonic to the 127 subharmonic are centrosymmetric, in order to save resource in the sheet, the data that only need obtain first-harmonic to the 63 subharmonic deposit in the dual port RAM.As shown in Figure 7.
C. total percent harmonic distortion module:
Comprise square, add up, evolution and division arithmetic.Wherein, the evolution algorithm is to adopt approximate look-up table method, the division module that the division arithmetic utilization designs voluntarily.Design two control modules, the function class of control module 1 seemingly in the function of control module 1 and the above-mentioned each harmonic containing ratio module, the function of control module 2 is to have increased on the basis of each harmonic containing ratio module square more, added up and the enable signal of rooting module, thereby according to each function sub-modules of sequential scheduling.Structured flowchart as shown in Figure 8.
2) effective value module and subsequent module
All will use effective value mostly in the electric energy quality monitoring index, the calculating that utilizes effective value can carry out many indexs is measured, as tri-phase unbalance factor, voltage dip and break period, the voltage rate etc. that transfinites.
A. effective value module:
As shown in Figure 9.The input data of effective value module are to obtain by the FFT module controls, and current 128 data are given FFT module and effective value module simultaneously in the dual port RAM.Under the effective situation of the control signal rms_rden of FFT module, successively the data of 8 passages are sent into the effective value module and handle.In the effective value module, produce control signal each module among Fig. 9 is carried out sequential scheduling by designing a controller, for example start with zero clearing etc., to satisfy the requirement of operation time sequence to totalizer.Wherein, need to prove that because the FFT module has adopted the 100MHz clock, therefore the effective value module enable signal rms_rden that produces will be the one-period width of 100MHz clock.For Signal Matching therewith, the controller in the effective value module also will be sent in the storer of effective value module in the data in the following dual port RAM of 100MHz clock, and other computing modules still move under the 50MHz clock.
B. tri-phase unbalance factor module:
Adopt the enable signal of the start signal of 2ms as the tri-phase unbalance factor module.When the start signal was effective, the effective value that obtains 8 passages of effective value module output deposited in the dual port RAM, and wait tri-phase unbalance factor module is handled.This method has designed two control modules in the tri-phase unbalance factor module, control module 1 provides the clock signal of writing that effective value module output result is write dual port RAM, and control module 2 provides the control signal of reading clock signal and sub-function module that reads data in the dual port RAM.When the start signal is effective, control module 1 is sent the effective value result of 8 passages into dual port RAM successively under the 50MHz global clock, send the useful signal over of a clock period width then, control module 2 detects this signal when effective, then obtains the three-phase voltage effective value and advances calculation.Electric current tri-phase unbalance factor and voltage tri-phase unbalance factor are similar.Structured flowchart as shown in figure 10.
3) power measurement module
This method adopts discrete method to measure power.During design active power module, asynchronous for fear of u (n) and i (n), after the sampling that needs to wait for 8 passages of same sampled point is all finished, starting power metering module, as long as can before next sampled point begins, finish power calculation, just can guarantee the correctness of calculating.Therefore, in the A/D module, increase a flag signal, finish the sampling of 8 passages as Max125 after, produce the flag signal of one-period width, be used for indicating this time to convert.The power measurement module detects the flag signal when effective, the enable power module.Active power metering module is controlled data write and computing by two control modules.Structured flowchart as shown in figure 11.
When design applied power module, according to effective value module result of calculation, the effective value of 16 in its 8 passage is write in the dual port RAM, calculate then.Be similar to active power metering module, under the control action of two modules, applied power metering module is obtained the effective value of required passage from dual port RAM, send into multiplier module and then obtain result of calculation.
4) design of supplementary module
The total system device also needs some supplementary modules except main functional module, comprise the control module of dual port RAM, FIFO, division module, Nios II reading etc., to satisfy the needs of user logic zone design.
A. data transmission module
Because what this method adopted is that data flow architecture carries out the user logic region design, for each module can collaborative work, in the method for attachment of intermodule by sheet in dual port RAM coordinate to realize as supplementary module.Therefore, on the time of intermodule concurrent working, just need meet certain requirements, that is: the time of each resume module speed is less than the refresh time interval of input data buffer data, to guarantee the response data processing in time of each module, make data flow to next module, avoid occurring data jamming from a module.User logic zone dual port RAM is connected block diagram as shown in Figure 5 with other functional modules.
Result after the A/D conversion leaves in two default dual port RAMs, and the data that are respectively applied between data acquisition module and FFT module, effective value module and the power measurement module cooperate.FIFO is used for cooperating the dual port RAM that links to each other with the effective value module with the FFT module in Fig. 5, the read/write conflict that takes place when avoiding data acquisition and data processing module that it is operated.Because power measurement needs simultaneously the two paths signal value to be handled, being different from the calculating of FFT and effective value only calculates single channel, therefore, data storage method after the A/D conversion is different with the effective value module with FFT, needs to open up in addition between data acquisition module and power measurement module a memory block.
Equally, also be to carry out cooperating of data between FFT module, effective value module and follow-up frequency analysis module (each harmonic containing ratio module and total percent harmonic distortion module), the tri-phase unbalance factor module by dual port RAM.Because FFT and effective value are pressed single-point and are calculated, refreshing frequency fast (every 156.25us refreshes once), and that the monitoring standard real-time of follow-up frequency analysis and tri-phase unbalance factor does not require is too high, and the metering result is based on data complete cycle, can handle by complete cycle, therefore just need FFT and effective value by complete cycle result of calculation import respectively that other one group of dual port RAM is prepared against follow-up frequency analysis module and the tri-phase unbalance factor module reads calculating.
B. the control module of carrying out data interaction with Nios II CPU
For with the soft nucleus CPU data interaction, data processed result need deposit in respectively in the interior dual port RAM of sheet, when soft nucleus CPU is visited certain data processing module when depositing data in the dual port RAM in, if soft nucleus CPU provide respective modules read useful signal and address signal.Wherein, because data processed result writes the frequency difference of dual port RAM separately respectively, come reading of data then to occur read/write conflict easily with Fixed Time Interval for soft nucleus CPU-Nios II.Soft nucleus CPU is that Fixed Time Interval sends a read signal and reads total data, if it is too high with respect to the read signal frequency that soft nucleus CPU sends that the data processing sub-function module writes the frequency of dual port RAM, so very likely soft nucleus CPU all can't read the result of this sub-function module forever in write cycle time.So, twoport RAM1 in the middle of this method is opened up a group in addition, and cooperate controller to coordinate read/write conflict to avoid the generation of above-mentioned situation, its structured flowchart is as shown in figure 12.
When the soft nucleus CPU chip selection signal is effective, soft-core processor reads the data of this chip selection signal institute respective modules under global clock, with en1 is that example is implemented as follows: when chip selection signal en1 was effective, soft-core processor read data among the RAM1, and RAM will can not import data in RAM1.When en1 is invalid, whether writing address signal wraddr or sampling control signal clko that inquiry writes RAM are complete 1, if complete 1 its sub-function module of expression has write the total data of complete cycle to RAM, can import data this moment by RAM in RAM1, get back to original state after finishing and continue inquiry en1 signal; Wraddr is not that 1 its sub-function module of expression does not write whole results to RAM as yet entirely, will keep waiting status.In this process, masked the en1 signal to RAM1 importing data and wait process, made the process of sub-function module importing RAM and the process of soft-core processor reading of data isolate mutually from RAM.
5, the embedded soft nuclear of CPU---Nios II processor
So-called " soft nuclear " just is not meant and solidifies on silicon chip, need be configured and download to IP kernel in the programmable chip to it by eda tool during use.Nios II is a kind of soft nuclear (Soft-Core) CPU.32 Nios II processor adopting of design Harvard structure, data bus and instruction bus are separately.In order to debug conveniently, integrated JTAG debugging module.
After creating Nios II 32 bit CPU modules, according to the function that system will realize, the peripheral components that Nios II processor needs has: LCD, button, LED, communication interface, FLASH storer, SRAM storer.According to used peripheral hardware and device property, the module that the system that sets up from SOPC Builder will add comprises: button PIO, LCD PIO, LED PIO, external bus (Avalon tri-state bridge), external RAM interface, outside FLASH interface, RS-232 interface and with the interface in user logic zone.
Specify separately base address in eda software each assembly in the Nios II system, the base address of FLASH is set to 0x00000000, and locking, so that software address stored and need not consider the offset address value in the FLASH storer.Complete system configuration and address mapping thereof are as shown in figure 13.
Arrange external memory address and scope, for peripherals and interface are provided with required interrupt priority level, configuration peripherals is set up and is kept required condition, sets the file that is used for ROM, RAM in the initialization sheet.After the compiling of Nios II system is finished, generate exterior block diagram.According to the electric energy quality monitor requirement, Nios II soft nucleus CPU system is finished in the configuration design, and the final system module that generates as shown in figure 14.
The electric energy quality monitoring application-specific integrated circuits sample of finishing according to above design procedure as shown in figure 15.
Claims (1)
1. method for designing based on the electric energy quality monitoring application-specific integrated circuits of soft nucleus CPU technology, it is characterized in that, this method is carried out the design of electric energy quality monitoring application-specific integrated circuits on the power quality monitor design platform that makes up, the hardware circuit of this power quality monitor design platform comprises:
An on-site programmable gate array FPGA is connected with power module, reseting module, adc circuit, system clock, shaping circuit, LCD MODULE, communication module, alarm module and keyboard at the scene on the programmable gate array FPGA; Wherein, adc circuit, shaping circuit are responsible for the conversion of simulating signal to digital signal, so that handle; LCD MODULE, keyboard, communication module, alarm module are responsible for man-machine interaction and are communicated by letter; Power module, reseting module are responsible for the power supply of whole platform and are reinitialized;
The design of electric energy quality monitoring application-specific integrated circuits specifically comprises the following steps:
1) electric energy quality monitoring application-specific integrated circuits structural design
Functional requirement according to electric energy quality monitoring application-specific integrated circuits, specified data acquisition function, data processing function, human-computer interaction function and communication function four parts, on-site programmable gate array FPGA is divided into user logic functional area and embedded Nios II data handling system, and is communicated with chip external memory; Described Nios II data handling system comprises Nios IICPU, on-chip memory, serial ports RS-232, keyboard, Liquid Crystal Module, be used to realize complicated man-machine interaction, communication, warning, data recording function, give full play to microprocessor and adopt software to realize the superiority of complicated control function; The user logic functional area comprises data acquisition module and data processing module, data acquisition module is the IP kernel of writing by Hardware Description Language VHDL, finish the A/D converter that is adopted at the power quality monitor design platform, carry out the conversion of simulating signal to digital signal, utilize digital frequency multiplier that the square-wave signal to be measured of following the tracks of mains frequency is carried out digital frequency multiplication, thereby obtain the sampling trigger pulse clko of ADC controller, the coefficient of digital frequency multiplier by measured signal weekly the sampling number N of ripple determine, sampling number is ripple 128 points weekly, sampling interval is 156.25us, the A/D converter of selecting for use is that model is the chip of MAX125, MAX125 is 14 precision, the single channel slewing rate is 3us, a slice MAX125 chip internal has 4 sampling holders, can realize that 4 passages change simultaneously, externally can connect the simulating signal input of 8 passages, the simulating signal of 8 passages is sent into MAX125, the wait A/D converter is sampled, effective sampling trigger pulse clko of the every output of digital frequency multiplier, the ADC controller is just finished the once sampling operation of default channel number, stops to wait for the arrival of next trigger pulse then; Data processing module is the core of electric energy quality monitoring application-specific integrated circuits, and data processing module comprises: frequency analysis, effective value, tri-phase unbalance factor, voltage dip and break period, voltage transfinite rate, power analysis, subsidiary function module: maintenance data processing modules implement FFT computing, the computing of each harmonic containing ratio, effective value computing, carry out the transfinite measurements and calculations of rate of tri-phase unbalance factor computing, voltage dip and break period, voltage;
2) design of data flow architecture between the electric energy quality monitoring application-specific integrated circuits internal module
Standard integrated circuit internal data flow structure, method of attachment between the design module and work schedule fitting method are with the collaborative work between each processing unit of data-driven;
3) electric energy quality monitoring application-specific integrated circuits related optimization
The purpose of optimal design is under the condition that realizes identical function, reduce the use of resource, improve the speed of electric energy quality monitoring application-specific integrated circuits, taked optimized Measures according to FFT computing, the computing of each harmonic containing ratio, effective value computing, the transfinite characteristics of measurements and calculations of rate of tri-phase unbalance factor computing, voltage dip and break period, voltage of carrying out from combinational logic, state machine design, global clock design, resources allocation aspect, made design on the utilization of resources and speed ability, all obtain optimization;
4) adopt soft nucleus CPU to replace traditional stone microprocessor
The IP kernel that functional module in this method adopts hardware description language to write is realized, and in design, utilize the soft nuclear of embedded type CPU---Nios II, substitute traditional stone microprocessor, avoided increasing the additional hardware circuit, the cost of electric energy quality monitoring application-specific integrated circuits, the complicacy that has reduced structure and system power dissipation have not only been saved, and avoid being difficult for the expansion of upgrading and function because hardware constraints causes the single of electric energy quality monitoring application-specific integrated circuits;
5) at the characteristics of electric energy quality monitoring object, the choose reasonable algorithm is write functional module with Hardware Description Language VHDL, realizes the monitoring to the quality of power supply.
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