CN101197346A - 纳米熔断器结构布置及其制造方法 - Google Patents

纳米熔断器结构布置及其制造方法 Download PDF

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CN101197346A
CN101197346A CNA2007101866069A CN200710186606A CN101197346A CN 101197346 A CN101197346 A CN 101197346A CN A2007101866069 A CNA2007101866069 A CN A2007101866069A CN 200710186606 A CN200710186606 A CN 200710186606A CN 101197346 A CN101197346 A CN 101197346A
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fuse
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杨海宁
J·A·曼德尔曼
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International Business Machines Corp
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Abstract

纳米熔断器结构布置例如包括其上形成有导电区域的半导体衬底；其最大直径小于约50nm且最大长度小于约250nm的并形成在导电区域上的导电细长纳米结构；具有与纳米结构的细长外表面完全分隔开且完全围绕纳米结构的细长外表面的阻挡部分的阻挡层，该阻挡层和表面之间的空间基本上由真空构成，并且近乎等距离地分隔开，使得导电细长纳米结构可以响应于可在其中流动的在从大约4μA到大约120μA的范围内的电流而熔断。

Description

纳米熔断器结构布置及其制造方法
技术领域
本发明总体涉及纳米熔断器(nano-fuse)结构，并且更具体地涉及包括纳米熔断器结构并具有对邻近器件或者其它结构的熔断器熔断保护的布置。
背景技术
随着电子电路尺寸的减小，对更高密度的有源和无源器件结构的需求增加。已知各种纳米熔断器结构及其布置，例如包括可熔断熔丝(link)，其具有约为(±10％)50nm且典型地约为20nm的最大横截面直径。该熔丝包括一种或者多种导电材料，并且例如通过在熔丝上流过过度电流而熔断。导电材料包括例如金属、金属硅化物或者导电(例如，掺杂)半导体。图1示出了常规电可编程熔断器(eFuse)布置的示意电路图，诸如连接至驱动晶体管的纳米熔断器结构，其中Vdd大约3伏，并且其中大约4mA的电流I将会熔断熔丝。
例如在下列文献中讲授了常规的或者公知的熔断器、eFuse或者纳米熔断器结构布置：2003年9月23日授权的美国专利No.6,624,499 B2，Kothandaraman等人的SYSTEM FOR PROGRAMMINGFUSE STRUCTURE BY ELECTROMIGRATION OF SILICIDEENHANCED BY CREATING TEMPERATURE GRADIENT；2003年8月26日授权的美国专利No.6,611,039 B2，Thomas C.Anthony的VERTICALLY ORIENTED NANO-FUSE AND NAN0-RESISTORCIRCUIT ELEMENTS，以及2006年3月7日授权的美国专利No.7,009,222 B2，Chao-Hsiang Yang的PROTECTIVE METALSTRUCTURE AND METHOD TO PROTECT LOW-K DIELECTRICLAYER DURING FUSE BLOW PROCESS，这里通过参考将它们的全部内容引入。
在熔断器熔丝熔断期间，金属或者其它颗粒材料(particulatematerial)从熔丝释放出(例如，熔断)，并且可能影响附近的器件或者其它结构。而且，与熔断器熔丝接触的或者与其相距非常近的材料会增加熔断或者断开熔断器熔丝所需的电功率或者电流。
用于实现熔断器熔丝熔断效果的几种公知布置包括：例如授予Yang的专利No.US 7,009,222 B2公开了护圈(guard ring)，其包括围绕最上面金属间电介质(IMD)层中熔断器部分的金属互连结构；以及授予Anthony的专利No.US 6,611,039 B2公开了围绕绝缘插头的纳米熔断器隔离物(spacer)，该绝缘插头可以被拔出以提供用于熔化的或者蒸发的熔断器材料进入的空间。例如，参见授予Anthony的‘039专利的第5栏，第1-8行。
尽管这些公知布置是有帮助的，但是从本发明人的角度来看，这些公知布置并未被证明是完全满意的，因为本发明人认为例如熔断器熔丝的将要熔断的部分与诸如低k电介质材料的各种材料保持密切物理接触。
除了诸如由于来自熔断器熔丝熔断或者断开期间释放出的颗粒和其它材料的污染而影响所接触(例如，电介质)层的缺陷外，此密切物理接触还影响熔断熔断器熔丝所需的功率或电流。
本发明人认为这些以及其它缺陷在本发明中得以克服。
发明内容
因此，本发明的首要目的是提供一种纳米熔断器结构布置，其降低熔断或者断开熔断器熔丝所需的电功率或者电流。
本发明的另一目的在于提供一种纳米熔断器结构布置，其降低由熔断器熔丝熔断释放出的材料引起的对围绕熔断器熔丝的器件或者其它结构的不利影响。
本发明的另外目的在于提供制造以及操作这样的纳米熔断器结构布置的方法。
本发明的前述目的和其它目的在这样的纳米熔断器结构布置中实现，其包括其上形成有导电区域的半导体衬底；最大直径小于约50nm且最大长度小于约250nm并形成在导电区域上的导电细长纳米结构；具有与纳米结构的主要细长表面完全分隔开且完全围绕纳米结构的主要细长表面的阻挡部分的阻挡层，阻挡部分和主要细长表面之间的空间基本上由真空构成，并且近乎等距离分隔开，使得导电细长纳米结构可以响应于可在其中流动的在从大约4μA到大约120μA范围内的电流而熔断。
在本发明的另一个实施方式中，该空间基本上由诸如空气或者惰性气体的流体构成，而不是基本上由真空构成。
本发明的实施方式包括纳米结构，其可以是纳米引线、纳米管或者甚至用大马士革形成的导电体。纳米引线或者纳米管例如适当地掺杂或者注入有诸如As、P或者诸如Ni、Ti或W的金属的导电掺杂剂，和/或适当地设置(例如，镀覆)有诸如Ti、Ta、Ni或者W的导电外层。
阻挡部分形成例如圆柱形空腔或者通孔。本发明的实施方式包括纳米结构，其被置于空腔内导电区域上的大约中心位置并从该位置延伸，使得纳米结构的主要细长表面与阻挡部分近乎等距离分隔开。
本发明还包括制造和操作纳米熔断器结构布置的方法。
有益地，由于纳米结构(诸如纳米引线或者纳米管)的主要部分与周围阻挡层壁(例如电介质)通过基本上由真空或者适当绝缘流体(例如，周围空气或者惰性气体)构成的空间分隔开，所以用于熔断器熔丝熔断的功率或者电流的要求降低，并且对周围结构(例如，电介质阻挡层)和任何邻近器件(例如，晶体管)的损害减轻。
但是，本发明人已经意识到美国专利申请公开No.US2005/0104056 A1，2003年6月18日提交、2005年5月19日公布的Mizuhisa Nihei的ELECTRONIC DEVICE USING CARBONELEMENT LINEAR STRUCTURE AND PRODUCTION METHODTHEREOF，在此通过参考将其全部引入。Nihei的公开披露了一种电子器件，其包括在过孔内部暴露的硅化物层上垂直生长的一个或者多个碳纳米管。例如，参见Nihei的公开的图4C、第[0037]段和第[0038]段。
附图说明
通过以下结合附图的详细说明，本发明的各种特征和方面将变得更加明白，附图中：
图1示出了常规半导体eFuse结构布置的一般示意电路图；
图2A、2B、3A和3B是当执行用于制造根据本发明的如图12、17和23所示的布置的最终实施方式的方法时形成的顺序中间结构布置的顶部平面示意图和侧部剖面示意图；
图4和图5是当执行用于制造根据本发明的布置的方法时形成的又一个顺序中间结构布置的另外的侧部剖面示意图；
图6A和图6B是根据本发明第一实施方式的又一个顺序中间结构布置的另外的顶部平面示意图和侧部剖面示意图；
图7、图8、图9、图10和图11是根据本发明第一实施方式的另外的顺序中间结构布置的侧部剖面示意图；
图12、图17和图23是分别根据本发明的第一、第二和第三实施方式的最终结构布置；
图13、图14、图15和图16是根据本发明第二实施方式的顺序中间结构布置的侧部剖面示意图；
图18、图19、图20、图21和图22是根据本发明第三实施方式的顺序中间结构布置的侧部剖面示意图；以及
图24是在熔断器熔丝熔断后的图12布置的侧部剖面示意图，其中示出了颗粒材料或者熔断部分P。
具体实施方式
现在转到附图，尤其转到图2至图12，所示为各种中间顺序结构布置，它们在各步骤期间产生以制造根据本发明的纳米熔断器结构布置的第一实施方式(图10、图11或者图12)。仅详细描述那些理解本发明所需实施方式的特征或者方面。鉴于直接的说明和附图，本领域技术人员容易知道并理解对于执行方法以及制造根据本发明的布置有用的各种技术和工具。
在图2A和沿着线A-A截取的剖面视图(图2B)中，提供半导体衬底10。衬底10是体硅，但是可替代地是绝缘体上硅(SOI)或者其它合适的衬底。
在图3A和沿着线A-A截取的剖面视图(图3B)中，至少一个MOS器件20以任何常规方式形成在衬底10上。MOS器件20包括栅极叠层，该栅极叠层具有形成在置于衬底10上的栅极氧化物24上的多晶硅栅极22。可替代地，栅极22是金属栅极。隔离物26以任意常规方式由电介质材料形成。器件20经历常规掺杂/注入以形成源极导电区域S和漏极导电区域D以及扩展区(未示出)。
接着，器件20包括以任意常规方式在栅极22上和与MOS器件邻近的导电区域中形成的硅化物接触28，在这种情况下，该MOS器件是诸如NFET的MOSFET。另外的硅化物接触(未示出)可以形成在诸如源极区域S的其它导电区域中。参见图4的侧部剖面示意图。形成MOS器件20包括各种常规的、公知的且不需要进一步讨论的步骤：层沉积、刻蚀、掺杂(载流子引入)和硅化。关于MOS或者CMOS器件制造的更多细节，可以参见例如2003年4月15日授权的美国专利No.6,548,877 B2，Yang等人的METAL OXIDESEMICONDUCTOR FIELD EFFECT TRANSISTOR FOR REDUCINGRESISTANCE BETWEEN SOURCE AND DRAIN；和2000年2月22日授权的美国专利No.6,028,339，Frenette等人的DUAL WORKFUNCTION CMOS DEVICE，在此通过参考将它们的全部内容引入。
接着，将共形绝缘层30沉积在如图5的进一步剖面示意图中所示的中间结构布置上。
层30例如是诸如低k电介质(例如，具有小于约3.2的介电常数)的绝缘体。例如，层30是SiCHO电介质材料，并用诸如PECVD或者旋涂(spin-on)的任何常规技术进行沉积。
根据本发明，形成空腔或者通孔32使之穿过层30，并且在第一实施方式中穿过硅化电接触28到达衬底10，如图6A的顶部平面视图和侧部剖面视图(图6B)中所示。
空腔32例如通过刻蚀形成，诸如使用利用光致抗蚀剂掩膜(未示出)的反应离子刻蚀(RIE)。在第一实施方式中，通孔32具有近似圆柱体的形状、近似均匀的直径d和近似均匀的高度h。空腔32的直径d选自直径范围：从大约50nm到大约100nm。空腔32的高度h选自高度范围：从大约100nm到大约180nm。
在图7中，示出将共形催化层40沉积在图6A和图6B中所示的整个中间结构布置上。层40是例如Ti或者Ru，并且通过物理气相沉积(PVD)、离子溅射或者原子层沉积(ALD)来进行沉积。PVD是气相中的薄膜沉积工艺，其中源极材料在真空中物理地转移到衬底10和其它材料。衬底10位于常规薄膜工艺设备(未示出)的适当的腔室或者反应器中。层40在空腔32之外具有从大约5nm到大约30nm范围内的厚度以及在空腔32内具有从大约2nm到大约10nm的范围内的厚度。该厚度近似均匀。
接着，对图7中所示结构进行退火以在金属40和硅10具有直接接触的位置11处形成金属硅化物。通过公知技术将层40的未反应部分去除以形成图8的剖面示意图所示的种子部分42。层40的未反应部分的去除通过例如使用含NH4OH和H2O2的溶液进行选择性湿法刻蚀来完成。
接着，在空腔32内形成并布置合适的纳米结构(例如，被进一步处理以形成导电纳米引线50’的纳米引线50)，以便可以响应于可在纳米结构50’中流动的预定电流I而熔断。决定这种电流的因素包括：(i)纳米结构50’的组成、(ii)纳米结构的形状和尺寸(例如，高度/长度和宽度/直径)、(iii)纳米结构的主要部分和非常相接近的其它结构之间的空间关系，以及(iv)包括纳米结构50’的保持环境。根据本发明的实施方式：包含结构(例如，50’)的主要部分MA(图11)的保持环境基本上由真空或者惰性流体构成，与纳米结构的主要部分最邻近的结构是阻挡层(例如，30、60)、接触28和衬底10(对于本发明的第一实施方式)。
再次返回图8，为了形成结构50’，将纳米引线50(例如，Si)形成在空腔32中并完全地与形成空腔32的绝缘层30的周围壁31分隔开。通过诸如在从400℃到600℃温度范围内，将图8的结构暴露于含有诸如SiH4或者Si2H6的气体的硅一段合适的时间的公知技术来形成纳米引线50。通过诸如在引线形成期间适当地掺杂该引线和/或通过适当的硅化或者另外通过将导电材料引入纳米引线50上或者引入其中来使引线50导电。对于Si纳米引线，典型的气体前体包括那些通常用于Si层的CVD的气体前体，即Si2H6、SiH4、SiH2Cl2和SiCl4，对它们的选择很大程度上依赖于所用的反应器以及所需的催化生长和未催化生长的比率。可以添加掺杂剂气体，诸如硼烷(B2H6)和磷烷(PH3)以控制纳米引线的电阻率。为了进一步的细节，参见图9和图10以及以下的公开：
a)Kawano等人的SELECTIVE VAPOR-LIQUID-SOLID EPITAXIALGROWTH OF MICRO-SI PROBE ELECTRODE ARRAYS WITHON-CHIP MOSFETS ON SI(111)SUB STRATES，IEEE Transactions on Electron Devices，第51卷、第3期、2004年3月，第415-420页；
b)Yang等人的CATALYCTIC SYNTHESES OF SILICONNANOWIRES AND SILICA NANOTUBES，2004年，4th IEEE Conference onNanotechnology，第448-450页；
c)Yung等人的ELECTROLESS PLATING OF NICKEL ONCARBON NANOTUBES FILM，2005 Electronics Packaging Technology Conference，第636-638页；以及
d)Hoenlein等人的CARBON NANOTUBE APPLICATIONS INMICROELECTRONICS，IEEE Transactions on Components and Packaging Technologies，第27卷、第4期，2004年12月，第629-634页，通过参考将这些公开的全部内容都在此引入。
导电纳米引线50’与衬底10的导电区域(例如D)导电接触，如图10所示。
接着，沉积诸如SiO2或者SiCHO的另一个共形绝缘层60，并随后在某种程度上去除层60以使得纳米引线50’的端部51暴露。该去除通过化学机械抛光(CMP)或者其它常规去除技术完成，见图11。在图11中，掺杂的和/或硅化的纳米引线50’具有主要细长部分MA和次要细长部分MI。部分MA具有细长最外表面MAS，其与阻挡层壁31近乎等距离(图12中的箭头dd)分隔开。由于在密闭处理环境中(例如，未示出的半导体处理腔室)形成纳米引线结构布置(例如图11)，所以完全围绕主要表面MAS的空间32’基本上由真空或者诸如在合适压力下的惰性气体的其它期望的流体绝缘体构成。惰性气体包括例如氩气、氮气或者氦气。
在图11中，根据本发明，形成并布置空腔32中纳米引线50’的部分MA以响应于流过引线50’的阈值电流I而断开或者熔断，该电流具有从大约4μA到大约120μA的范围内选出的大小。用于这些电流的最终纳米引线50’的最外面尺寸是：最大直径MAXD从大约10nm到大约50nm的范围内选出，并且最大高度MAXH从大约100nm到大约250nm的范围内选出。直径近似均匀；高度近似均匀。当熔断时，纳米引线50’释放出颗粒或者熔化材料，这些颗粒或者熔化材料包含在空腔32内而不影响器件20。鉴于直接的说明和附图，形成并布置引线50’以及本发明的其它实施方式对于本领域技术人员而言都是熟知的。
最后，在图12中，将金属导体70常规地形成为与端部51电接触。导体70例如是铜、钨或者金属硅化物，并且通过电镀、化学气相沉积或者离子溅射来形成。层80是层间电介质层，其包括SiCHO并且使用常规CVD工艺或者旋涂方法沉积。层80典型地在形成导体70前形成。
在图13至图17中示出了制造本发明的第二实施方式，以及在图18至图23中示出了制造本发明的第三实施方式。
根据第二实施方式，纳米结构是掺杂的和/或硅化的纳米管CNT’。根据本发明的第三实施方式，纳米结构是金属或者金属合金导体C。
根据第二实施方式，图13至图17示出了跟随图5所示结构之后产生的结构。在此实施方式中，空腔321不延伸穿过硅化接触281，如图13所示。碳纳米管CNT通过公知技术形成在接触281上(图14)，并且随后通过公知技术进行掺杂和/或硅化(图15)。碳纳米管的掺杂可以通过使用碱性金属，诸如但不限于Li、Na、K和Cs，以及使用单一金属富勒烯封装镧系元素(mono-metallofullereneencapsulating lanthanide elements)，诸如但不限于Ce、Nd、Gd、Dy来实现，或者通过使用例如F的部分化学特质和/或使用例如B和N在碳纳米管的侧壁上进行替代掺杂来实现。也参见美国专利申请公开No.US 2005/0167755 A1，Dubin等人的MICROCIRCUITFABRICATION AND INTERCONNECTION，将其在此引入。沉积绝缘体601(图16)，并且随后进一步形成绝缘体801和金属布线701(图17)。
根据第三实施方式，图18至图23示出了跟随图5所示结构之后产生的结构。在图23中，纳米结构C是这样的导体，其具有从导体的一端向导体的相对端变细的或者递减的最大直径，如所示。
尽管出于描述优选实施方式的目的，已经在此说明并且描述了特定实施方式，但是本领域技术人员将理解到，在不脱离本发明范围的情况下，为实现相同目的而计划的各种替代方案和/或等同实现均可以替代所示出和描述的特定实施方式。本领域技术人员将容易理解到，本发明可以用各种各样的实施方式实现。本申请意在覆盖在此描述的实施方式的任何修改或者变体。因此，本发明显然仅由权利要求和其等同方案所限制。

Claims (21)

1.一种纳米熔断器结构布置，包括：
半导体衬底，其上形成有导电区域；
导电细长纳米结构，其具有在从大约10nm到大约50nm范围内的最大直径和在从大约100nm到大约250nm的最大长度，并且形成在所述导电区域上；
阻挡层，其具有与所述纳米结构的细长外表面完全分隔开且完全围绕所述细长外表面的阻挡部分，所述阻挡层和表面之间的空间基本上由真空构成并且近乎等距离地分隔开，使得所述导电细长纳米结构可以响应于可流过所述纳米结构的在从大约4μA到大约120μA的范围内的电流而熔断。
2.根据权利要求1所述的布置，所述导电细长纳米结构包括导电纳米引线，并且所述近乎等距离的空间在从大约5nm到大约20nm的范围内。
3.根据权利要求1所述的布置，所述导电细长纳米结构包括导电掺杂剂。
4.根据权利要求1所述的布置，所述外表面包括金属硅化物.
5.根据权利要求1所述的布置，所述阻挡层包括电介质材料。
6.根据权利要求1所述的布置，所述阻挡层包括基本上由SiCHO构成的低k电介质材料。
7.根据权利要求1所述的布置，所述阻挡层还包括设置在所述空间之上的帽层。
8.根据权利要求7所述的布置，所述导电细长纳米结构延伸至所述帽层中。
9.根据权利要求8所述的布置，所述帽层包括低k电介质材料。
10.根据权利要求2所述的布置，所述导电纳米结构包括碳纳米管，所述碳纳米管的外部表面层包括从由金属和金属硅化物组成的组中选择的材料。
11.根据权利要求10所述的布置，所述外部表面层是从由Ni、Co、Pt或者Cu构成的组中选择的材料。
12.根据权利要求8所述的布置，所述纳米结构完全延伸穿过所述帽层。
13.根据权利要求12所述的布置，还包括导电层，其设置在所述帽层上并与所述纳米结构电接触。
14.根据权利要求1所述的布置，所述电流不大于60μA。
15.一种纳米熔断器结构布置，包括：
半导体衬底；
电接触，其设置在所述衬底上；
导电细长纳米结构，其形成在所述接触上，所述导电纳米结构具有小于约20nm的最大直径；
保护阻挡层，其具有完全围绕所述导电纳米结构的最外面主要细长部分的部分，所述阻挡层的所述部分包括电介质材料并与所述导电纳米结构的细长部分的最外表面完全分隔开，所述纳米结构形成并布置成使得所述纳米结构可以响应于可在其中流动的在从大约4μA到大约120μA的范围内的电流而熔断。
16.根据权利要求15所述的布置，所述阻挡层还包括布置在所述半导体衬底上的硅化物。
17.根据权利要求15所述的布置，所述表面与所述电介质材料之间的最小间隔在从大约5nm到大约20nm的范围内。
18.根据权利要求1所述的布置，所述阻挡层和表面之间的空间基本上由流体构成。
19.一种熔断纳米熔断器结构的方法，包括：
提供半导体衬底，其上形成有细长导电纳米结构，所述细长导电纳米结构的主要部分设置在由阻挡层的部分形成的空腔内并由所述空腔围绕，所述纳米结构的主要部分与所述阻挡层的部分分隔开；
使电流流过所述纳米结构，以便熔断所述空腔内纳米结构的至少一部分，所述电流在从大约4μA到大约120μA的范围内，并且随后
将所熔断的部分包含在所述空腔中。
20.一种形成纳米熔断器结构布置的方法，包括：
提供半导体衬底；
形成至少一个MOSFET器件，其具有在所述衬底上的栅极叠层；
在所述MOSFET器件的栅极叠层上和邻近所述MOSFET器件的导电区域中都形成硅化接触以制得第一结构布置；
在所述第一结构上设置第一绝缘层；
形成穿过所述第一绝缘层并穿过所述导电区域中的硅化接触到达所述衬底的空腔，以制得第二结构；
在所述第二结构上设置催化层；
去除所述催化层以形成种子部分；
在所述空腔中形成纳米引线；
在所述纳米引线上引入导电材料以制得第三结构布置；
在所述第三结构布置上设置第二绝缘层，使得所述空腔只含有所述纳米引线和基本上由真空构成的空间；
去除所述第二绝缘层的一部分以将所述纳米引线的一端暴露，并且随后
在所述一端处设置电导体，使得所述纳米引线可以响应于在从4μA到120μA范围内的电流而熔断。
21.根据权利要求20所述的方法，所述去除催化层的步骤包括选择性地刻蚀该层以形成所述种子部分。
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