CN101183131A - 边界扫描环境下电路板互连故障的内建测试实现方法 - Google Patents
边界扫描环境下电路板互连故障的内建测试实现方法 Download PDFInfo
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CNB2007103039910A CN100510763C (zh) | 2007-12-24 | 2007-12-24 | 边界扫描环境下电路板互连故障的内建测试实现方法 |
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CNB2007103039910A CN100510763C (zh) | 2007-12-24 | 2007-12-24 | 边界扫描环境下电路板互连故障的内建测试实现方法 |
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CN101183131A true CN101183131A (zh) | 2008-05-21 |
CN100510763C CN100510763C (zh) | 2009-07-08 |
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101464494B (zh) * | 2009-01-19 | 2011-03-23 | 北京大学 | 一种现场可编程门阵列器件中使用的互连线测试电路 |
CN102565682A (zh) * | 2010-12-14 | 2012-07-11 | 苏州工业园区谱芯科技有限公司 | 一种基于二分法的故障测试向量的定位方法 |
CN103675641A (zh) * | 2013-12-23 | 2014-03-26 | 龙芯中科技术有限公司 | 芯片故障定位方法、装置及系统 |
CN103675576A (zh) * | 2012-09-18 | 2014-03-26 | 英业达科技有限公司 | 基于边界扫描的芯片连接测试系统及其方法 |
TWI476422B (zh) * | 2010-02-12 | 2015-03-11 | Synopsys Shanghai Co Ltd | Scanning Chain Reconfiguration Method and Device Based on Bidirectional Optimization Selection in Entity Design |
CN111933206A (zh) * | 2020-07-31 | 2020-11-13 | 上海安路信息科技有限公司 | Ddr物理层地址命令路径的内建自测试方法及测试系统 |
WO2023028743A1 (zh) * | 2021-08-30 | 2023-03-09 | 华为技术有限公司 | 用于设计逻辑门网络的方法和电子设备 |
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2007
- 2007-12-24 CN CNB2007103039910A patent/CN100510763C/zh not_active Expired - Fee Related
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101464494B (zh) * | 2009-01-19 | 2011-03-23 | 北京大学 | 一种现场可编程门阵列器件中使用的互连线测试电路 |
TWI476422B (zh) * | 2010-02-12 | 2015-03-11 | Synopsys Shanghai Co Ltd | Scanning Chain Reconfiguration Method and Device Based on Bidirectional Optimization Selection in Entity Design |
CN102565682A (zh) * | 2010-12-14 | 2012-07-11 | 苏州工业园区谱芯科技有限公司 | 一种基于二分法的故障测试向量的定位方法 |
CN102565682B (zh) * | 2010-12-14 | 2014-05-28 | 苏州工业园区谱芯科技有限公司 | 一种基于二分法的故障测试向量的定位方法 |
CN103675576A (zh) * | 2012-09-18 | 2014-03-26 | 英业达科技有限公司 | 基于边界扫描的芯片连接测试系统及其方法 |
CN103675641A (zh) * | 2013-12-23 | 2014-03-26 | 龙芯中科技术有限公司 | 芯片故障定位方法、装置及系统 |
CN103675641B (zh) * | 2013-12-23 | 2016-04-27 | 龙芯中科技术有限公司 | 芯片故障定位方法、装置及系统 |
CN111933206A (zh) * | 2020-07-31 | 2020-11-13 | 上海安路信息科技有限公司 | Ddr物理层地址命令路径的内建自测试方法及测试系统 |
CN111933206B (zh) * | 2020-07-31 | 2021-06-18 | 上海安路信息科技股份有限公司 | Ddr物理层地址命令路径的内建自测试方法及测试系统 |
WO2023028743A1 (zh) * | 2021-08-30 | 2023-03-09 | 华为技术有限公司 | 用于设计逻辑门网络的方法和电子设备 |
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CN100510763C (zh) | 2009-07-08 |
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Assignee: Beihang University Assignor: Zhejiang Sheng Ti Technology Industry Co., Ltd. Contract record no.: 2010330002112 Denomination of invention: Built-in testing realization method of circuit board interconnect fault under boundary scanning environment Granted publication date: 20090708 License type: Exclusive License Open date: 20080521 Record date: 20101101 |
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Assignee: Zhejiang Sheng Ti Technology Industry Co., Ltd. Assignor: Beihang University Contract record no.: 2010330002112 Denomination of invention: Built-in testing realization method of circuit board interconnect fault under boundary scanning environment Granted publication date: 20090708 License type: Exclusive License Open date: 20080521 Record date: 20101101 |
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