CN101145579B - 具有槽沟的源体短路电极的、逆槽沟和源极接地的场效应晶体管结构 - Google Patents

具有槽沟的源体短路电极的、逆槽沟和源极接地的场效应晶体管结构 Download PDF

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CN101145579B
CN101145579B CN200710149391.3A CN200710149391A CN101145579B CN 101145579 B CN101145579 B CN 101145579B CN 200710149391 A CN200710149391 A CN 200710149391A CN 101145579 B CN101145579 B CN 101145579B
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CN101145579A (zh
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雷燮光
弗兰克斯·赫尔伯特
安荷·叭剌
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Chongqing Wanguo Semiconductor Technology Co ltd
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Abstract

本发明披露一种底源横向扩散式MOS(BS-LDMOS)器件。该器件的源区横向设置，跟半导体基底顶面附近的漏区相对，基底上支持的门极处于源区跟漏区之间。该BS-LDMOS器件还有一个结合的陷阱-沟道区，其在半导体基底中设置的深度完全低于体区，后者设置在接近顶面的源区附近，其中结合的陷阱-沟道区起埋置的源-体接点功能，从而将体区和源区电连接到基底的底面，起源电极的功能。将其漂移区设置在门极下面靠近顶面，跟源区有一段距离，并且延伸到包围漏区。该结合的陷阱-沟道区延伸到漂移区下面，并且该结合的陷阱-沟道区具有的掺杂剂的传导率跟漂移区的相反且补偿了漂移区，来减小源-漏电容。

Description

具有槽沟的源体短路电极的、逆槽沟和源极接地的场效应晶体管结构
技术领域
本发明涉及半导体功率器件，更具体地涉及逆槽沟的和源极接地的场效应晶体管结构(FET)，其中采用了槽沟的源体短路电极的传导基底。
背景技术
对于包含源极电感的FET、MOSFET(金属氧化物半导体场效应晶体管)和JFET(结型场效应管)等半导体功率器件，常规技术对于进一步降低其源极电感面临一些技术困难和局限性。尤其是，本领域的技术人员对于减小源极电感面临技术挑战。同时，因为越来越多的功率器件应用要求这些器件具有高效率、高增益和适应高频率的功能，对于半导体功率器件这些不断增长的需求都要求减小其源极电感。一般来说，取消半导体功率器件包内的焊接线就能减小源极电感。通过配置半导体基底作为源极来连接半导体功率器件，做了许多努力来取消焊接线。这类办法也有困难，因为在通常的垂直式半导体功率器件中是将漏极安排在基底上的。参照图1A和1B所分别表示的带槽沟的和平面的DMOS(双扩散金氧化物半导体器件)器件，这两类垂直式功率器件采用基底作为漏极，其中的电流从源极流到下面设置在基底的底上的漏极区域。在器件包装工艺中对于顶上的源电极的电连接通常需要焊接线，这样就增加了源极电感。
参照图1C，由Seung-Chul Lee等人在Physica Cripta T101，pp.58-60，2002所披露的新型垂直式沟道LDMOS(横向扩散金属氧化物半导体)器件，图示为标准的垂直式带槽沟的DMOS结构，其中漏极接点设置在顶面边缘上，而源极仍设在活性区顶面。然而，这个器件中顶上的漏极接点所需的横向间隔造成单元横距变大的局限性。除了单元横距变大的局限性，带有槽沟的FET一般还有制造成本的问题，由于制备带槽沟的FET所需的工艺条件并非所有的铸造工厂都有的，这就提高了制造成本。由于这样的缘故，将功率器件实施成横平式器件并采用平面门极也是合乎需要的。
已经披露了几种带有接地的基底和源极的横平式DMOS器件。横平式DMOS器件通常包括连接顶上的源极到P+基底之间的P+陷阱区(或者代之以槽沟)。由于陷阱或槽沟要占据空间，陷阱区域或槽沟使得单元横距增大。参见图1D所示G.Cao等人发表的器件的截面图(“Comparative Study of DriftRegion Designs in RF LDMOSFETs”，IEEE Electron Devices，August 2004，pp1296-1303)。以及Ishiwaka O等人的文章(“A 2.45 GHz power LdMOSFETwith reduced source inductance by V-groove connections”，International ElectronDevices Meeting.Technical Digest，Washington DC，USA，1-4 Dec.1985，pp.166-169)。Leong尝试了在P+和P-epi二层的界面上用埋层来减少横向扩散从而减小横距(US Patent 6372557，Apr.16，2002)。在D’Anna and Hébert(USPatent 5821144，Oct 13，1998)和Hébert(US Patent 5869875，Feb.9，1999，“Lateral Diffused MOS transistor with trench source contact”)两个专利中披露的器件中通过将源极陷阱或者槽沟设置在该结构的外周来减小单元横距。然而在这些文件中，图示器件的大多数采用同一种金属作源极/体(极)接点区域和门极屏蔽区域，而某些器件采用了第二种金属来作漏极和门极屏蔽区域。这些配置中的横向扩散增大了水平面上的漂移长度，一般会有大的单元横距。大的单元横距会使通态电阻大，通态电阻是电阻和器件面积的函数。大的单元横距引起器件尺寸变大，包的尺寸也变大，于是使得器件的成本增大。
因此，对于功率半导体器件的设计和制造技术，仍然需要提供新的器件配置和制备方法来形成功率器件，以便解决上面讨论的问题和局限性。
发明内容
本发明提供的一种具有槽沟的源体短路电极的、逆槽沟和源极接地的场效应晶体管结构，解决了背景技术中讨论的问题和局限。
因此本发明的一个方面提供一种新的和改进的源极接地的、逆槽沟的FET到重度掺杂的基底，例如，重掺杂N+基底上，它的源极在底上而漏极在顶上，通过采用槽沟体/源短路结构，并且不用P+陷阱，使得具有减小了的单元横距，从而实现了低的制造成本。低的制造成本的实现是由于低的有效管芯成本，加上在实施改进的器件配置时减小了单元横距。这就克服了上面讨论过的常规半导体功率器件遇到的无法收缩单元横距的技术困难和局限性。
特别是，本发明的一个方面提供一种新的和改进的源极接地的、逆槽沟的FET到重度掺杂的基底，例如，重掺杂N+基底上，它的源极在底上而漏极在顶上，它取消了源极焊线从而明显减小了源极电感，同时采用了集成的分布在器件中的体-源短路结构或者金属互连层从而最小化了特征的Rsp(通态电阻)。
本发明的另一方面提供一种新的和改进的源极接地的、逆槽沟的FET到重度掺杂的基底，例如，重掺杂N+基底上，它的源极在底上而漏极在顶上，它可适应于相当宽范围的高和低电压的应用。本发明所披露的这种半导体功率器件由于采用了分布式体极接点配置，减小了闭锁可能性，减小了氧化物门极造成的热载流子注入和峰值电压生成等问题，从而进一步实现了稳定可靠的工作。
本发明的另一方面提供一种新的和改进的源极接地的、逆槽沟的FET到重度掺杂的基底，例如，重掺杂N+基底上，它的源极在底上而漏极在顶上，它可提供带有可控漂移区长度的垂直电流沟道从而更能适应于减小横距的配置。它通过传导基底和在槽沟底部形成源极接点跟重度掺杂的N+基底直接接触来建立源极跟底面的连接。从而消除了对于采用深度阻抗陷阱或者槽沟接点的需求。
本发明的另一方面提供一种新的和改进的源极接地的、逆槽沟的FET到重度掺杂的基底，例如，重掺杂N+基底上，它的源极在底上而漏极在顶上，使得可以容易地配置成集成的高端(HS)和低端(LS)带槽沟的功率型MOSFET并集成在同一块半导体管芯上，来适合降压变流器的应用。作为HS FET的源极和LS FET的漏极的一个基底就建立了HS FET的源极和LSFET的漏极之间的直接接触。
简单叙述本发明的一个较佳实施例披露的一种半导体功率器件包括一个源极接地的、逆槽沟的FET到重掺杂N+基底上，它的源极在底上而漏极在顶上，它进一步包括多个槽沟来形成其中的门极。该半导体功率器件还包括分布在器件中作为埋置的导体的体-源接点，以便在重掺杂N+基底上将体区跟源区电连接起来。
此外本发明披露了一种制备应用于降压变流器的、集成的高端(HS)和低端(LS)带槽沟的功率型MOSFET的方法。此方法包括步骤：在同一块基底上同时制备一个逆槽沟的场效应晶体管(iT-FET)半导体器件起HS FET功能以及一个肖特基FET器件起LS FET功能，通过将iT-FET的源极形成到基底的底面上以直接电连接到肖特基FET的漏极。而且，在一个较佳实施例，同时制备一个iT-FET(逆槽沟的场效应晶体管)半导体器件以及一个肖特基FET器件的步骤还包括步骤：将该iT-FET半导体器件及肖特基FET器件集成到该半导体基底的同一管芯上，从而可以不用铅框而将降压变流器制备成单一管芯上的单个芯片。
本发明提供的具有槽沟的源体短路电极的、逆槽沟和源极接地的场效应晶体管结构，克服了常规半导体功率器件遇到的无法收缩单元横距的技术困难和局限性，最小化了特征的通态电阻，减小了闭锁可能性，减小了氧化物门极造成的热载流子注入和峰值电压生成等问题，从而进一步实现了稳定可靠的工作，消除了对于采用深度阻抗陷阱或者槽沟接点的需求。
附图说明
图1A和图1B分别图示通常的垂直式功率器件的配置的槽沟门极和平面门极两种实施方案的截面图；
图1C是垂直沟道LDMOS器件的截面图；
图1D是为RF(射频)用途的LDMOSFET(横向扩散金属氧化物半导体场效应晶体管)器件的漂移区设计的截面图；
图2是作为本发明一个实施例的、带有在重掺杂N+底层上形成的底源的、采用了作为分布在器件内的埋置导体来形成的体-源短路结构的、源极接地的逆槽沟FET器件的截面图；
图3是作为本发明另一个实施例的、带有在重掺杂N+底层上形成的底源的、采用了作为器件中的金属互连层来形成的体-源短路结构的、另一个源极接地的逆槽沟FET器件的截面图；
图4是采用槽沟(中的)源极接点来从顶面连接到底源的另一个源极接地的逆槽沟FET器件的截面图；
图5A和图5B分别是本发明所采用的以一个iT-FET器件起顶部FET器件功能及一个肖特基FET器件起底部器件功能的集成组合式降压变流器的截面图和电路图；
图6A至图6K为说明制造图5A所示应用于降压变流器的集成高端和低端的带槽沟的MOSFET的制备工艺步骤的系列截面图。
具体实施方式
参照图2的本发明的、具有底源顶漏(即源极在底部和漏极在顶部)的、源极接地的逆槽沟FET器件的截面图。该源极接地的逆槽沟FET器件是支撑在起底面源电极作用的N+基底105上。起P体区功能的P-外延生长层110支撑在基底105顶上。基底上配置了活性单元区，终止区通常设置在基底外围。该FET器件100有多条开口在基底顶面上的槽沟，其深度达外延生长层110的较低部。开在活性单元区上的槽沟充以门极多晶硅层以形成门极120，槽沟侧壁垫了一层槽沟壁氧化层125。在终止区的槽沟形成门极流道120′，槽沟门极120延伸到该处。N+区160设置在门极槽沟下并在N+基底和源区155之间延伸，后者包围在P掺杂区130内，而P掺杂区130则形成于围绕槽沟门极120的外延生长层内。在体区130顶部形成N联结区135来接触N漂移区145，后者被基底顶面附近的N+漏极接点区140所包围。在门极侧壁的上部形成较厚的门极氧化物层125′，来将槽沟门极120跟N漂移区145绝缘，以便减小Cgd(门漏电容)。在源区155和N联接区145之间由P区130形成了一个沟道。可代替地，门极槽沟可达到N+基底，区域155和160都不需形成了。
带槽沟垂直式FET器件还包括在活性单元区内埋置的传导体槽沟底上形成的体-源短路结构150。该体-源短路结构150采用传导芯杆150来形成，例如它可为一个Ti(钛)、Co(钴)、W的硅化物做的芯杆，被P掺杂区155和N+基底(或可选用传导芯杆150下的重掺杂N++区)所围绕，以形成一个高度传导、低电阻率的体-源短路结构。漏极金属170覆盖了活性单元区，而门极金属180形成在终止区。漏极金属和门极金属分别通过漏极接点开口和门极接点开口电接触漏极140和门极流道120′，这两个开口分别通过钝化层185、介电层175例如一个BPSG(硼磷硅玻璃)层、和绝缘层例如氧化层165，覆盖了FET器件的顶面。所示集成的体/源短路150是充填槽沟的埋置的传导体芯杆，用以形成分布到整个器件的体-源短路结构。这一配置的N漂移区留下不连接，因为没有到终止区的接点。由于基底处于源电位，就是NMOS(N沟道MOS电路)器件的接地电位，该浮动的N漂移区145可能工作在地电位。图标的该器件配置还有一个优点，在划线区锯断管芯产生的任何损伤都趋向于将该浮动N漂移区短路到接地的基底。此器件结构提供了一个包括将源极连接到基底底上的底源的垂直沟道。跟常规底源器件不同，本发明的底源器件并不用靠在源极区底下的P+陷阱来实现。反之，本发明的底源器件采用体/源短路结构来作为传导芯杆150。所以，本发明的器件结构节省了横向空间，避免了P+陷阱横向扩散。
参照图3所示源极接地逆槽沟FET器件的可替代实施例，它跟图2所示配置相似。唯一差别是该器件形成在N+基底上，而该基底上有N-Epi层。用离子注入来形成体层130。该体-源短路结构具有可选择的、形成在体-源短路槽沟侧壁的至少一部分上的P+掺杂区152，来改进跟传导芯杆150的体接触。
参照图4的作为本发明的一个可替代的实施方案的另一个iT-FET器件。图4的器件具有跟图3相同的结构，差别只在，在终止区有一个槽沟体-源短路芯杆连接150，将设置在基底底上的埋置源极105跟设置在半导体顶面上的源衬190连接起来。可替代地，这一体-源短路芯杆和源衬190可同时形成，采用相同材料沉积在漏极金属170上。
如图2和图3所示，终止区的槽沟填进门极多晶硅层120′，起门极流道的功能，作为设置在活性单元区上的槽沟门极120的连续延伸的一部分。门极金属1 80跟漏极金属170同时形成在器件顶面，然后造成它们作为漏极金属和门极金属的图形，而将源电极形成在基底的底面，作为接地电极。
按照上述器件配置，实现了低制造成本，因为用小的管芯可实现较低有效管芯成本，从而补偿了较高的制造成本。最重要的是，通过采用基底源极接触达到了低的源极电感，而通过实施分布在器件上的源-体短路结构使得源极电阻最小化。而且，如上所述器件的小的横距进一步减小了它在给定的工作电压下的特征的Rsp。这种器件配置便于兼容设计的缩放并适应于工作在相当宽范围的高和低电压下的器件。这种器件由于通过源-体短路结构的分布式体极接点配置，减小了闭锁可能性，减小了热载流子注入，和能够对付门极氧化物造成的峰值电压生成等问题，从而进一步实现了稳定可靠的工作。所以，这里就披露了一种逆槽沟的源极接地的FET器件，它允许垂直电流通过垂直沟道。用这种垂直沟道实施的漂移区的可控的漂移长度，使得可能制造小而可缩放的单元横距。由于设在槽沟底部的源极接点直接接触重度掺杂的基底，就减小了源极电阻。再也不需要如常规底源FET器件通常实施的深度阻抗的陷阱区或槽沟接点。
图5A是用于降压变流器的集成高端和低端槽沟功率MOSFET的截面图，图5B是降压变流器的电路图。图5A和图5B所示降压变流器集成了图2所示的iT-FET器件和专利申请No.11/056346和11/356944所披露的肖特基MOS器件。本申请参考并包括了这两个申请所披露的内容。任何别种肖特基二极管也可跟平面的和槽沟的FET或者iT-FET集成来做降压变流器应用。该iT-FET器件和肖特基FET支撑在共同的基底105上，后者起it-FET器件的源极和肖特基FET器件的漏极的功能。该肖特基FET器件包括被接近顶面的源区145′围绕的槽沟门极120′，又包围在体区110内。源区145′跟源极金属层170′电接触。该肖特基FET器件的槽沟门极120′被衬垫了门极氧化物层125′并且跟门极金属180′电连接。以往在电路板的水平或者在集成包的水平组装降压变流器都要用复杂的铅框，代之以本发明，可在一个半导体管芯上集成HS和LS MOSFET的降压变流器，因而减小了包的尺寸。由于采用了较为简单的铅框结构，包的成本也就降低了。
参照图6A至图6K的系列横截面图，来说明图5A所示的器件结构的制造工艺过程。如图6A，实施LTO(低温氧化物)沉积来形成氧化物层215，接着加上槽沟掩膜。然后进行氧化物蚀刻和槽沟蚀刻来形成支撑在基底205上的外延层210中的多条槽沟209，然后除去掩膜。然后加工半导体管芯的两个区域：高端iT-FET区和低端FET区。在图6B中，先进行牺牲氧化来形成牺牲氧化物层，接着施加底源光刻胶掩膜208来实施0度槽沟底源注入以便在高端iT-FET区形成多个底源区220，同时低端FET区是被光刻胶208挡住的。在图6C中，除去掩膜208，实施牺牲氧化物蚀刻，接着进行门极氧化工艺来形成门极氧化物层225，并扩散槽沟底源区220。在图6D中，沉积多晶硅层，掺杂，然后再蚀刻回去。氧化物蚀刻之后进行屏蔽氧化来形成氧化物层235。
如图6E，用体掩膜实施选择性体掺杂剂注入来形成体区240，接着进行体扩散工艺以便将体区240扩散进入外延层210。此步骤中也生成一个氧化物层。施加源/漏光刻胶掩膜237，先实施氧化物蚀刻，接着将N+掺杂剂注入来分别为iT-FET和肖特基器件形成漏区245-D和源区245-S。如图6F，除去源/漏掩膜237，施加LDD(横向漂移扩散)掩膜238，为it-FET器件注入该LDD区250。如图6G，施加接触槽沟光刻胶掩膜，进行氧化物蚀刻来开辟多条接触槽沟252，接着进行硅蚀刻和大倾角接触注入。
如图6H，进行硅蚀刻进一步蚀刻接触槽沟，施加底部接触槽沟光刻胶掩膜239，为iT-FET器件注入槽沟底部接触区255，以便接触底源区。图6I中，除去光刻胶掩膜239，接着进行退火工艺，然后沉积钨的硅化物260，或者用别的类型的金属例如钛或钴的硅化物做沉积，然后蚀刻回去。于是在iT-FET器件上形成多个底源接触芯杆260，而在肖特基器件上形成多个带槽沟的肖特基二极管260-S。如图6J，实施LTO沉积过程来形成顶部氧化物层265，接着做BPSG层沉积并且回流。施加接触掩膜来开辟多个接触开口，以使得iT-FET器件的门极和漏极245-D接触，也使得用肖特基器件以及带槽沟的肖特基二极管260-S的低端MOSFET中的门极和源极245-S接触。在图6K中，先沉积一个金属层，然后对iT-FET器件，形成其门极金属270-G和漏极金属270-D的图形，而将其源端形成在底面。对采用肖特基器件的低端MOSFET，进一步将其金属层形成门极金属280G和源极金属280-S的图形。
虽然现在采用了这些较佳的实施方案来描述本发明，应该理解这些公开不得解释为限制性的。本领域的技术人员在阅读了上面所公开的之后，无疑可能做出各种更动和修改。因此，后面的权利要求才应该解释成覆盖了落在本发明的真实精神和范围内的所有更动和修改。

Claims (21)

1.一种逆槽沟场效应晶体管半导体器件，包括半导体基底和设置在基底底上的源极和设置在基底顶上的漏极，其特征在于，所述逆槽沟场效应晶体管半导体器件还包括：
沿着槽沟中的门极设置在所述源极和所述漏极之间的垂直式电流传导沟道，该门极被开口在所述半导体基底上的槽沟的各侧壁上所设置的门极氧化物所衬垫；及由设置在埋置的传导体槽沟中的向下延伸的传导芯杆构成的源-体短路结构，用来将所述基底中的体区跟设置在所述基底的底面上的所述源极电学短路；
设置在所述基底的顶面附近的漂移区，它围绕着设置门极的半导体基底上的槽沟的上部，并且包围了所述漏极；
所述漂移区是一个N漂移区并且留下不连接，以构成浮动的N漂移区，且实质上具有源极电压，藉此，锯断逆槽沟场效应晶体管半导体器件的管芯产生的任何损伤都趋向于将所述浮动N漂移区短路到接地的基底。
2.如权利要求1的逆槽沟场效应晶体管半导体器件，其特征在于，所述垂直式电流传导沟道还包括设置在所述基底上的掺杂沟道区，它围绕着设置门极的半导体基底上的槽沟的底部，并且延伸到所述基底的底面上设置的所述源极。
3.如权利要求2的逆槽沟场效应晶体管半导体器件，其特征在于，还包括：设置在所述漂移区下面的联接区，它向下延伸到所述掺杂沟道区，用来将所述漂移区跟所述掺杂沟道区联接起来。
4.如权利要求2的逆槽沟场效应晶体管半导体器件，其特征在于，其中：所述源-体短路结构的所述传导芯杆还包括硅化钛传导芯杆，它从传导体槽沟的底部向下延伸到所述源极。
5.如权利要求2的逆槽沟场效应晶体管半导体器件，其特征在于，其中：所述源-体短路结构的所述传导芯杆还包括硅化钴传导芯杆，它从传导体槽沟的底部向下延伸到所述源极。
6.如权利要求2的逆槽沟场效应晶体管半导体器件，其特征在于，其中：所述源-体短路结构的所述传导芯杆还包括硅化钨传导芯杆，它从传导体槽沟的底部向下延伸到所述源极。
7.如权利要求1的逆槽沟场效应晶体管半导体器件，其特征在于，还包括：设置在所述槽沟中的门极的底面下的源极掺杂区，它被掺杂沟道区所围绕。
8.如权利要求1的逆槽沟场效应晶体管半导体器件，其特征在于，其中：所述槽沟中的门极还包括设置在所述各侧壁的上部的厚氧化物垫片层，用来将所述槽沟中的门极跟所述基底的顶面附近设置的所述漏极绝缘，以进一步减小门-漏耦合电容。
9.如权利要求1的逆槽沟场效应晶体管半导体器件，其特征在于，其中：所述源极还包括设置在所述基底的底部的N+掺杂区。
10.如权利要求9的逆槽沟场效应晶体管半导体器件，其特征在于，其中：所述漏极还包括设置在所述基底的顶部的N+掺杂区。
11.如权利要求9的逆槽沟场效应晶体管半导体器件，其特征在于，其中：掺杂沟道区包括设置在所述基底内的P掺杂区，它围绕着设置门极的半导体基底上的槽沟的底部，并且延伸到所述源极。
12.如权利要求9的逆槽沟场效应晶体管半导体器件，其特征在于，其中：基底的底部还包括一个N+掺杂接触增进带，来增进所述源-体短路结构跟所述源极的电接触。
13.如权利要求1的逆槽沟场效应晶体管半导体器件，其特征在于，还包括：设置在半导体基底外围的终止区包括跟所述槽沟中的门极电连接的槽沟门极流道，用来跟设置在所述终止区内的门极金属电连接。
14.如权利要求1的逆槽沟场效应晶体管半导体器件，其特征在于，所述逆槽沟场效应晶体管半导体器件为金属氧化物半导体场效应晶体管器件。
15.如权利要求1的逆槽沟场效应晶体管半导体器件，其特征在于，所述逆槽沟场效应晶体管半导体器件为功能增进模式的金属氧化物半导体场效应晶体管器件。
16.如权利要求1的逆槽沟场效应晶体管半导体器件，其特征在于，其中：所述逆槽沟场效应晶体管半导体器件为耗尽模式的金属氧化物半导体场效应晶体管器件。
17.如权利要求1的逆槽沟场效应晶体管半导体器件，其特征在于，其中：
所述逆槽沟场效应晶体管半导体器件还包括：设置在开口于所述半导体基底顶面的传导体槽沟中的、向下延伸的传导芯杆构成的源-体短路结构，用来将所述基底中的体区跟设置在所述基底的所述底面上的所述源极电学短路，所述源-体短路结构电连接到设置在半导体顶部的顶面上的源电极。
18.如权利要求1的逆槽沟场效应晶体管半导体器件，其特征在于，其中：所述源-体短路结构由设置在所述埋置的传导体槽沟中的所述传导芯杆所构成，该传导体槽沟设置在所述半导体基底上的活性单元区，用来将所述基底中的体区跟设置在所述基底的所述底面上的所述源极电学短路。
19.如权利要求1的逆槽沟场效应晶体管半导体器件，其特征在于，还包括：多个所述源-体短路结构，它们形成为设置在多个埋置的传导体槽沟中的埋置的传导芯杆，这些传导体槽沟分布在所述逆槽沟场效应晶体管半导体器件上。
20.如权利要求3的逆槽沟场效应晶体管半导体器件，其特征在于，其中包括：所述体区形成在所述半导体基底里的N外延层内，作为一个注入的体区。
21.如权利要求3的逆槽沟场效应晶体管半导体器件，其特征在于，其中包括：所述源-体短路结构由从埋置的传导体槽沟的底面向下延伸的传导芯杆所构成，该传导体槽沟设置在所述半导体基底的外围的终止区，用来将所述基底中的体区跟设置在所述基底的底面上的所述源极电学短路，并且进一步将设置在所述基底的底面上的所述源极跟设置在所述半导体基底的顶面上的一个源极垫片电学短路。
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