CN101136394A - Multiple chip semi-conductor packaging structure and encapsulation method - Google Patents
Multiple chip semi-conductor packaging structure and encapsulation method Download PDFInfo
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- CN101136394A CN101136394A CNA2006100306262A CN200610030626A CN101136394A CN 101136394 A CN101136394 A CN 101136394A CN A2006100306262 A CNA2006100306262 A CN A2006100306262A CN 200610030626 A CN200610030626 A CN 200610030626A CN 101136394 A CN101136394 A CN 101136394A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
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Abstract
This invention relates to a semiconductor packaging structure of multiple chips and a method, in which, the structure includes several flip-chips and a lead frame containing a die pad and a lead, and a middle pad connected with the flip-chips and an edge pad connecting the lead and the middle pad are set on the die pad, and a related packaging method for multi-chip semiconductor includes: providing several flip-chips and a lead frame with a die pad and a lead, and middle and edge pads are set on the die pad characterizing in also including the following steps: connecting the middle pad of the die pad with the flip-chips electrically, connecting the middle pad with the edge pad electrically and connecting the edge pad with the lead.
Description
Technical field
The present invention relates to multi-chip semiconductor package structure and method for packing, relate in particular to a plurality of flip-chips by interconnective semiconductor package of lead frame and method for packing.
Background technology
Along with the demand of miniaturization, lightweight and the multifunction of electronic component day by day increases, cause semiconductor packages density constantly to increase, thereby shared area must dwindle package dimension and encapsulation the time.Develop in the technology that for satisfying above-mentioned demand, the multi-chip semiconductor encapsulation technology has far-reaching contribution for whole cost, usefulness and the reliability of packaged chip.
Yet in the multi-chip semiconductor encapsulation process, the method for attachment of chip chamber also has significant effects for the size and the performance of semiconductor packages.According to the method that connects, semiconductor packages is divided into wire bonds type or flip-chip bonding type.The bonding wire of conduction is adopted in the encapsulation of wire bonds type, the electrode of semiconductor chip is connected to the lead-in wire of lead frame; And the conductive solder projection be placed on the semiconductor core plate electrode is adopted in the encapsulation of flip-chip variety, semiconductor chip is connected to lead frame or semiconductor chip is directly connected to the splicing ear of circuit board.The encapsulation of flip-chip bonding type has the electrical connection path shorter than wire bonds type package, thereby excellent thermal characteristics and electrical characteristics and littler package size is provided.
Prior art multi-chip semiconductor encapsulation making method, shown in Figure 1A, lead frame comprises die pad 141 and a plurality of lead-in wire 142.The pad 106 of the first positive cartridge chip 100 substrate opposite faces is connected with the lead-in wire 142 of lead frame by bonding line 146; Die pad 141 first surfaces of first positive cartridge chip 100 basal surfaces and lead frame are bonding.The pad 126 of the second positive cartridge chip 120 substrate opposite faces is connected with the lead-in wire 142 of lead frame by bonding line 146; Die pad 141 second surfaces of the basal surface of the first positive cartridge chip 120 and lead frame are bonding.
Shown in Figure 1B, first positive cartridge chip 100 basal surfaces are assemblied in die pad 141 first surfaces by adhesive; By bonding line 146 pad 106 of the first positive cartridge chip 100 substrate opposite faces and the lead-in wire 142 of lead frame are connected one to one again, for example wherein pad 1 is connected with lead-in wire b, pad 8 is connected with lead-in wire c, and pad 9 is connected with lead-in wire e, and pad 16 is connected with lead-in wire g.
Shown in Fig. 1 C, the second positive cartridge chip 120 is assemblied in die pad 141 second surfaces by adhesive; By bonding line 146 pad 126 of second positive cartridge chip 120 upper surfaces and the lead-in wire 142 of lead frame are connected one to one again, for example wherein pad 1 ' is connected with lead-in wire c with lead-in wire b connection pads 8 ', and pad 9 ' is connected with lead-in wire g with lead-in wire e connection pads 16 '.
Wherein, 126 one-tenth mirror image symmetries of pad of the pad 106 of the first positive cartridge chip 100 substrate opposite faces and the second positive cartridge chip 120 substrate opposite faces, be connected to by bonding line on the lead-in wire of same lead frame.
The existing semiconductor package fabrication method such as the patent No. are described by the technical scheme of the U.S. Patent Publication of US 6674173.
Though, with the multi-chip semiconductor method for packing area of encapsulation has been reduced, closeness and function all increase.But because a plurality of chips are by bonding line pad on the chip to be connected with the lead-in wire of lead frame respectively, cause connection times frequent, cause lead inductance higher, and then limit the highest operation frequency and the speed of this kind encapsulation.
Summary of the invention
The problem that the present invention solves provides a kind of multi-chip semiconductor package structure and method for packing, prevent because a plurality of chips are by bonding line pad on the chip to be connected with the lead-in wire of lead frame respectively, cause connection times frequent, cause lead inductance higher, and then limit the highest operation frequency and the speed of this kind encapsulation.
For addressing the above problem, the invention provides a kind of semiconductor package, comprise: several flip-chips and lead frame, described lead frame comprises die pad and lead-in wire, middle pad and edge pad are arranged on the die pad, middle pad is electrically connected with flip-chip, and the edge pad is used for lead-in wire and middle pad is electrically connected.
Described flip-chip comprises mother chip and sub-chip, and mother chip and sub-chip distribution are in the lead frame both sides.Lead frame is a single layer structure, and middle pad and edge pad on the die pad run through die pad thickness.
Be distributed with pad on mother chip and the sub-chip, the pad on the sub-chip be electrically connected with the middle pad of die pad, the pad on the mother chip is electrically connected with the middle pad of die pad with solder projection with solder projection.
Pad on mother chip and the sub-chip is divided into function and drives pad and not function driving pad.Function drives that function driving pad is the mirror image antisymmetry on pad and the mother chip on the sub-chip, be connected on the different middle pad of die pad, not function drives that not function driving pad is the mirror image symmetry on pad and the mother chip on the sub-chip, connects one to one on the middle pad of die pad.
For addressing the above problem, a kind of multi-chip semiconductor method for packing of the present invention, a kind of multi-chip semiconductor method for packing, several flip-chips and lead frame at first are provided, described lead frame comprises die pad and lead-in wire, middle pad and edge pad are arranged on the die pad, it is characterized in that, also comprise the following steps: the middle pad and the flip-chip of die pad are electrically connected; The middle pad and the edge pad of die pad are electrically connected; The edge pad and the lead-in wire of die pad are electrically connected.
Described flip-chip comprises mother chip and sub-chip, and mother chip and sub-chip distribution are in the lead frame both sides, and lead frame is a single layer structure, and middle pad and edge pad on the die pad run through die pad thickness.
Be distributed with pad on mother chip and the sub-chip, the pad on the sub-chip be electrically connected with the middle pad of die pad, the pad on the mother chip is electrically connected with the middle pad of die pad with solder projection with solder projection.
Pad on mother chip and the sub-chip is divided into function and drives pad and not function driving pad.Not function drives that not function driving pad is the mirror image symmetry on pad and the mother chip on the sub-chip, connect one to one on the middle pad of die pad, function drives that function driving pad is the mirror image antisymmetry on pad and the mother chip on the sub-chip, is connected on the different middle pad of die pad.
Connect the edge pad of die pad and the lead-in wire of lead frame with bonding line, the material of bonding line is gold, copper, aluminium or albronze.Be electrically connected with the edge pad with the middle pad of connecting line with die pad, the material of connecting line is copper, iron, nickel, iron-nickel alloy or corronil.
Compared with prior art, the present invention has the following advantages: the not function of mirror image symmetry on upside-down mounting mother chip and the sub-chip of upside-down mounting is driven pad connect one to one to the middle pad of the die pad of lead frame, connect edge pad and middle pad on the die pad then, again the edge pad on the die pad is connected with the lead-in wire of lead frame.Reduced the number of times of line like this, system's electrical property improves.
Description of drawings
Figure 1A to Fig. 1 C is a prior art multi-chip semiconductor method for packing.
Fig. 2 A to Fig. 2 B comprises a plurality of chip schematic diagrames on the wafer of the present invention.
Fig. 3 A to Fig. 3 B is the chip schematic diagram that the present invention has pad.
Fig. 4 A to Fig. 4 B is a multi-chip semiconductor encapsulation schematic diagram of the present invention.
Fig. 5 is a line schematic diagram on the die pad of lead frame of the present invention.
Fig. 6 is the edge pad and the lead-in wire connection diagram of the die pad of lead frame of the present invention.
Embodiment
Along with the demand of miniaturization, lightweight and the multifunction of electronic component day by day increases, cause semiconductor packages density constantly to increase, at present, the area of encapsulation is reduced, closeness and function raising with the multi-chip semiconductor method for packing.But because a plurality of chips are to be connected on the lead-in wire of lead frame by bonding line respectively, cause connection times frequent, cause lead inductance higher, and then limit the highest operation frequency and the speed of this kind encapsulation.Connecting line construction when the present invention encapsulates by changing multi-chip semiconductor reduces the semiconductor packages area, when the closeness of semiconductor packages improves, has reduced the number of times of line, and system's electrical property improves.Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Multi-chip semiconductor package structure comprises: several flip-chips and lead frame, described lead frame comprises die pad and lead-in wire, middle pad and edge pad are arranged on the die pad, be electrically connected between middle pad and flip-chip, the edge pad is used for lead-in wire and the electrical connection of middle pad.
Fig. 4 A to Fig. 4 B is a multi-chip semiconductor encapsulation schematic diagram of the present invention.Shown in Fig. 4 A and Fig. 4 B, flip-chip comprises mother chip 41 and sub-chip 40, mother chip 41 and sub-chip 40 are distributed in lead frame 42 both sides, and lead frame 42 is a single layer structure, and middle pad 422 423 426 and edge pad 424 on the die pad 420 run through die pad; Be distributed with pad on the sub-chip 40, pad is divided into not function and drives pad 401 and function driving pad 402, be distributed with pad on the mother chip 41, pad is divided into not function and drives pad 411 and function driving pad 412, not function drives on pad 401 and the mother chip 41 not function to drive pad 411 is the mirror image symmetry on its neutron chip 40, by solder projection 413 not function on the mother chip 41 being driven pad 411 is electrically connected with middle pad 422 in the die pad 420, function drives on pad 402 and the mother chip function to drive pad 412 be the mirror image antisymmetry on the sub-chip 40, and the function on the sub-chip 40 drives pad 402 and passes through solder projection 404 and be electrically connected with the middle pad 423 of die pad 420; On the die pad 420 connecting line is arranged, being electrically connected between pad 422 423 426 and the edge pad 424 in the middle of being used for; Bonding line 425 is arranged on the lead frame 42, the edge pad 424 of die pad 420 is electrically connected with lead-in wire 421.
Except embodiment, die pad 420 can also be a sandwich construction, and middle pad and edge pad are arranged on the die pad of sandwich construction, and through hole is arranged in the die pad of sandwich construction, fill up metallics in the described through hole in order to be communicated with the middle pad of sandwich construction die pad surface.
In the present embodiment, the material that reaches pad in the die pad 420 on the mother chip 41, on the sub-chip 40 is a metal or alloy, concrete example such as copper, aluminium, or albronze.
In the present embodiment, the material that solder projection 403 413 adopts is an alloy, and concrete example is leypewter in this way, sn-ag alloy, or SAC alloy.
The material of the middle pad 422 423 426 of connection die pad 420 and the connecting line of edge pad 424 is copper, iron, nickel, iron-nickel alloy or corronil.
In the present embodiment, what connect the edge pad 424 of die pad 420 and the lead-in wire 421 in the lead frame 42 is bonding line 425, and the material of bonding line 425 is gold, copper, aluminium or albronze.
The multi-chip semiconductor method for packing, several flip-chips and lead frame at first are provided, and described lead frame comprises die pad and lead-in wire, and middle pad and edge pad are arranged on the die pad, it is characterized in that, also comprise the following steps: the middle pad and the flip-chip of die pad are electrically connected; The middle pad and the edge pad of die pad are electrically connected; The edge pad and the lead-in wire of die pad are electrically connected.
Continue with reference to figure 4A to Fig. 4 B, shown in Fig. 4 A, the driving of the not function on the sub-chip 40 pad 401 is electrically connected with middle pad 422 in the die pad 420 with solder projection 403; With solder projection 413 not function on the mother chip 41 being driven pad 411 is electrically connected with middle pad 422 in the die pad 420; Function on the sub-chip 40 drives pad 402 and is electrically connected with the middle pad 423 of die pad 420 by solder projection 404; With middle pad 422 423 and the edge pad 424 on the connecting line connection die pad 420; Then, the edge pad 424 on the die pad 420 is electrically connected with the lead-in wire 421 of lead frame 42 by bonding line 425.
Shown in Fig. 4 B, with solder projection 403 not function on the sub-chip 40 is driven pad 401 and be electrically connected with middle pad 421 on the die pad 420; With solder projection 413 not function on the mother chip being driven pad 411 is electrically connected with middle pad 422 in the die pad 420; With solder projection 414 function on the mother chip 41 being driven pad 412 is electrically connected with middle pad 426 in the die pad 420; With middle pad 422 426 and the edge pad 424 on the connecting line connection die pad 420; Then, the edge pad 424 on the die pad 42 is electrically connected with the lead-in wire 421 of lead frame 42 by bonding line 425.
In the present embodiment, adopt a upside-down mounting mother chip and sub-chip of upside-down mounting to lay respectively at the both sides of lead frame, except that embodiment, also can there be two upside-down mounting mother chips and the sub-chip of upside-down mounting to carry out the encapsulation of multicore sheet, also can be that two sub-chips of upside-down mounting and a upside-down mounting mother chip carry out the encapsulation of multicore sheet, even can have sub-chip of more upside-down mounting and upside-down mounting mother chip to carry out the encapsulation of multicore sheet.
Fig. 2 A to Fig. 2 B comprises a plurality of chip schematic diagrames on the wafer of the present invention.Shown in Fig. 2 A, a plurality of mother chips 200 are arranged on the wafer 20, be furnished with complicated circuit on the mother chip 200, comprise and mother chip 200 surface pads circuit in succession.Shown in Fig. 2 B, a plurality of sub-chips 220 are arranged on the wafer 22, be furnished with complicated circuit on the sub-chip 220, comprise the circuit that is connected with sub-chip 220 surface pads.
Fig. 3 A to Fig. 3 B is the chip schematic diagram that the present invention has pad.As shown in Figure 3A, a plurality of pads 201 are arranged on the mother chip 200, the pad on the mother chip 200 201 is carried out label, be designated as 21 22 23 2,425 26 27 28 29 30 31 32 33 34 35 36 37.Mother chip 200 comprises the circuit of a plurality of complexity, and the circuit that is connected with pad 201 on the mother chip 200 is wherein arranged.Mother chip 200 upper surface labels are near 21 the pad a pair of bit flag 203 to be arranged, and contraposition sign 203 is the usefulness that is used in aligned position when pad is connected on the die pad of mother chip 200 and lead frame.
Shown in Fig. 3 B, on the sub-chip 220 a plurality of pads 201 ' are arranged, the pad on the sub-chip 220 201 ' is carried out label, be designated as 21 ' 22 ' 23 ' 24 ' 25 ' 26 ' 27 ' 28 ' 29 ' 30 ' 31 ' 32 ' 33 ' 34 ' 35 ' 36 ' 37 '.Sub-chip 220 comprises the circuit of a plurality of complexity, and the circuit that is connected with pad 201 ' on the sub-chip 220 is wherein arranged.Sub-chip 220 upper surface labels are near 21 ' the pad a pair of bit flag 203 ' to be arranged.Contraposition sign 203 ' is the usefulness that is used in aligned position when pad is connected on the die of chip and lead frame.
In the present embodiment, on the mother chip 200 label be 21 22 23 24 25 26 27 28 29 30 31 32 3,334 35 36 pad 201 with sub-chip 220 on label be that 21 ' 22 ' 23 ' 24 ' 25 ' 26 ' 27 ' 28 ' 29 ' 30 ' 31 ' 32 ' 33 ' 34 ' 35 ' 36 ' pad 201 ' is not function driving pad, when mother chip 200 and sub-chip 220 are installed on the lead frame, on the mother chip 200 label be 21 22 2,324 25 26 27 28 29 30 31 32 33 34 35 36 pads 201 with sub-chip 220 on label be that 21 ' 22 ' 23 ' 24 ' 25 ' 26 ' 27 ' 28 ' 29 ' 30 ' 31 ' 32 ' 33 ' 34 ' 35 ' 36 ' pad 201 ' becomes the mirror image symmetry.On the mother chip 200 label be 37 pad 201 with sub-chip 220 on label be that 37 ' pad 201 ' has been the effect of function driving, and be the mirror image antisymmetry,
Fig. 5 is a line schematic diagram on the die pad of lead frame of the present invention.As shown in Figure 5, middle pad 422 labels with on the die pad 420 of lead frame are designated as 21 " 22 " 35 " 36 ".By solder projection the not function on the middle pad in the die pad 420 422 and Fig. 3 B neutron chip 220 being driven pad connects one to one, label is that to drive pad be 21 by label on solder projection and the die pad 420 for 21 ' not function on for example sub-chip 220 " middle pad 422 be connected; label be 22 ' not function driving pad by label on solder projection and the die pad 420 is 22 on the sub-chip 220 " middle pad 422 be connected, label is that to drive pad be 35 by label on solder projection and the die pad 420 for 35 ' not function on the sub-chip 220 " middle pad 422 be connected, label be 36 ' not function driving pad by label on solder projection and the die pad 420 is 36 on the sub-chip 220 " middle pad 422 be connected.In addition, the label that plays the function driving action on the sub-chip 220 be 37 ' pad with die pad 420 on label be 37 " middle pad 423 be connected.
By solder projection the middle pad 422 that the not function on the mother chip 200 among Fig. 3 A drives on pad and the die pad 420 is connected one to one, for example label is that to drive pad be 21 by label on solder projection and the die pad 420 for 21 not function on the mother chip 200 " middle pad 422 be connected; label be 22 not function driving pad by label on solder projection and the die pad 420 is 22 on the mother chip 200 " middle pad 422 be connected, label is that to drive pad be 35 by label on solder projection and the die pad 420 for 35 not function on the mother chip 200 " middle pad 422 be connected, label be 36 not function driving pad by label on solder projection and the die pad 420 is 36 on the mother chip 220 " middle pad 422 be connected.In addition, to play function driving action label on the mother chip 200 be 37 pad with the die pad 420 of lead frame on label be 37 " ' middle pad 426 be connected.
Edge pad 422 labels with on the die pad 420 of lead frame are designated as 51 52 55 64 67 68.Then, is 21 with connecting line with label on the die pad 420 " middle pad 422 and die pad 420 on label be that 51 edge pad 424 is connected; be 22 with connecting line with label successively " middle pad 422 and label be that 52 edge pad 424 is connected, is 35 with connecting line with label " middle pad 422 and label be that 67 edge pad 424 is connected, be 36 with label " middle pad 422 and label be that 68 edge pad 424 is connected.
Is 37 with connecting line with label on the die pad 420 " middle pad 423 be that 55 edge pads 424 are connected with label; Is 37 with connecting line with label on the die pad 420 " ' middle pad 426 and label be that 64 edge pad 424 is connected.
Fig. 6 is the edge pad and the lead-in wire connection diagram of the die pad of lead frame of the present invention.As shown in Figure 6, lead-in wire 421 labels to lead frame 42 are designated as 51 ' 52 ' 55 ' 64 ' 67 ', 68 '.Edge pad on the die pad 424 lead-in wire 421 with lead frame is connected one to one, for example with bonding line be 51 edge pad 424 with label on the die pad with lead frame 42 on label be that 51 ' lead-in wire 421 is connected; Be 52 edge pad 424 with bonding line with label on the die pad with lead frame 42 in label be that 52 ' lead-in wire 421 is connected; Be 55 edge pad 424 with bonding line with label on the die pad with lead frame 42 on label be that 55 ' lead-in wire 421 is connected; Be 64 edge pad 424 with bonding line with label on the die pad with lead frame 42 on label be that 64 ' lead-in wire 421 is connected; Be 67 edge pad 424 with bonding line with label on the die pad with lead frame 42 in label be that 67 ' lead-in wire 421 is connected; Be 68 edge pad 424 with bonding line with label on the die pad with lead frame 42 in label be that 68 ' lead-in wire 421 is connected.
The present invention adopts flip-chip, chip is connected on the die pad of lead frame, and then is connected with lead-in wire by die pad, the semiconductor packages area is reduced, when the closeness of semiconductor packages improves, but also reduced the number of times of line, system's electrical property improves.
Though the present invention with preferred embodiment openly as above; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (16)
1. multi-chip semiconductor package structure, comprise: several flip-chips and lead frame, described lead frame comprises die pad and lead-in wire, and middle pad and edge pad are arranged on the die pad, middle pad is electrically connected with flip-chip, and the edge pad is used for lead-in wire and middle pad is electrically connected.
2. multi-chip semiconductor package structure according to claim 1 is characterized in that: described flip-chip comprises mother chip and sub-chip, and mother chip and sub-chip distribution are in the lead frame both sides.
3. multi-chip semiconductor package structure according to claim 2 is characterized in that: described lead frame is a single layer structure, and middle pad and edge pad on the die pad run through die pad thickness.
4. multi-chip semiconductor package structure according to claim 3, it is characterized in that: be distributed with pad on mother chip and the sub-chip, with solder projection the pad on the sub-chip is electrically connected with the middle pad of die pad, the pad on the mother chip is electrically connected with the middle pad of die pad with solder projection.
5. multi-chip semiconductor package structure according to claim 4 is characterized in that: the pad on mother chip and the sub-chip is divided into function and drives pad and not function driving pad.
6. multi-chip semiconductor package structure according to claim 5 is characterized in that: function drives that function driving pad is the mirror image antisymmetry on pad and the mother chip on the sub-chip, is connected on the different middle pad of die pad.
7. multi-chip semiconductor package structure according to claim 6 is characterized in that: not function drives that not function driving pad is the mirror image symmetry on pad and the mother chip on the sub-chip, connects one to one on the middle pad of die pad.
8. a multi-chip semiconductor method for packing at first provides several flip-chips and lead frame, and described lead frame comprises die pad and lead-in wire, and middle pad and edge pad are arranged on the die pad, it is characterized in that, also comprises the following steps:
The middle pad and the flip-chip of die pad are electrically connected;
The middle pad and the edge pad of die pad are electrically connected;
The edge pad and the lead-in wire of die pad are electrically connected.
9. multi-chip semiconductor method for packing according to claim 8 is characterized in that: described flip-chip comprises mother chip and sub-chip, and mother chip and sub-chip distribution are in the lead frame both sides.
10. multi-chip semiconductor method for packing according to claim 9 is characterized in that: described lead frame is a single layer structure, and middle pad and edge pad on the die pad run through die pad thickness.
11. multi-chip semiconductor method for packing according to claim 10, it is characterized in that: be distributed with pad on mother chip and the sub-chip, with solder projection the pad on the sub-chip is electrically connected with the middle pad of die pad, the pad on the mother chip is electrically connected with the middle pad of die pad with solder projection.
12. multi-chip semiconductor method for packing according to claim 11 is characterized in that: the pad on mother chip and the sub-chip is divided into function and drives pad and not function driving pad.
13. multi-chip semiconductor method for packing according to claim 12 is characterized in that: function drives that function driving pad is the mirror image antisymmetry on pad and the mother chip on the sub-chip, is connected on the different middle pad of die pad.
14. multi-chip semiconductor method for packing according to claim 13 is characterized in that: not function drives that not function driving pad is the mirror image symmetry on pad and the mother chip on the sub-chip, connects one to one on the middle pad of die pad.
15. multi-chip semiconductor method for packing according to claim 14 is characterized in that: be electrically connected with the edge pad with the middle pad of connecting line with die pad, the material of connecting line is copper, iron, nickel, iron-nickel alloy or corronil.
16. multi-chip semiconductor method for packing according to claim 15 is characterized in that: connect the edge pad of die pad and the lead-in wire of lead frame with bonding line, the material of bonding line is gold, copper, aluminium or albronze.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2006100306262A CN100468728C (en) | 2006-08-31 | 2006-08-31 | Multiple chip semi-conductor packaging structure and encapsulation method |
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| CNB2006100306262A CN100468728C (en) | 2006-08-31 | 2006-08-31 | Multiple chip semi-conductor packaging structure and encapsulation method |
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| CN100468728C CN100468728C (en) | 2009-03-11 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102194800A (en) * | 2010-02-26 | 2011-09-21 | 海力士半导体有限公司 | Multi-chip package with improved signal transmission |
| CN102332440A (en) * | 2010-07-12 | 2012-01-25 | 无锡华润安盛科技有限公司 | Inverted lead frame and packaging structure thereof |
| CN111106088A (en) * | 2018-10-25 | 2020-05-05 | 英飞凌科技股份有限公司 | Semiconductor package with lead frame interconnect structure |
| CN113053847A (en) * | 2019-12-26 | 2021-06-29 | 珠海格力电器股份有限公司 | Chip packaging structure and preparation method thereof |
-
2006
- 2006-08-31 CN CNB2006100306262A patent/CN100468728C/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102194800A (en) * | 2010-02-26 | 2011-09-21 | 海力士半导体有限公司 | Multi-chip package with improved signal transmission |
| CN102332440A (en) * | 2010-07-12 | 2012-01-25 | 无锡华润安盛科技有限公司 | Inverted lead frame and packaging structure thereof |
| CN111106088A (en) * | 2018-10-25 | 2020-05-05 | 英飞凌科技股份有限公司 | Semiconductor package with lead frame interconnect structure |
| US11444011B2 (en) | 2018-10-25 | 2022-09-13 | Infineon Technologies Ag | Semiconductor package with leadframe interconnection structure |
| CN113053847A (en) * | 2019-12-26 | 2021-06-29 | 珠海格力电器股份有限公司 | Chip packaging structure and preparation method thereof |
| CN113053847B (en) * | 2019-12-26 | 2023-06-20 | 珠海格力电器股份有限公司 | Chip packaging structure and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100468728C (en) | 2009-03-11 |
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