CN101131941B - Semiconductor chip packaging process and its structure - Google Patents
Semiconductor chip packaging process and its structure Download PDFInfo
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- CN101131941B CN101131941B CN2007101515823A CN200710151582A CN101131941B CN 101131941 B CN101131941 B CN 101131941B CN 2007101515823 A CN2007101515823 A CN 2007101515823A CN 200710151582 A CN200710151582 A CN 200710151582A CN 101131941 B CN101131941 B CN 101131941B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
This invention is about a packaging manufacturing process of semiconductor chip and its structure, and its manufacturing process includes: provide a substrate containing an image sensor chip and insulation colloid, and its image sensor chips contains solder pad and active region; cover a transparent insulator on the active region; form an insulating layer on the surface of the substrate; open a number of openings to expose welding pad; form a number of cross-cutting holes on the outer surface of the image sensor chips, and these holes run through insulation layer and insulation colloid; form a metal layer on the surface of the insulation layer, opening, solder pad surface, pass through holes and the basement, and extend the solder pad to the bottom surface of the basement; pattern the bare metal layers to expose the top region of transparent insulation layer and remove part of the metal layer on the bottom surface of the substrate; cut and form packaging structure containing a single image sensor chip.
Description
Technical field
The present invention relates to a kind of semiconductor chip package procedure and structure thereof, particularly relate to a kind of manufacture method and structure thereof that is suitable for the bumpless encapsulating structure of Image Sensor.
Background technology
See also the U.S. Patent bulletin the 6th that Figure 1A illustrates, 040,235 discloses a kind of semiconductor die package method, and this patented technology is to cover an insulation material 120 at a wafer 110 active surfaces, as glass, its contact from the wafer active surface extends to the back side of wafer.Wafer is after cutting into a plurality of chips, and the contact of each chip is to extend to package surface by metallic circuit 130.Yet if the chip defective products in each wafer is too much, it all is defective productss that the half chip is for example arranged in the wafer, unclear with the obvious benefit of this kind packaged type.
In addition, see also the U.S. Patent bulletin that Figure 1B illustrates and disclose a kind of semiconductor die package method the 6th, 271, No. 469, it then forms an insulating barrier 160 again with the substrate of colloid 140 as carries chips 150, forms metallic circuit 170 on insulating barrier.Program can form the encapsulating structure of bumpless whereby.Yet this processing procedure and structure are because of forming the opening of hollow out in semiconductor chip surface, so and be not suitable for the semiconductor chip that encapsulation Image Sensor or temperature, moisture sensing element etc. must act on the active surface ingress of air, so its application is limited.
Summary of the invention
The objective of the invention is to, overcome the defective that prior art exists, and provide a kind of new semiconductor chip package procedure and structure thereof, technical problem to be solved is to make its encapsulating structure have the contact that is extended to chip back by the chip active surface, and have the required hatch frame of image sensing chip in the active area of chip active surface, be very suitable for practicality.
The object of the invention to solve the technical problems realizes by the following technical solutions.A kind of semiconductor chip package procedure according to the present invention's proposition, it comprises the following step: a substrate is provided, this substrate has a upper surface and a lower surface, and this substrate is an insulation colloid that comprises a plurality of image sensing chips and be surrounded on those image sensing chips, each those image sensing chip has an active surface that flushes with this upper surface of substrate and a back side that flushes with this substrate lower surface, have a plurality of weld pads on this active surface, and an active area; Cover a transparent insulator on the active area of each those image sensing chip; Form an insulating barrier in this upper surface of substrate; Form plurality of openings on this insulating barrier, and those openings are to be positioned at those image sensing chip weld pad places, so that those weld pads are exposed; Form a plurality of through holes in those image sensing chip outsides, and run through the insulation colloid of this insulating barrier and this substrate; Form a metal level on this surface of insulating layer, those open surfaces, those weld pad surfaces, those through hole surfaces and this substrate lower surface, to extend those weld pads to this substrate lower surface; This metal level of patterning, with exposed this transparent insulator top area, and the subregion of removing this metal level on this substrate lower surface, and form a plurality of contacts; And impose cutting technique, in order to form a plurality of encapsulating structures that comprise single image sensor chip.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid semiconductor chip package procedure, wherein after this metal level step of this patterning and before imposing the cutting technique step, more comprise the following step: form a protective layer and a lower protective layer on, protective layer is located at this upper surface of substrate on this, and this lower protective layer is located at this substrate lower surface; Form plurality of openings in a plurality of ball positions of planting of this lower protective layer, reach the relative position at this transparent insulator top of protective layer on this, to expose this transparent insulator top surface; And form a plurality of soldered balls in those contacts, so that forming with this metal level, those soldered balls are connected.
Aforesaid semiconductor chip package procedure, a plurality of through holes of wherein said formation more comprised formation one stress-buffer layer in this substrate lower surface before the step in those image sensing chip outsides.
Aforesaid semiconductor chip package procedure, wherein those through holes more comprise and run through this stress-buffer layer.
Aforesaid semiconductor chip package procedure, the step of wherein said covering one transparent insulator more comprise in advance at this transparent insulator top surface and paste a protection glue, and form in the step of a plurality of soldered balls at this, more comprise and remove this protection glue.
Aforesaid semiconductor chip package procedure, the step of wherein said covering one transparent insulator are to utilize a transparent colloid that this transparent insulator directly is covered on each those image sensing chip active area.
Aforesaid semiconductor chip package procedure, the step of wherein said covering one transparent insulator is on each those image sensing chip active area, utilize a grid (spacer) to prop up this transparent insulator, so that each those image sensing chip and this transparent insulator keep a spacing.
Aforesaid semiconductor chip package procedure, wherein said formation one metal level step is to plate a metal seed layer (seed layer) with sputtering way, forms metal level with plating mode on this metal seed layer again.
The object of the invention to solve the technical problems also realizes by the following technical solutions.According to a kind of semiconductor chip package that the present invention proposes, it comprises: an image sensing chip (imagesensor die), and it comprises an active surface, and an opposing backside surface, and has an active area and a plurality of weld pad on this active surface; One transparent insulator, it is to be arranged on this image sensing chip active area; One insulating barrier, it is the peripheral region that is formed at this image sensing chip active surface and coats this image sensing chip, and has plurality of openings, in order to expose those weld pads of this image sensing chip; One patterned metal layer, it is the subregion that is formed at this insulating barrier, those insulating barrier openings and this image sensing chip back side, and forms a plurality of contacts in this back side, and this patterned metal layer is electrically connected at those weld pads; And a plurality of vias, be to run through this insulating barrier, and be electrically connected at this patterned metal layer.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid semiconductor chip package; it more comprises a protective layer and a lower protective layer on one; should go up the upper surface that protective layer is formed at this insulating barrier; and expose this transparent insulator place; this lower protective layer then is formed at this image sensing chip back side; and have at least one opening, in order to expose those contacts.
Aforesaid semiconductor chip package, between wherein said insulating barrier and this patterned metal layer, more comprising a stress-buffer layer is formed on this image sensing chip back side, and this stress-buffer layer is positioned at the below of this insulating barrier lower surface, and this patterned metal layer and be coated on the bottom surface of this stress-buffer layer.
Aforesaid semiconductor chip package, it more comprises a grid (space) and places on this image sensing chip active surface, and props up this transparent insulator, it is striden establish and keep a spacing on this image sensing chip active area.
Aforesaid semiconductor chip package, a upper surface of its insulating barrier and this transparent insulator end face are with high.
The present invention compared with prior art has tangible advantage and beneficial effect.As known from the above, for achieving the above object, the invention provides a kind of semiconductor chip package procedure and structure thereof, its fabrication steps comprises: a substrate with a upper surface and a lower surface is provided, substrate comprises a plurality of image sensing chips and peripheral insulation colloid, each image sensing chip has an active surface that flushes with upper surface of substrate and and flushes opposing backside surface with substrate lower surface, has a plurality of weld pads on the active surface, and an active area; Cover a transparent insulator on the active area of each image sensing chip; Form an insulating barrier in upper surface of substrate; Form plurality of openings on insulating barrier, and its opening is to be positioned at image sensing chip weld pad place, so that weld pad is exposed; Form a plurality of through holes in the image sensing chip outside, and run through the insulation colloid of insulating barrier and substrate; Form a metal level on surface of insulating layer, open surfaces, weld pad surface, through hole surface and substrate lower surface, to extend weld pad to substrate lower surface; Patterned metal layer is with exposed transparent insulator top area, and the subregion of removing the metal level on the substrate lower surface, and forms a plurality of contacts; And impose cutting technique, to form a plurality of encapsulating structures that comprise single image sensor chip.
By technique scheme, semiconductor chip package procedure of the present invention and structure thereof have following advantage and beneficial effect at least:
Semiconductor chip package procedure of the present invention and structure thereof have been adopted, can use its processing procedure that the contact of the active surface of chip is extended the side chip back, and the packaging part of formation bumpless, and because of this processing procedure can be made opening above the active area of its packaged chip active surface, can make chip component contact, be applicable to the encapsulation of optical elements such as Image Sensor with light source.
In sum, the present invention discloses a kind of semiconductor chip package procedure and structure thereof, and its processing procedure comprises: provide one to comprise image sensing chip and the substrate of the colloid that insulate, its image sensing chip has weld pad and active area; Cover a transparent insulator on active area; Form an insulating barrier in upper surface of substrate; Open plurality of openings with exposed weld pad; Form a plurality of through holes in the image sensing chip outside, and run through insulating barrier and insulation colloid; Form a metal level in surface of insulating layer, open surfaces, weld pad surface, through hole surface and substrate lower surface, to extend weld pad to substrate lower surface; Patterned metal layer is with exposed transparent insulator top area and remove the subregion of the metal level on the substrate lower surface and form contact; Cutting forms the encapsulating structure that comprises single image sensor chip.The present invention has above-mentioned plurality of advantages and practical value, no matter it all has bigger improvement on method, product structure or function, obvious improvement is arranged technically, and produced handy and practical effect, and the outstanding effect that has enhancement than prior art, thereby being suitable for practicality more, and having the extensive value of industry, really is a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Figure 1A illustrates the semiconductor chip package of prior art;
Figure 1B illustrates the semiconductor chip package of another prior art;
Fig. 2 A, Fig. 2 B, Fig. 2 C, Fig. 2 D, Fig. 2 E, Fig. 2 F, Fig. 2 G and Fig. 2 H illustrate the manufacturing process generalized section of first embodiment of the invention;
Fig. 3 A, Fig. 3 B, Fig. 3 C, Fig. 3 D and Fig. 3 E illustrate the manufacturing process generalized section of second embodiment of the invention;
Fig. 4 A illustrates the encapsulating structure generalized section of first embodiment of the invention;
Fig. 4 B illustrates the encapsulating structure generalized section of second embodiment of the invention;
Fig. 5 A illustrates the stress-buffer layer encapsulating structure generalized section that is formed at the image sensing chip back side and insulating barrier lower surface of the present invention; And
Fig. 5 B illustrates the encapsulating structure generalized section that grid between utilization of the present invention is erected transparent insulator.
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, to semiconductor chip package procedure and its embodiment of structure, step, structure, feature and the effect thereof that foundation the present invention proposes, describe in detail as after.
See also the manufacturing process generalized section of the first embodiment of the invention that Fig. 2 A, Fig. 2 B, Fig. 2 C, Fig. 2 D, Fig. 2 E, Fig. 2 F, Fig. 2 G and Fig. 2 H illustrated.Its manufacturing step is to comprise: a substrate 21 is provided in advance, substrate 21 has a upper surface 211 and a lower surface 212, and substrate 21 is insulation colloids 214 that comprise a plurality of image sensing chips 213 and be surrounded on image sensing chip 213, each image sensing chip 213 has an active surface 2131 that flushes with substrate 21 upper surfaces 211 and a back side 2132 that flushes with substrate 21 lower surfaces 212, has a plurality of weld pads 21311 and an active area 21312 on the active surface 2131; Cover a transparent insulator 22 again, as the mode of using a transparent colloid directly to cover, or utilize glass to be covered on the active area 21312 of each image sensing chip 213, also can use that a grid 31 is propped up transparent insulator 22 so that image sensing chip 213 keeps a spacing with transparent insulator 22; The continuous insulating barrier 23 that forms is in substrate 21 upper surfaces 211, and its thickness and transparent insulator 22 end faces are good about equally; Then can utilize as the exposure imaging technology and form plurality of openings 231 on insulating barrier 23, and be positioned at image sensing chip 213 weld pads, 21311 places and make weld pad 21311 exposed; Form a plurality of through holes 24 again in image sensing chip 213 outsides, and through hole 24 is the insulation colloids 214 that run through insulating barrier 23 and substrate 21; Form a metal level 25 again on insulating barrier 23 surfaces, opening 231 surfaces, weld pad 21311 surfaces, through hole 24 surfaces and substrate 21 lower surfaces, to extend weld pad 21311 to substrate 21 lower surfaces, and its generation type can plate metal seed layer (seed layer) earlier in its surperficial (not shown) with sputtering way earlier, form metal level 25 on metal seed layer, with plating mode again so that metal level 25 tool adequate thicknesses; Then with metal level 25 patternings with exposed transparent insulator 22 top area, and the subregion of removing the metal level 25 on substrate 21 lower surfaces, and form a plurality of contacts 26; Impose cutting technique at last, in order to form a plurality of semiconductor chip packages that comprise single image sensing chip 213.
See also the manufacturing process generalized section of the second embodiment of the invention that Fig. 3 A, Fig. 3 B, Fig. 3 C, Fig. 3 D and Fig. 3 E illustrated.It is as described below that above-mentioned first embodiment of the invention also can further be improved to another second embodiment again, above-mentioned first embodiment with metal level 25 patternings with exposed transparent insulator 22 top area steps after, impose the cutting technique step before, more comprise the following steps: to form a protective layer 27 and a lower protective layer 28 on one, last protective layer 27 is located at substrate 21 upper surfaces 211, and lower protective layer 28 is located at substrate 21 lower surfaces 212; Form the plant ball position of plurality of openings 29 again in lower protective layer 28, and the relative position of going up transparent insulator 22 tops of protective layer 27, to expose transparent insulator 22 top surfaces; At last form a plurality of soldered balls 30 each contact 26 again, electrically connect so that soldered ball 30 forms with metal level 25 in lower protective layer 28.
Among above-mentioned first embodiment or second embodiment, formed a plurality of through holes 24 before the step in image sensing chip 213 outsides, more comprise formation one stress-buffer layer 32 in the step of substrate lower surface.And aforementioned through hole 24 more comprises and runs through stress-buffer layer 32.
Among above-mentioned first embodiment or second embodiment, more comprise in advance at transparent insulator 22 top surfaces subsides one protection glue (not shown) in the step that covers a transparent insulator 22, and in the step that forms a plurality of soldered balls 30, more comprise the step of removing protection glue.
See also the encapsulating structure generalized section of Fig. 4 first embodiment of the invention that A illustrates.Its semiconductor chip package 40 comprises: an image sensing chip 213 (image sensor die), and it comprises an active surface 2131, and an opposing backside surface 2132, and has an active area 21312 and a plurality of weld pad 21311 on the active surface 2131; One transparent insulator 22 is to be arranged on image sensing chip 213 active area 21312; One insulating barrier 23 is the peripheral regions that are formed at image sensing chip 213 active surfaces 2131 and coat image sensing chip 213, and has the weld pad 21311 of plurality of openings 231 in order to expose image sensing chip 213; One patterned metal layer 41 is the subregions that are formed at insulating barrier 23, opening 231 and image sensing chip 213 back sides, and forms a plurality of contacts 26 in the back side, and patterned metal layer 41 is electrically connected at weld pad 21311; And a plurality of vias 42, be to run through insulating barrier 23 and be electrically connected at patterned metal layer 41.
Continuous Fig. 4 B that sees also.The improvement of above-mentioned semiconductor chip package 40 structures; can more comprise a protective layer 27 and a lower protective layer 28 on one; last protective layer 27 is formed at the upper surface of insulating barrier 23; and expose transparent insulator 22 places; lower protective layer 28 then is formed at image sensing chip 213 back sides; and have at least one opening 29, in order to expose contact 26.Also can comprise a plurality of soldered balls 30 again, it is to be formed on those contacts 26.
Continuous Fig. 5 A that sees also.The improvement of aforesaid semiconductor chip-packaging structure 40 structures, wherein between insulating barrier 23 and the patterned metal layer 41, more comprise a stress-buffer layer 32 and be formed on image sensing chip 213 back sides and insulating barrier 23 lower surfaces, and patterned metal layer 41 and be coated on the bottom surface of stress-buffer layer 32.
Continuous Fig. 5 B that sees also.Aforesaid semiconductor chip-packaging structure 40 structures can more comprise a grid 31 (space) and place on image sensing chip 213 active surfaces 2131, and prop up transparent insulator 22, it is striden establish and keep a spacing on image sensing chip 213 active area 21312.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be not break away from the technical solution of the present invention content, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (13)
1. semiconductor chip package procedure is characterized in that it comprises the following step:
One substrate is provided, this substrate has a upper surface and a lower surface, and this substrate is an insulation colloid that comprises a plurality of image sensing chips and be surrounded on those image sensing chips, each those image sensing chip has an active surface that flushes with this upper surface of substrate and a back side that flushes with this substrate lower surface, have a plurality of weld pads on this active surface, and an active area;
Cover a transparent insulator on the active area of each those image sensing chip;
Form an insulating barrier in this upper surface of substrate;
Form plurality of openings on this insulating barrier, and those openings are to be positioned at those image sensing chip weld pad places, so that those weld pads are exposed;
Form a plurality of through holes in those image sensing chip outsides, and run through the insulation colloid of this insulating barrier and this substrate;
Form a metal level on this surface of insulating layer, those open surfaces, those weld pad surfaces, those through hole surfaces and this substrate lower surface, to extend those weld pads to this substrate lower surface;
This metal level of patterning, with exposed this transparent insulator top area, and the subregion of removing this metal level on this substrate lower surface, and form a plurality of contacts; And
Impose cutting technique, in order to form a plurality of encapsulating structures that comprise single image sensor chip.
2. semiconductor chip package procedure according to claim 1 is characterized in that wherein more comprising the following step after this metal level step of this patterning and before imposing the cutting technique step:
Form a protective layer and a lower protective layer on, protective layer is located at this upper surface of substrate on this, and this lower protective layer is located at this substrate lower surface;
Form plurality of openings in a plurality of ball positions of planting of this lower protective layer, reach the relative position at this transparent insulator top of protective layer on this, to expose this transparent insulator top surface; And
Form a plurality of soldered balls in those contacts, be connected so that those soldered balls form with this metal level.
3. semiconductor chip package procedure according to claim 1 is characterized in that wherein a plurality of through holes of this formation more comprised formation one stress-buffer layer in this substrate lower surface before the step in those image sensing chip outsides.
4. semiconductor chip package procedure according to claim 3, it is characterized in that wherein those through holes more comprise runs through this stress-buffer layer.
5. semiconductor chip package procedure according to claim 1, it is characterized in that wherein the step of this covering one transparent insulator more comprises in advance at this transparent insulator top surface subsides one protection glue, and form in the step of a plurality of soldered balls at this, more comprise and remove this protection glue.
6. semiconductor chip package procedure according to claim 1 is characterized in that wherein the step of this covering one transparent insulator is to utilize a transparent colloid that this transparent insulator directly is covered on each those image sensing chip active area.
7. semiconductor chip package procedure according to claim 1, it is characterized in that wherein the step of this covering one transparent insulator is on each those image sensing chip active area, utilize a grid to prop up this transparent insulator, so that each those image sensing chip and this transparent insulator keep a spacing.
8. semiconductor chip package procedure according to claim 1 is characterized in that wherein this formation one metal level step is to plate a metal seed layer with sputtering way, forms metal level with plating mode on this metal seed layer again.
9. semiconductor chip package is characterized in that it comprises:
One image sensing chip, it comprises an active surface, and an opposing backside surface, and has an active area and a plurality of weld pad on this active surface;
One transparent insulator, it is to be arranged on this image sensing chip active area;
One insulating barrier, it is the peripheral region that is formed at this image sensing chip active surface and coats this image sensing chip, and has plurality of openings, in order to expose those weld pads of this image sensing chip;
One patterned metal layer, it is the subregion that is formed at this insulating barrier, those insulating barrier openings and this image sensing chip back side, and forms a plurality of contacts in this back side, and this patterned metal layer is electrically connected at those weld pads; And
A plurality of vias are to run through this insulating barrier, and are electrically connected at this patterned metal layer.
10. semiconductor chip package according to claim 9; it is characterized in that it more comprises a protective layer and a lower protective layer on one; should go up the upper surface that protective layer is formed at this insulating barrier; and expose this transparent insulator place; this lower protective layer then is formed at this image sensing chip back side; and have at least one opening, in order to expose those contacts.
11. semiconductor chip package according to claim 9, it is characterized in that wherein between this insulating barrier and this patterned metal layer, more comprising a stress-buffer layer is formed on this image sensing chip back side, and this stress-buffer layer is positioned at the below of this insulating barrier lower surface, and this patterned metal layer and be coated on the bottom surface of this stress-buffer layer.
12. semiconductor chip package according to claim 9, it is characterized in that it more comprises a grid and places on this image sensing chip active surface, and prop up this transparent insulator, it is striden establish and keep a spacing on this image sensing chip active area.
13. semiconductor chip package according to claim 9 is characterized in that wherein a upper surface and this transparent insulator end face of this insulating barrier are high together.
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| CN2007101515823A CN101131941B (en) | 2007-09-28 | 2007-09-28 | Semiconductor chip packaging process and its structure |
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| CN103855066A (en) * | 2012-11-28 | 2014-06-11 | 硕达科技股份有限公司 | Image induction chip packaging method for protecting chip |
| CN104659041A (en) * | 2013-11-20 | 2015-05-27 | 硕达科技股份有限公司 | Packaging method of induction chip |
| JP6612979B2 (en) * | 2015-10-28 | 2019-11-27 | チャイナ ウェイファー レベル シーエスピー カンパニー リミテッド | Image sensing chip packaging structure and packaging method |
| US10276536B2 (en) * | 2017-04-28 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and formation method of chip package with fan-out structure |
| TWI710123B (en) * | 2019-11-27 | 2020-11-11 | 恆勁科技股份有限公司 | Package structure of sensor device and manufacturing method thereof |
| CN112864030B (en) * | 2021-01-18 | 2022-08-09 | 北京师范大学 | Packaging method and packaging structure of photoelectric detection chip |
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