CN101131941A - Semiconductor chip packaging process and structure thereof - Google Patents

Abstract

The invention relates to a semiconductor chip packaging process and a structure thereof, wherein the process comprises the following steps: providing a substrate comprising an image sensing chip and an insulating colloid, wherein the image sensing chip is provided with a welding pad and an active area; covering a transparent insulator on the active region; forming an insulating layer on the upper surface of the substrate; opening the plurality of openings to expose the bonding pads; forming a plurality of through holes on the outer side of the image sensing chip and penetrating the insulating layer and the insulating colloid; forming a metal layer on the surface of the insulating layer, the surface of the opening, the surface of the welding pad, the surface of the through hole and the lower surface of the substrate so as to extend the welding pad to the lower surface of the substrate; patterning the metal layer to expose the top region of the transparent insulator and remove part of the metal layer on the lower surface of the substrate to form contacts; cutting to form a package structure containing a single image sensing chip.

Description

Semiconductor chip packaging process and its structure

technical field

The invention relates to a semiconductor chip packaging process and its structure, in particular to a manufacturing method and structure of a non-bump packaging structure suitable for image sensing elements.

Background technique

Please refer to US Patent Publication No. 6,040,235 shown in FIG. 1A , which discloses a semiconductor chip packaging method. The patented technology is to cover an insulating material 120 on the active surface of a wafer 110, such as glass, which extends from the contact on the active surface of the wafer. to the backside of the wafer. After the wafer is cut into a plurality of chips, the contacts of each chip are extended to the surface of the package through the metal lines 130 . However, if there are too many chip defective products in each wafer, for example, half of the chips in a wafer are defective products, it is obviously not beneficial to use this packaging method.

In addition, please refer to the US Patent Publication No. 6,271,469 shown in FIG. 1B , which discloses a semiconductor chip packaging method, which uses the colloid 140 as the substrate of the chip carrier 150, and then forms an insulating layer 160, and forms metal lines on the insulating layer. 170. Through this procedure, a packaging structure without bumps can be formed. However, this process and structure cannot form hollow openings on the surface of the semiconductor chip, so it is not suitable for packaging image sensing elements or temperature and humidity sensing elements and other semiconductor chips that must be active in contact with the air. Therefore, its application The field is limited.

Contents of the invention

The purpose of the present invention is to overcome the defects in the prior art and provide a new semiconductor chip packaging process and its structure. The technical problem to be solved is to make the packaging structure have contacts extending from the active surface of the chip to the back of the chip. And the active area on the active surface of the chip has an opening structure required by the image sensing chip, which is very suitable for practical use.

The purpose of the present invention and the solution to its technical problems are achieved by adopting the following technical solutions. According to a semiconductor chip packaging process proposed by the present invention, it includes the following steps: providing a substrate, the substrate has an upper surface and a lower surface, and the substrate includes a plurality of image sensor chips and surrounds the image sensor chips. An insulating gel of the chip, each of the image sensing chips has an active surface flush with the upper surface of the substrate and a back surface flush with the lower surface of the substrate, a plurality of welding pads are provided on the active surface, and a active area; covering a transparent insulator on the active area of each of the image sensing chips; forming an insulating layer on the upper surface of the substrate; forming a plurality of openings on the insulating layer, and the openings are located in the images Sensing chip bonding pads, so that these bonding pads are exposed; forming a plurality of through holes on the outside of these image sensing chips, and penetrating through the insulating layer and the insulating glue of the substrate; forming a metal layer on the surface of the insulating layer , the surfaces of the openings, the surfaces of the pads, the surfaces of the through holes, and the lower surface of the substrate, so as to extend the pads to the lower surface of the substrate; pattern the metal layer to expose the top region of the transparent insulator, and removing part of the metal layer on the lower surface of the substrate to form a plurality of contacts; and applying cutting technology to form a plurality of packaging structures including a single image sensing chip.

The purpose of the present invention and its technical problems can also be further realized by adopting the following technical measures.

The aforementioned semiconductor chip packaging process, wherein after the step of patterning the metal layer and before the step of dicing, further includes the following steps: forming an upper protective layer and a lower protective layer, the upper protective layer is provided on the substrate surface, the lower protective layer is arranged on the lower surface of the substrate; a plurality of openings are formed at the ball planting positions of the lower protective layer, and the relative positions of the top of the transparent insulator of the upper protective layer, so as to expose the top of the transparent insulator surface; and forming a plurality of solder balls on each of the contacts of the lower protective layer, so that the solder balls form a connection with the metal layer.

In the aforementioned semiconductor chip packaging process, before the step of forming a plurality of through holes outside the image sensing chips, it further includes forming a stress buffer layer on the lower surface of the substrate.

In the aforementioned semiconductor chip packaging process, the through holes further include penetrating through the stress buffer layer.

In the aforementioned semiconductor chip packaging process, the step of covering a transparent insulator further includes pasting a protective glue on the top surface of the transparent insulator, and the step of forming a plurality of solder balls further includes removing the protective glue.

In the aforementioned semiconductor chip packaging process, the step of covering a transparent insulator is to use a transparent colloid to directly cover the transparent insulator on the active area of each of the image sensing chips.

The aforementioned semiconductor chip packaging process, wherein the step of covering a transparent insulator is to use a spacer to prop up the transparent insulator on the active area of each of the image sensing chips, so that each of the A distance is maintained between the image sensor chip and the transparent insulator.

The aforementioned semiconductor chip packaging process, wherein the step of forming a metal layer is to plate a metal seed layer (seed layer) by sputtering, and then form a metal layer on the metal seed layer by electroplating.

The purpose of the present invention and the solution to its technical problem also adopt the following technical solutions to achieve. According to a semiconductor chip packaging structure proposed by the present invention, it includes: an image sensor die (image sensor die), which includes an active surface, and an opposite back, and the active surface has an active area and a plurality of welding Pad; a transparent insulator, which is arranged on the active area of the image sensing chip; an insulating layer, which is formed on the active surface of the image sensing chip and covers the surrounding area of the image sensing chip, and has a plurality of openings for exposing the bonding pads of the image sensing chip; a patterned metal layer formed on the insulating layer, the openings of the insulating layer and a part of the backside of the image sensing chip, and on the part of the back of the image sensing chip A plurality of contacts are formed on the back surface, and the patterned metal layer is electrically connected to the welding pads; and a plurality of via holes penetrate the insulating layer and are electrically connected to the patterned metal layer.

The purpose of the present invention and its technical problems can also be further realized by adopting the following technical measures.

The aforementioned semiconductor chip packaging structure further includes an upper protective layer and a lower protective layer, the upper protective layer is formed on the upper surface of the insulating layer and exposes the transparent insulator, and the lower protective layer is formed on the image The back surface of the sensing chip has at least one opening for exposing the contacts.

The aforementioned semiconductor chip packaging structure, wherein between the insulating layer and the patterned metal layer, further includes a stress buffer layer formed on the back surface of the image sensing chip and the lower surface of the insulating layer, and the patterned metal layer And coated on the bottom surface of the stress buffer layer.

The aforementioned semiconductor chip packaging structure further includes a space placed on the active surface of the image sensing chip, and propping up the transparent insulator so that it straddles and maintains a distance between the active area of the image sensing chip superior.

In the aforementioned semiconductor chip packaging structure, an upper surface of the insulating layer is at the same height as the top surface of the transparent insulator.

Compared with the prior art, the present invention has obvious advantages and beneficial effects. As can be seen from the above, in order to achieve the above object, the present invention provides a semiconductor chip packaging process and its structure, the process steps include: providing a substrate with an upper surface and a lower surface, the substrate includes a plurality of image sensing chips and peripheral Each image sensor chip has an active surface that is flush with the upper surface of the substrate and a back surface that is flush with the lower surface of the substrate. There are a plurality of solder pads on the active surface and an active area; covering a transparent An insulator is placed on the active area of each image sensing chip; an insulating layer is formed on the upper surface of the substrate; a plurality of openings are formed on the insulating layer, and the openings are located at the bonding pads of the image sensing chip, so that the bonding pads are exposed; Forming a plurality of through holes on the outside of the image sensor chip, and penetrating through the insulating colloid of the insulating layer and the substrate; forming a metal layer on the surface of the insulating layer, the surface of the opening, the surface of the pad, the surface of the through hole and the lower surface of the substrate to extend the welding Pad to the lower surface of the substrate; pattern the metal layer to expose the top area of the transparent insulator, and remove part of the metal layer on the lower surface of the substrate to form a plurality of contacts; and apply cutting technology to form a plurality of single image sensors. Chip packaging structure.

By virtue of the above technical solutions, the semiconductor chip packaging process and its structure of the present invention have at least the following advantages and beneficial effects:

Adopting the semiconductor chip packaging process and its structure of the present invention, the contacts on the active surface of the chip can be extended to the back of the chip by using the process to form a package without bumps, and because the process can be used on the active surface of the packaged chip. Openings are made above the active area of the surface so that the chip components can be in contact with the light source, which is more suitable for the packaging of optical components such as image sensing components.

To sum up, the present invention discloses a semiconductor chip packaging process and its structure. The process includes: providing a substrate including an image sensing chip and insulating colloid, the image sensing chip having a pad and an active area; covering a transparent The insulator is on the active area; an insulating layer is formed on the upper surface of the substrate; a plurality of openings are opened to expose the pad; a plurality of through holes are formed on the outside of the image sensing chip, and penetrate the insulating layer and insulating colloid; a metal layer is formed on the insulating The surface of the layer, the surface of the opening, the surface of the pad, the surface of the through hole and the lower surface of the substrate, so as to extend the pad to the lower surface of the substrate; the patterned metal layer is formed by exposing the top area of the transparent insulator and removing a part of the metal layer on the lower surface of the substrate Forming contacts; dicing to form a package structure including a single image sensor chip. The present invention has the above-mentioned many advantages and practical value, it has great improvement no matter in method, product structure or function, has significant progress in technology, and has produced easy-to-use and practical effect, and has more advantages than prior art The enhanced outstanding function is more suitable for practical use and has wide application value in the industry. It is a novel, progressive and practical new design.

The above description is only an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention, it can be implemented according to the contents of the description, and in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable , the following preferred embodiments are specifically cited below, and are described in detail as follows in conjunction with the accompanying drawings.

Description of drawings

FIG. 1A illustrates a prior art semiconductor chip packaging structure;

FIG. 1B illustrates another prior art semiconductor chip packaging structure;

FIG. 2A, FIG. 2B, FIG. 2C, FIG. 2D, FIG. 2E, FIG. 2F, FIG. 2G and FIG. 2H are schematic cross-sectional views of the manufacturing process of the first embodiment of the present invention;

FIG. 3A, FIG. 3B, FIG. 3C, FIG. 3D and FIG. 3E are schematic cross-sectional views of the manufacturing process of the second embodiment of the present invention;

FIG. 4A is a schematic cross-sectional view of the packaging structure of the first embodiment of the present invention;

FIG. 4B is a schematic cross-sectional view of the packaging structure of the second embodiment of the present invention;

5A is a schematic cross-sectional view of the package structure of the stress buffer layer formed on the back surface of the image sensor chip and the lower surface of the insulating layer of the present invention; and

FIG. 5B is a schematic cross-sectional view of the packaging structure of the present invention in which the transparent insulator is erected by lattices.

Detailed ways

In order to further explain the technical means and effects that the present invention adopts to achieve the intended purpose of the invention, below in conjunction with the accompanying drawings and preferred embodiments, the semiconductor chip packaging process and its structure according to the present invention will be described according to its specific implementation, steps, and structure. , features and their effects are described in detail below.

Please refer to FIG. 2A , FIG. 2B , FIG. 2C , FIG. 2D , FIG. 2E , FIG. 2F , FIG. 2G and FIG. 2H , which are schematic cross-sectional views of the manufacturing process of the first embodiment of the present invention. The manufacturing steps include: providing a substrate 21 in advance, the substrate 21 has an upper surface 211 and a lower surface 212, and the substrate 21 includes a plurality of image sensing chips 213 and an insulating colloid 214 surrounding the image sensing chips 213, Each image sensing chip 213 has an active surface 2131 flush with the upper surface 211 of the substrate 21 and a back surface 2132 flush with the lower surface 212 of the substrate 21. The active surface 2131 has a plurality of solder pads 21311 and an active region 21312 Cover a transparent insulator 22 again, such as using a transparent colloid to directly cover, or using glass to cover the active area 21312 of each image sensor chip 213, and a grid 31 can also be used to prop up the transparent insulator 22 so that The image sensor chip 213 is kept at a distance from the transparent insulator 22; continue to form an insulating layer 23 on the upper surface 211 of the substrate 21, the thickness of which is approximately equal to that of the top surface of the transparent insulator 22; and then a plurality of openings can be formed by using techniques such as exposure and development 231 is on the insulating layer 23, and is located at the bonding pad 21311 of the image sensing chip 213 so that the bonding pad 21311 is exposed; then a plurality of through holes 24 are formed outside the image sensing chip 213, and the through holes 24 penetrate the insulating layer 23 and The insulating colloid 214 of the base 21; and then form a metal layer 25 on the surface of the insulating layer 23, the surface of the opening 231, the surface of the welding pad 21311, the surface of the through hole 24 and the lower surface of the base 21, so as to extend the welding pad 21311 to the lower surface of the base 21, And its formation method can first coat metal seed layer (seed layer) on its surface (not shown in the figure) by sputtering, and then form metal layer 25 on the metal seed layer by electroplating, so that metal layer 25 has sufficient thickness; then the metal layer 25 is patterned to expose the top region of the transparent insulator 22, and part of the metal layer 25 on the lower surface of the substrate 21 is removed to form a plurality of contacts 26; finally, a cutting technique is applied to form a plurality of contacts. A semiconductor chip package structure including a single image sensor chip 213 .

Please refer to FIG. 3A , FIG. 3B , FIG. 3C , FIG. 3D and FIG. 3E , which are schematic cross-sectional views of the manufacturing process of the second embodiment of the present invention. The above-mentioned first embodiment of the present invention can also be further improved into another second embodiment as described below, after the step of patterning the metal layer 25 to expose the top area of the transparent insulator 22 in the above-mentioned first embodiment, cutting Before the technical steps, the following steps are further included: forming an upper protective layer 27 and a lower protective layer 28, the upper protective layer 27 is arranged on the upper surface 211 of the substrate 21, and the lower protective layer 28 is arranged on the lower surface 212 of the substrate 21; then forming a plurality of openings 29 at the ball planting position of the lower protective layer 28, and the relative position of the transparent insulator 22 top of the upper protective layer 27, to expose the top surface of the transparent insulator 22; finally form a plurality of solder balls 30 on each of the lower protective layer 28 The contact 26 is used to form an electrical connection between the solder ball 30 and the metal layer 25 .

In the above-mentioned first or second embodiment, before the step of forming the plurality of through holes 24 outside the image sensor chip 213, a step of forming a stress buffer layer 32 on the lower surface of the substrate is further included. Moreover, the aforementioned through hole 24 further includes a through stress buffer layer 32 .

In the first embodiment or the second embodiment above, the step of covering a transparent insulator 22 further includes pasting a protective glue (not shown in the figure) on the top surface of the transparent insulator 22 in advance, and the step of forming a plurality of solder balls 30 , including the step of removing the protective glue.

Please refer to FIG. 4A , which is a schematic cross-sectional view of the packaging structure of the first embodiment of the present invention. Its semiconductor chip packaging structure 40 includes: an image sensing chip 213 (image sensor die), which includes an active surface 2131, and a relative back surface 2132, and has an active area 21312 and a plurality of welding pads 21311 on the active surface 2131 ; A transparent insulator 22 is disposed on the active area 21312 of the image sensing chip 213; an insulating layer 23 is formed on the active surface 2131 of the image sensing chip 213 and covers the surrounding area of the image sensing chip 213, and has a plurality of openings 231 is used to expose the bonding pad 21311 of the image sensor chip 213; a patterned metal layer 41 is formed on the insulating layer 23, the opening 231 and a part of the backside of the image sensor chip 213, and forms a plurality of contacts 26 on the backside, And the patterned metal layer 41 is electrically connected to the pad 21311 ; and a plurality of via holes 42 penetrate the insulating layer 23 and are electrically connected to the patterned metal layer 41 .

Continued see Figure 4B. The improvement of the structure of the above-mentioned semiconductor chip packaging structure 40 may further include an upper protective layer 27 and a lower protective layer 28, the upper protective layer 27 is formed on the upper surface of the insulating layer 23, and exposes the transparent insulator 22, and the lower protective layer 28 It is formed on the back of the image sensor chip 213 and has at least one opening 29 for exposing the contact 26 . It may further include a plurality of solder balls 30 formed on the contacts 26 .

See Figure 5A for continued. The improvement of the aforementioned semiconductor chip packaging structure 40 structure, wherein between the insulating layer 23 and the patterned metal layer 41, a stress buffer layer 32 is formed on the back of the image sensing chip 213 and the lower surface of the insulating layer 23, and the patterned metal layer The layer 41 covers the bottom surface of the stress buffer layer 32 .

Please refer to Figure 5B for continued. The aforementioned semiconductor chip packaging structure 40 may further include a grid 31 (space) placed on the active surface 2131 of the image sensing chip 213, and propping up the transparent insulator 22 so that it straddles and maintains a distance between the image sensing chip 213 Active area 21312 on.

The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone familiar with this field Those skilled in the art, without departing from the scope of the technical solution of the present invention, may use the technical content disclosed above to make some changes or modify them into equivalent embodiments with equivalent changes, but as long as they do not depart from the technical solution of the present invention, the Technical Essence Any simple modifications, equivalent changes and modifications made to the above embodiments still fall within the scope of the technical solution of the present invention.

Claims (13)

1. A semiconductor chip packaging process, characterized in that it comprises the following steps: A base is provided, the base has an upper surface and a lower surface, and the base includes a plurality of image sensing chips and an insulating gel surrounding the image sensing chips, each of the image sensing chips has a An active surface flush with the upper surface of the substrate and a back surface flush with the lower surface of the substrate, the active surface has a plurality of welding pads, and an active area; Covering a transparent insulator on the active area of each of the image sensing chips; forming an insulating layer on the upper surface of the substrate; forming a plurality of openings on the insulating layer, and the openings are located at the bonding pads of the image sensing chip, so that the bonding pads are exposed; forming a plurality of through holes on the outside of the image sensing chips, and penetrating through the insulating layer and the insulating glue of the substrate; forming a metal layer on the surface of the insulating layer, the surfaces of the openings, the surfaces of the pads, the surfaces of the through holes, and the lower surface of the base, so as to extend the pads to the lower surface of the base; patterning the metal layer to expose the top region of the transparent insulator, and removing a portion of the metal layer on the lower surface of the substrate to form a plurality of contacts; and A dicing technique is applied to form a plurality of packaging structures including a single image sensor chip. 2. The semiconductor chip packaging process according to claim 1, further comprising the following steps after the step of patterning the metal layer and before the step of cutting the metal layer: forming an upper protective layer and a lower protective layer, the upper protective layer is arranged on the upper surface of the substrate, and the lower protective layer is arranged on the lower surface of the substrate; forming a plurality of openings at the ball planting positions of the lower protection layer, and at positions opposite to the top of the transparent insulator of the upper protection layer, so as to expose the top surface of the transparent insulator; and A plurality of solder balls are formed on each of the contacts of the lower protective layer, so that the solder balls are connected with the metal layer. 3 . The semiconductor chip packaging process according to claim 1 , wherein before the step of forming a plurality of through holes outside the image sensing chips, it further comprises forming a stress buffer layer on the lower surface of the substrate. 4 . 4. The semiconductor chip packaging process according to claim 3, wherein the through holes further include penetrating through the stress buffer layer. 5. The semiconductor chip packaging process according to claim 1, wherein the step of covering a transparent insulator further comprises pasting a protective glue on the top surface of the transparent insulator in advance, and in the step of forming a plurality of solder balls , including removing the protective glue. 6 . The semiconductor chip packaging process according to claim 1 , wherein the step of covering a transparent insulator is to use a transparent colloid to directly cover the transparent insulator on the active area of each of the image sensing chips. 7. The semiconductor chip packaging process according to claim 1, wherein the step of covering a transparent insulator is to use a grid to prop up the transparent insulator on the active area of each of the image sensing chips, so as to A distance is maintained between each of the image sensing chips and the transparent insulator. 8 . The semiconductor chip packaging process according to claim 1 , wherein the step of forming a metal layer is to plate a metal seed layer by sputtering, and then to form a metal layer on the metal seed layer by electroplating. 9. A semiconductor chip packaging structure, characterized in that it comprises: An image sensing chip, which includes an active surface and an opposite back surface, and has an active area and a plurality of welding pads on the active surface; a transparent insulator disposed on the active area of the image sensing chip; an insulating layer, which is formed on the active surface of the image sensing chip and covers the surrounding area of the image sensing chip, and has a plurality of openings for exposing the bonding pads of the image sensing chip; A patterned metal layer, which is formed on the insulating layer, the openings of the insulating layer and a part of the back of the image sensor chip, and forms a plurality of contacts on the back, and the patterned metal layer is electrically connected to the pads; and A plurality of via holes penetrate the insulating layer and are electrically connected to the patterned metal layer. 10. The semiconductor chip packaging structure according to claim 9, further comprising an upper protective layer and a lower protective layer, the upper protective layer is formed on the upper surface of the insulating layer and exposes the transparent insulator, The lower protective layer is formed on the back of the image sensor chip and has at least one opening for exposing the contacts. 11. The semiconductor chip package structure according to claim 9, wherein between the insulating layer and the patterned metal layer, a stress buffer layer is further formed on the back surface of the image sensing chip and the lower surface of the insulating layer and the patterned metal layer covers the bottom surface of the stress buffer layer. 12. The semiconductor chip packaging structure according to claim 9, further comprising a grid placed on the active surface of the image sensing chip, and propping up the transparent insulator so that it straddles and maintains a distance between On the active area of the image sensor chip. 13. The semiconductor chip package structure according to claim 9, wherein an upper surface of the insulating layer is at the same height as the top surface of the transparent insulator.

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