CN101111939A - Flash memory cell having buried floating gate structure and method of manufacturing the same - Google Patents
Flash memory cell having buried floating gate structure and method of manufacturing the same Download PDFInfo
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- CN101111939A CN101111939A CNA2006800038515A CN200680003851A CN101111939A CN 101111939 A CN101111939 A CN 101111939A CN A2006800038515 A CNA2006800038515 A CN A2006800038515A CN 200680003851 A CN200680003851 A CN 200680003851A CN 101111939 A CN101111939 A CN 101111939A
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- 238000007667 floating Methods 0.000 title claims abstract description 119
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000004065 semiconductor Substances 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 238000005516 engineering process Methods 0.000 claims description 32
- 238000000034 method Methods 0.000 claims description 32
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 19
- 229920005591 polysilicon Polymers 0.000 claims description 19
- 238000002955 isolation Methods 0.000 claims description 13
- 150000004767 nitrides Chemical class 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 230000005641 tunneling Effects 0.000 claims description 2
- 239000008186 active pharmaceutical agent Substances 0.000 description 12
- 238000010586 diagram Methods 0.000 description 12
- 230000003071 parasitic effect Effects 0.000 description 9
- 230000008878 coupling Effects 0.000 description 8
- 238000010168 coupling process Methods 0.000 description 8
- 238000005859 coupling reaction Methods 0.000 description 8
- 238000001020 plasma etching Methods 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 230000005684 electric field Effects 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 230000001965 increasing effect Effects 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 101100204059 Caenorhabditis elegans trap-2 gene Proteins 0.000 description 2
- 244000287680 Garcinia dulcis Species 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000007850 degeneration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000004321 preservation Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000004576 sand Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42336—Gate electrodes for transistors with a floating gate with one gate at least partly formed in a trench
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
Abstract
Disclosed herein are a flash memory cell having a buried floating gate structure and a method of manufacturing the flash memory cell. The flash memory cell includes a semiconductor substrate, a control gate, a dielectric layer, a floating gate, a floating gate, a tunnel oxide layer, and source and drain regions. The control gate is formed on the semiconductor substrate and is formed of a first conductive layer. The dielectric layer is formed between the surface of the semiconductor substrate and the control gate. The floating gate is buried in the semiconductor substrate below the dielectric layer and is formed of a second conductive layer. The tunnel oxide layer formed to surround the floating gate in the semiconductor substrate. The source and drain regions are spaced apart from each other, with the floating gate and the tunnel oxide layer within the semiconductor substrate being disposed therebetween.
Description
Technical field
The present invention relates generally to the method for semiconductor device and manufacturing semiconductor device, the method that is specifically related to have the flash cell of buried floating gate structure and makes this flash cell.
Background technology
The characteristic of flush memory device is: even do not provide power supply to flush memory device, the information that is stored in its memory cell also will be retained.Therefore, this kind flush memory device is widely used on the storage card of computer being used for.The unit cell of normal flash device has the grid structure of stacked in order floating boom, control gate and electrode.
Fig. 1 is the cutaway view of traditional stack gate flash cell 100.As shown in Figure 1, in stack gate flash cell 100, on Semiconductor substrate 1, be formed with dark N trap 2, P trap 4 and trench isolation layer 2.On the surface of Semiconductor substrate 1, be formed with mutual separated source region 5 and drain region 6, between source region 5 and drain region 6, be provided with channel region.Stacked in order tunnel oxide 7, floating boom (being FG) 8, dielectric film 9 and control gate (CG) 10 in channel region.Dielectric film 9 is formed by oxide-nitride thing-oxide (ONO) layer.Source region 5 and drain region 6 all have the N that utilizes wall 11 to form
+/ N
-The structure of knot.
Fig. 2 is the circuit diagram of the electronic model of stack gate flash cell shown in Figure 1.As shown in Figure 2, C
FCBe the electric capacity that the ONO dielectric film 9 that is arranged between control gate 10 and the floating boom 8 is produced, C
SBe the parasitic capacitance that between source knot 5 and floating boom 8, produces, C
DBe the parasitic capacitance that between drain junction 6 and floating boom 8, produces, C
BBe the parasitic capacitance that between floating boom 8 and Semiconductor substrate 1, produces.At this moment, suppose total capacitance C
TEqual C
FC+ C
S+ C
B+ C
D, with respect to C
FCAnd C
B, C
SAnd C
DValue very little.Therefore, total capacitance C
TApproximate capacitor C
FCWith parasitic capacitance C
BSum, i.e. C
T C
FC+ C
BBased on the electric capacity that between each node, produces, the parasitic couplings rate can be defined as follows.That is, with the parasitic couplings rate a of source knot 5
SBe defined as C
S/ C
T, with the parasitic couplings rate a of drain junction 6
DBe defined as C
D/ C
T, with the parasitic couplings rate a of floating boom 8
GBe defined as C
FC/ C
T
In addition, V
CG, V
FS, V
S, V
DSAnd V
BBe respectively the bias voltage that is applied on control gate 10, floating boom 8, source knot 5, drain junction 6 and the Semiconductor substrate 1, wherein V
FSBe bias voltage V
CGAnd V
DSFunction, and have following relation:
By formula 1 as can be seen, when the parasitic couplings rate of floating boom 8 reduced, the amount of charge that is stored in the floating boom 8 reduced, and as bias voltage V
DSDuring increase, the amount of charge that is stored in the floating boom 8 increases.
At this moment, can't directly visit floating boom 8, thereby utilize the voltage V of the control gate 10 that direct control can be visited by electricity with electrical way
CGMethod, control the voltage V of floating boom 8 indirectly
FG
At this moment, the transistorized V of available following formula representation unit
T CGThreshold voltage shift Δ V
T CG:
By formula 3 as can be seen, V
T CGWith Q
FCBe directly proportional, and and C
FCBe inversely proportional to.
Also measure the threshold voltage shift Δ V of the unit that is caused by applying voltage by apply suitable bias voltage to source, leakage, grid and body
T CG, can finish the reading of stack gate flash cell 100, programming and erase operation.Be used to carry out read, the bias level of programming and erase operation is as follows:
Table 1
| Pattern | V S | V CG | V D | V B |
| Read operation | 0V | V cc(4.2V) | V read(0.7V) | 0V |
| Programming operation | 0V | V pp(9V) | V DS(4.75V) | 0V |
| Erase operation | Float | -V pp(-7V) | Float | V pp(9V) |
As shown in Figure 3 and Figure 4, the read operation of stack gate flash cell 100 is done in such a manner, and, measures the threshold voltage V that is injected the unit that is changed by electric charge that is
T, and measured value compared with the threshold voltage of reference unit.In order to reach this purpose, under the situation of the source region 5 of unit and body 1 ground connection, apply voltage V
CG=V
CC≈ 4.2V (that is V,
TE＜V
CG＜V
TP) and V
DS=V
READ≈ 1.0V, the transistorized leakage current I of measuring unit
D, and whether be in programming state or be in erase status according to measured electric current determining unit.
As shown in Figure 4, the programming operation of stack gate flash cell 100 is done in such a manner, that is, and and with the threshold voltage increase Δ V of cell transistor
T, Δ V
TBe V
TEWith V
TPPoor, and detect the threshold voltage increased.For lamination flash cell 100 is programmed, when under the situation of source region 5 and body 1 ground connection, applying V
CG=V
PP≈ 9V and V
DSDuring ≈ 4.75V, the source region below 85 moves to drain region 6 to electronics along raceway groove from floating boom.At this moment, when the transverse electric field that forms along raceway groove quickened electronics and therefore obtain enough energy, as shown in Figure 5, channel hot electron (CHE) was owing to longitudinal electric field enters in the floating boom 8 near 6 places, drain region.Because the CHE that enters, the threshold voltage variation of cell transistor Δ V
T, as shown in Equation 3.At this moment, obtain flowing into the electric current I of floating boom 8 by following formula
G
I
G＝dQ
FC/dt＝C
FCΔV
T CG/Δt
P (4)
Wherein, Δ t
PBe the programming time, and Δ V
T CGWith Δ t
PChange.In addition, Δ V
T CGDepending on following parameter sensitivity ground changes:
I) control-grid voltage V
CGWith drain voltage V
DS
The ii) coupling efficiency a between control gate and the floating boom
G, and C
FC
The iii) channel length of cell transistor and channel width;
Iv) temperature.
That is to say, when the length of effective channel in the stack gate flash cell (Leff) reduces, the thickness t of tunnel oxide
OxReduce C
FCIncrease, and V
CGOr V
SDDuring increase, Δ V
T CGIncrease.Thereby the programming time shortens.
In stack gate flash cell 100, be done in such a manner based on the programmed method of CHE, that is, under the situation of source region 5 ground connection, stress application voltage between control gate 10 and drain region 6 (stress voltage).In order to finish programming operation efficiently, at V
DS≈ V
CCSituation under must apply heavily stressed voltage V
CGAt this moment, when applying too high bias voltage to control gate 10 when reducing to programme the time, the stress that is applied on the tunnel oxide 7 increases, thereby the possibility that produces defective is increased, and therefore will produce the problem about product reliability.
In addition, owing to constantly make the extra tunnelling that causes by electronics occur by the electric field that bias voltage produced between control gate 10 and the drain region 6 in programming, thus since the cause of electric field enters floating boom 8 from raceway groove electronics spill in floating boom 8 with the form of leakage current.The size of leakage current depends on coupling capacitance C
FCWith stress voltage V
CGAnd change.When dwindling cell transistor to increase the integrated level of product, reduce programming simultaneously during the time, it is more serious that this problem will become.
As shown in Figure 4, the erase operation of stack gate flash cell is done in such a manner, that is, and and with the threshold voltage reduction Δ V of cell transistor
T, Δ V
TBe V
TEWith V
TPPoor, detect the difference between its numerical value then.Under the situation of all floating, apply V in source region 5 and drain region 6
CG=-V
Pp≈-7.0V and V
B=+V
PpDuring ≈+9.0V, the electric charges that are stored in the floating boom 8 move to raceway groove.This phenomenon is called as Fowler-Nordheim (FN) tunnelling.At this moment, can use as shown in Figure 5 have P trap 42, a P
+Triple-well (triple well) structure of trap 41 and dark N trap 2, thus can realize body bias V
B
When making the charge Q that is stored in the floating boom 8 owing to the FN tunnelling
FCWhen increasing or reducing, the threshold voltage variation Δ V of stack gate flash cell 100
TChange detected amount Δ V
T, and according to detected Δ V
TWhether the information of determining unit is wiped free of.In method for deleting, use sector erase algorithm usually, wherein memory array is divided into a plurality of, and finishes erase operation according to memory array organization on the piece base.At this moment, the programming time of each unit is generally 0.2 mouthful, and the erasing time of each unit be generally 2ms, so carrying out the long period that needs about 100ms under the situation that section wipes.
Following formula has been explained the electric current that is produced by the FN tunnelling:
I
G(A*E
2 OX*Exp(-B/E
OX) (5)
Wherein, A and B are constants, E
OxBe the electric field in the tunnel oxide 7.Thereby obtain following various.
logI
G～E
OX (6)
E
OX＝V
CG/t
OX＝(|V
FG-V
S|)/t
OX (7)
Formula 6 also can be write:
logI
G～(|V
FG-V
S|)/t
OX (8)
Wherein, t
OxThickness for tunnel oxide 7.
In the negative bias erase operation, obtain following formula.
logI
G～(|V
FG-V
S|)/t
OX＝|(a
S-1)V
S+a
G(V
CG-ΔV
T)| (9)
Electric current logI
GBe coupling efficiency a
G, V
CGAnd V
SFunction.Especially, electric current logI as can be seen
GWith V
CGIncrease rapidly pro rata, and with the t of tunnel oxide
OxReduce rapidly pro rata.Therefore, even V as can be seen
CGOnly change 1V, FN tunnelling current logI
GAlso will increase tens times, and the thickness t of tunnel oxide
OxAlso will change sensitively with same degree.Thus, as can be seen, for the CHE scheme, FN tunnelling scheme can be used for programming operation or erase operation effectively.
Above-mentioned stack gate flash cell 100 has following point.
At first, structurally, comprise that the stack gate flash cell 100 of floating boom 8, dielectric layer 9 and control gate 10 has flat structures, so when cell transistor was constantly dwindled, because short-channel effect, this flat structures had limitation.
Secondly, minimize in order to make short-channel effect, stack gate flash cell 100 is necessary through two injection technologies, thereby forms N respectively in source region 5 and drain region 6
+/ N
-Knot.In order to reach this purpose, must additionally form the technology of nitride sidewall spacers layer.
The 3rd, when the flat type stack gate forms, form polysilicon/ONO/ polysilicon by reaction in-situ ion etching (RIE) technology, so that work simplification, thereby the profile of very difficult control gate.
The 4th, when stack gate flash cell 100 being programmed,, Lou disturb or the programming interference so will produce because its drain region 6 is under the high bias voltage by CHE.This is to produce in depletion region when band-band tunnelling (Band-to-Band Tunneling, i.e. BTBT) hot hole, the phenomenon that occurs when being injected into floating boom 8 then, and in depletion region, a plurality of knots overlap mutually.
The 5th, reading under the bias condition of table 1, stack gate flash cell 100 can be used for read operation about 10 to 20 years.In this case, as voltage V
DWhen increasing about 1V, in mechanism, generation is read to disturb, the mechanism of CHE for example, thus produce the problem that the unit that is wiped free of will be regarded as being programmed.
The 6th, when the stack gate flash cell 100 execution sources of wiping under the bias condition knot erase operation in table 1, the BTBT hot hole produces in the depletion region that a plurality of knots overlap mutually and injects in the floating boom 8, and therefore, tunnel oxide 7 is destroyed on sizable degree.Therefore, the problem that reliabilities such as data preservation, circulation are degenerated will be produced.
The 7th, in case when forming the floating boom 8 of stack gate flash cell 100, produce the out-of-alignment situation of image, then will produce undercutting, and when the etching polysilicon, the active area under the polysilicon will be exposed.Then, the active area that exposes in being used to form the RIE technology of floating boom 8 will be affected, thereby produce the ruined problem of substrate.
Therefore, need have a kind of like this flash cell of new construction, it can solve the problem of various stack gate flash cells, improves the integrated level of flash memory products simultaneously.
Summary of the invention
Technical problem:
Therefore, at above-mentioned the problems of the prior art, the purpose of this invention is to provide a kind of flash cell with buried floating gate structure.
Another object of the present invention provides a kind of method of making flash cell.
Technical scheme:
In order to reach above-mentioned first purpose, the invention provides a kind of flash cell, comprising: Semiconductor substrate; Control gate is formed on the described Semiconductor substrate, and is formed by first conducting shell; Dielectric layer is formed between described semiconductor substrate surface and the described control gate; Floating boom is imbedded described Semiconductor substrate under described dielectric layer, and is formed by second conducting shell; Tunnel oxide forms around the interior described floating boom of described Semiconductor substrate; And mutual separated source region and drain region, described floating boom and described tunnel oxide in the described Semiconductor substrate are set between described source region and the described drain region.
According to the preferred embodiments of the invention, the described tunnel oxide that centers on described floating boom has homogeneous thickness or have bigger thickness on the bottom corner portion of described floating boom.Preferably, described source region has different junction depths with described drain region, thereby makes described source region have junction depth less than the degree of depth of described floating boom, and described drain region has the junction depth identical with the degree of depth of described floating boom.Preferably, described source region and described drain region all have the junction depth identical with the degree of depth of described floating boom, less than the junction depth of the degree of depth of described floating boom or greater than the junction depth of the degree of depth of described floating boom.
In order to reach above-mentioned second purpose, the invention provides a kind of method of making flash cell, may further comprise the steps: a plurality of device isolation layers that form the presumptive area exposure that makes Semiconductor substrate; On the surface between described a plurality of device isolation layers, in described Semiconductor substrate, form groove; On the side of described groove, form tunnel oxide; Fill described groove and utilize described first conducting shell to form floating boom with first conducting shell, described floating boom is adjacent with described tunnel oxide; On described floating boom, form dielectric layer; Utilize second conducting shell on described dielectric layer, to form control gate; And the both sides at the described floating boom of described Semiconductor substrate form adjacent with described device isolation layer respectively source region and drain region.
Preferably, each in described first conducting shell and described second conducting shell is made by the polysilicon of polysilicon or doping, and described dielectric layer is formed by the O/N/O layer.In the method, can utilize the floating boom pattern and the control gate pattern that provide separately to form described floating boom and described control gate respectively, or utilize the floating boom pattern that described floating boom is formed that described control gate is formed.
Description of drawings
Detailed description below in conjunction with accompanying drawing will make above-mentioned purpose of the present invention, feature and advantage and other purposes, feature and advantage be more readily understood, wherein:
Fig. 1 is the cutaway view of traditional stack gate flash cell;
Fig. 2 is the circuit diagram of the electronic model of stack gate flash cell shown in Figure 1;
Fig. 3 and Fig. 4 are the performance diagram of stack gate flash cell shown in Figure 1;
Fig. 5 is the schematic diagram of the programming operation of stack gate flash cell shown in Figure 1;
Fig. 6 is the schematic diagram according to the flash cell with buried floating gate structure of first embodiment of the invention;
Fig. 7 is the layout according to first embodiment of the flash cell two-dimensional arrangements of first embodiment of the invention;
Fig. 8 to Figure 14 is the cutaway view along BB ' direction shown in Figure 7, and they are by shown in the order of technology;
Figure 15 to Figure 17 is the cutaway view along AA ' direction shown in Figure 7, and they are by shown in the order of technology;
Figure 18 is the layout according to second embodiment of the flash cell two-dimensional arrangements of first embodiment of the invention;
Figure 19 to Figure 25 is the cutaway view along BB ' direction shown in Figure 180, and they are by shown in the order of technology;
Figure 26 to Figure 28 is the cutaway view along AA ' direction shown in Figure 180, and they are by shown in the order of technology;
Figure 29 is the schematic diagram according to the flash cell with buried floating gate structure of second embodiment of the invention;
Figure 30 is the schematic diagram of the read operation of stack gate flash cell shown in Figure 29;
Figure 31 is the performance diagram of stack gate flash cell shown in Figure 29; And
Figure 32 is the schematic diagram according to the flash cell with buried floating gate structure of third embodiment of the invention.
Embodiment
Describe the preferred embodiments of the invention in detail hereinafter with reference to accompanying drawing.In different accompanying drawings, will adopt same label to represent same or similar element.
Fig. 6 is the schematic diagram according to the flash cell with buried floating gate (hereinafter to be referred as " BFG unit ") of first embodiment of the invention.BFG unit 50 is used to realize highly integrated flash memory.BFG unit 50 has by P trap 54b, P
+Three well structures that trap 54a and dark N trap 52 are formed, thus body-bias (bulk bias voltage) can be applied to the inside of Semiconductor substrate 51.Can utilize two well structures, to replace three well structures with P trap and dark N trap.BFG unit 50 will form at active area, and active area is isolated by trench isolations 53.Floating boom 56 both sides in being buried in Semiconductor substrate 51 are formed with source region 60a and drain region 60b.Between floating boom 56 and source region 60a and drain region 60b, be formed with tunnel oxide 55.On floating boom 56, be formed with dielectric layer 57 and control gate 58, be formed with nitride spacer layer 59 in the both sides of control gate 58.
Work under following bias condition in the BFG unit.Table 2 shows the raceway groove method for deleting, and table 3 shows the source method for deleting.
Table 2
| Pattern | Source (V S) | Control gate (V CG) | Leak (V D) | Body (V B) |
| Read operation | 0V | V cc(4.2V) | V read(0.7V) | 0V |
| Programming operation | 0V | V pp(9V) | V DS(4.75V) | 0V |
| Erase operation | Float | -V pp(-7V) | Float | V pp(9V) |
Table 3
| Pattern | Source (V S) | Control gate (V CG) | Leak (V D) | Body (V B) |
| Read operation | 0V | V cc(4.2V) | V read(0.7V) | 0V |
| Programming operation | 0V | V pp(9V) | V DS(4.75V) | 0V |
| Erase operation | 5V | -V pp(-9V) | Float | 0V |
Fig. 7 is the layout according to first embodiment of the flash cell two-dimensional arrangements of first embodiment of the invention.With reference to Fig. 6, a plurality of active area pattern 61 settings parallel to each other, and on the direction of intersecting with active area pattern 61, a plurality of floating boom patterns 66 are set.In the position identical control gate pattern 68 is set with floating boom pattern 66.In active area pattern 61, be arranged with contact mask pattern 62.
Below will utilize the method for layout description's manufacturing flash cell of Fig. 7.
Fig. 8 to Figure 14 is the cutaway view along BB ' direction shown in Figure 7, they are that Figure 15 to Figure 17 is the cutaway view along AA ' direction shown in Figure 7 by shown in the order of technology, and they are by shown in the order of technology.
As shown in Figure 8, on Semiconductor substrate 51, be formed with pad oxide layer 71, and on pad oxide layer 71, be formed with silicon-nitride layer 72 and tetraethyl orthosilicate (TEOS) layer 73.
As Fig. 9 and shown in Figure 10, in order to be formed with the source region, to utilize the device isolation layer pattern that active area pattern 61 is formed, and utilize active area pattern 61, form first groove 74 by reactive ion etching (RIE) technology.Each first groove 74 is formed up to the degree of depth of about 3000 simplely.With filling insulating material first groove 74, make its planarization by chemical-mechanical planarization (CMP) technology then, thereby form shallow trench isolation from (STI) layer 53.Then, remove pad oxide layer 71, silicon-nitride layer 72 and TEOS layer 73 by wet etching process.
As Figure 11 and shown in Figure 15, in the Semiconductor substrate 51 that is formed with trench isolation layer 53, also be formed with dark N trap 52 and P trap 54.Then, in active area, on the surface of the Semiconductor substrate 51 of unit to be formed grid, utilize the surface of floating boom pattern 66 (as shown in Figure 7), thereby form second groove 75 by RIE etch process etching semiconductor substrate 51.Then, by oxide wet etch technology groove the oxide skin(coating) of separator 53 is partly removed.
As Figure 12 and shown in Figure 16, utilize the dry/wet method for oxidation, on Semiconductor substrate 51, form second groove, 75 places, form the shallow tunnel oxide 55 that thickness is about 10nm.By chemical vapor deposition (CVD) technology, deposit thickness is about the N of 250nm on tunnel oxide 55
+Type first polysilicon layer.Then, remove first polysilicon layer, but keep first polysilicon layer of imbedding in second groove 75 by CMP technology.Isolate mutually between each adjacent floating boom 56, and autoregistration automatically.Floating boom pattern 66 (as shown in Figure 7) can be used as island type or linear pattern.Then, by oxide wet etch technology the oxide skin(coating) of trench isolation layer 53 is partly removed.
As Figure 13 and shown in Figure 17, on the Semiconductor substrate 51 that has formed floating boom 56, deposit the ONO dielectric material by CVD technology, and utilize the CVD method, deposition is used as second polysilicon layer of control gate on the ONO dielectric material.Then, control gate pattern 68 (as shown in Figure 7) is used as mask,, thereby forms dielectric layer 57 and control gate 58 subsequently by RIE etch process etching second polysilicon layer and ONO layer successively.
As shown in figure 14, the impurity (being N type impurity) that conduction type is different from P trap 54 injects in the Semiconductor substrate 51 of floating boom 56 both sides, thus formation source/drain region 60a and 60b.At this moment, further form nitride spacer layer 59, all have N thereby form in the side of control gate 58
-/ N
+The source of type dual structure/ drain region 60a and 60b.
Meanwhile, although the layout of Fig. 7 shows the situation of floating boom pattern 66 and control gate pattern 68 individualisms with as an embodiment, also floating boom pattern 66 and control gate pattern 68 can be merged into single pattern.As shown in figure 18, a plurality of active area pattern 91 settings parallel to each other, and on the direction of intersecting with active area pattern 91, a plurality of floating boom patterns 96 are set.In active area pattern 91, be arranged with contact mask pattern 92 respectively.
Figure 19 to Figure 25 and Figure 26 to Figure 28 show the method that the layout of utilizing Figure 18 is made flash cell.Figure 19 to Figure 25 is the cutaway view along BB ' direction shown in Figure 180, they are that Figure 26 to Figure 28 is the cutaway view along AA ' direction shown in Figure 180 by shown in the order of technology, and they are by shown in the order of technology.Because Figure 19 to Figure 25 is identical with above-described Fig. 8 to Figure 10, so for fear of repetition, will omit the detailed description to these accompanying drawings herein.
As Figure 22 and shown in Figure 26, in the Semiconductor substrate 51 that is formed with trench isolations 53, also be formed with dark N trap 52 and P trap 54, qualification will form the zone of raceway groove, and form pad oxide layer 101 and pad nitride layer 102.Then, utilize floating boom pattern 96 (as shown in figure 18) that pad oxide layer 101 and pad nitride layer 102 are carried out etching, thereby the inside of substrate 51 is revealed, form second groove 105 thus.
As Figure 23 and shown in Figure 27, in second groove 105, be formed with the tunnel oxide 55 of thin thickness to 10nm, be about the N of 250nm by CVD technology filling thickness in will forming second groove 105 of floating boom 56
+The type polysilicon, and the polysilicon of filling carried out etching, thus form floating boom 56.
As Figure 24 and shown in Figure 28, after deposition ONO dielectric material on floating boom 56, utilize the CVD method, deposition is used as second polysilicon layer of control gate 58 on this ONO dielectric material.Then, make this second polysilicon layer and the planarization of ONO layer by eat-backing (etch-back) technology or CMP technology.Preferably, using CMP technology all is favourable in many aspects.This is because removing by CMP technology under the situation of the part pad nitride layer and second polysilicon, only under second polysilicon that forms on the floating boom 56 can be preserved, so control gate 58 can form by self aligned mode.
As shown in figure 25, pad nitride layer 102 is removed, and further forms side wall spacers 59 on two sidewalls of control gate 58.Utilize ion injection method to form N type source region 60a and drain region 60b then.
In Figure 10 and manufacturing process shown in Figure 11, floating boom 56 and control gate 58 all form in self aligned mode.Because floating boom 56 and control gate 58 form in the BFG unit in self aligned mode, the variety of issue that the original position RIE technology that must use in the time of therefore can solving the stack gate unit that forms routine is brought, and can eliminate N
-/ N
+The necessity of two injection technologies and wall 59.In addition, the drain junction depletion region that BTBT takes place is formed under the floating boom 56, thereby can reduce to leak disturbs and eliminate and read to disturb.In addition, inject the degeneration to prevent the tunnel oxide that causes by hot hole when wiping in the source.
Figure 29 is the schematic diagram according to the BFG unit of second embodiment of the invention.As shown in figure 29, compare with BFG unit 50 shown in Figure 6, BFG unit 120 has following difference, promptly, the bottom corner portion of floating boom 122 is processed into circular arc, and the tunnel oxide 121 adjacent with this part forms thicker, and source region 120a forms with drain region 120b has different junction depths.Especially, the junction depth of source region 120a is less than the degree of depth of floating boom 122, and the junction depth of drain region 120b is identical with the degree of depth of floating boom 122.
Under the situation of ground connection in the process at source 120a and body 51 at programming operation, the V that applies
CG=V
PP≈ 9V and V
DSDuring ≈ 4.75V, BFG unit 120 has splitted construction, wherein produces maximum transverse field ' A ' and ' B ' 2.Therefore, can improve the efficient of programming.In addition, even owing to when reading, increase source voltage V
s, the expansion of the depletion region in source region as shown in figure 30 also is limited, so need not to consider to read to disturb.Therefore, as shown in figure 31, because the increase of source voltage, the I-V characteristic of BFG unit 120 becomes curve ' B ' by the curve ' A ' of routine, thereby mutual conductance (GM) is increased, and the ability enhancing that definite program and BFT unit 120 are wiped, thereby reading speed improved.
Figure 32 is the schematic diagram according to the BFG unit of second embodiment of the invention.Shown in figure 32, compare with BFG unit 50 shown in Figure 6, BFG unit 150 has following difference, that is, each among source region 150a and the drain region 150b all forms the junction depth that has less than floating boom 56 degree of depth.Finish the BFG unit 150 of programming operation and erase operation in F-N tunnelling mode and finish the F-N programming operation, and finish the F-N erase operation at drain region 150b at source region 150a.F-N programming operation and F-N erase operation are not finished at the same section of tunnel oxide 55, thereby are improving its reliability aspect the tunnel oxide degraded layer.
Under the bias condition of following table, finish the operation of BFG unit 150.
Table 4
| Pattern | Source (V S) | Control gate (V CG) | Leak (V D) | Body (V B) |
| Read operation | 0V | V cc(4.2V) | V read(0.7V) | 0V |
| Programming operation | -V pp(-7V) | V pp(9V) | Float | -V pp(-7V) |
| Erase operation | Float | -V pp(-7V) | V pp(9V) | Float |
Though, only disclose the preferred embodiments of the invention herein in order to reach illustrative purposes, it will be appreciated by those skilled in the art that under the situation of the scope and spirit that do not break away from claim of the present invention, can carry out various modifications, interpolation and displacement to the present invention.
Industrial usability
Above-mentioned BFG of the present invention unit can increase length of effective channel, thereby promotes unit size to reduce in proportion, and so that is used to form the N in source region and drain region-/N
+Two injection technologies of knot no longer are essential. In addition, different from control gate, floating boom forms by CMP technique in self aligned mode, thus the variety of issue that the original position RIE technique that must use when the BFG unit can solve the flash cell that has smooth stack gate structure when formation is brought. In addition, form under the floating boom at the drain junction depletion region that BTBT occurs, thereby can reduce to leak disturbs and eliminates and read to disturb. In addition, inject the degeneration to prevent the tunnel oxide that caused by hot hole when wiping in the source.
Claims (30)
1. flash cell comprises:
Semiconductor substrate;
Control gate is formed on the described Semiconductor substrate, and is formed by first conducting shell;
Dielectric layer is formed between described semiconductor substrate surface and the described control gate;
Floating boom is imbedded described Semiconductor substrate under described dielectric layer, and is formed by second conducting shell;
Tunnel oxide forms around the interior described floating boom of described Semiconductor substrate; And
Described floating boom and described tunnel oxide in mutual separated source region and the drain region, described Semiconductor substrate are set between described source region and the described drain region.
2. flash cell as claimed in claim 1, wherein the described tunnel oxide around described floating boom has homogeneous thickness.
3. flash cell as claimed in claim 1, wherein the described tunnel oxide around described floating boom has bigger thickness on the bottom corner portion of described floating boom.
4. flash cell as claimed in claim 1, wherein said source region has different junction depths with described drain region.
5. flash cell as claimed in claim 4, wherein said source region has the junction depth less than the degree of depth of described floating boom, and described drain region has the junction depth identical with the degree of depth of described floating boom.
6. flash cell as claimed in claim 1, wherein said source region all has the junction depth identical with the degree of depth of described floating boom with described drain region.
7. flash cell as claimed in claim 1, wherein said source region and described drain region all have the junction depth less than the degree of depth of described floating boom.
8. flash cell as claimed in claim 1, each in wherein said source region and the described drain region all has the junction depth greater than the degree of depth of described floating boom.
9. flash cell as claimed in claim 1, wherein said dielectric layer is formed by oxide/nitride/oxide (O/N/O) layer.
10. method of making flash cell may further comprise the steps:
A plurality of device isolation layers that formation exposes the presumptive area of Semiconductor substrate;
On the surface between described a plurality of device isolation layers, in described Semiconductor substrate, form groove;
On the side of described groove, form tunnel oxide;
Fill described groove with first conducting shell, and utilize described first conducting shell to form floating boom, described floating boom is adjacent with described tunnel oxide;
On described floating boom, form dielectric layer;
Utilize second conducting shell on described dielectric layer, to form control gate; And
Both sides at the described floating boom of described Semiconductor substrate form adjacent with described device isolation layer respectively source region and drain region.
11. the method for manufacturing flash cell as claimed in claim 10, each in wherein said first conducting shell and described second conducting shell is made by the polysilicon of polysilicon or doping.
12. the method for manufacturing flash cell as claimed in claim 10, wherein said dielectric layer is formed by oxide/nitride/oxide.
13. the method for manufacturing flash cell as claimed in claim 10, wherein the described tunnel oxide around described floating boom has homogeneous thickness.
14. the method for manufacturing flash cell as claimed in claim 10, wherein the described tunnel oxide around described floating boom has bigger thickness at the bottom corner portion of described floating boom.
15. the method for manufacturing flash cell as claimed in claim 10, wherein said source region has different junction depths with described drain region.
16. the method for manufacturing flash cell as claimed in claim 15, wherein said source region has the junction depth less than the degree of depth of described floating boom, and described drain region has the junction depth identical with the degree of depth of described floating boom.
17. the method for manufacturing flash cell as claimed in claim 10, wherein said source region all has the junction depth identical with the degree of depth of described floating boom with described drain region.
18. the method for manufacturing flash cell as claimed in claim 10, wherein said source region and described drain region all have the junction depth less than the degree of depth of described floating boom.
19. the method for manufacturing flash cell as claimed in claim 10, each in wherein said source region and the described drain region all has the junction depth greater than the degree of depth of described floating boom.
20. the method for manufacturing flash cell as claimed in claim 10 wherein utilizes the floating boom pattern and the control gate pattern that provide separately to form described floating boom and described control gate respectively.
21. the method for manufacturing flash cell as claimed in claim 10 wherein utilizes the floating boom pattern that forms described floating boom to form described control gate.
22. as claim 1 or 5 described flash cells, wherein by applying voltage to described source region and, described flash cell being programmed with binary message to described floating boom iunjected charge.
23. flash cell as claimed in claim 22 wherein reads the described binary message that is stored in the described flash cell by apply voltage to described source region.
24. as claim 1 or 7 described flash cells, wherein by apply voltage to described source region and from described source region to described floating gate tunneling electric charge, with binary message described flash cell is programmed.
25., wherein wipe the binary message that is stored in the described flash cell by apply the electric charge that voltage and tunnelling be stored in the described floating boom to described drain region as claim 1 or 7 described flash cells.
26. as claim 1 or 7 described flash cells, wherein by the electric charge of tunnelling by the generation of one of described source region and described drain region, binary message is stored in the described floating boom, utilize in described source region and the described drain region another then, by the described electric charge of tunnelling, wipe described binary message.
27. flash cell as claimed in claim 1 wherein forms described floating boom by chemical-mechanical planarization (CMP) technology.
28. flash cell as claimed in claim 1 wherein forms described control gate by chemical-mechanical planarization technology.
29. the method for manufacturing flash cell as claimed in claim 10, the step that wherein forms described floating boom is utilized chemical-mechanical planarization technology.
30. the method for manufacturing flash cell as claimed in claim 10, the step that wherein forms described control gate is utilized chemical-mechanical planarization technology.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020050011803A KR100675516B1 (en) | 2005-02-14 | 2005-02-14 | Flash memory cell having buried floating gate and fabrication method thereof |
| KR1020050011803 | 2005-02-14 |
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| Publication Number | Publication Date |
|---|---|
| CN101111939A true CN101111939A (en) | 2008-01-23 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2006800038515A Pending CN101111939A (en) | 2005-02-14 | 2006-01-24 | Flash memory cell having buried floating gate structure and method of manufacturing the same |
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| Country | Link |
|---|---|
| EP (1) | EP1849188A1 (en) |
| JP (1) | JP2008529298A (en) |
| KR (1) | KR100675516B1 (en) |
| CN (1) | CN101111939A (en) |
| WO (1) | WO2006085718A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102237313A (en) * | 2010-04-29 | 2011-11-09 | 武汉新芯集成电路制造有限公司 | Flash memory device and manufacturing method thereof |
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| KR100830339B1 (en) | 2006-12-27 | 2008-05-19 | 동부일렉트로닉스 주식회사 | Flash memory device |
| KR100894683B1 (en) | 2007-08-28 | 2009-04-24 | 경북대학교 산학협력단 | High performance 1T-DRAM cell device and manufacturing method thereof |
| JP2009146497A (en) * | 2007-12-13 | 2009-07-02 | Renesas Technology Corp | Semiconductor device |
| US9230977B2 (en) | 2013-06-21 | 2016-01-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Embedded flash memory device with floating gate embedded in a substrate |
| CN105097953B (en) * | 2014-05-13 | 2018-08-03 | 中芯国际集成电路制造(上海)有限公司 | Half floating gate transistor structures |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5315142A (en) * | 1992-03-23 | 1994-05-24 | International Business Machines Corporation | High performance trench EEPROM cell |
| KR0166840B1 (en) * | 1995-05-12 | 1999-01-15 | 문정환 | Semiconductor device having a recess channel structure |
| JPH09330988A (en) * | 1996-06-11 | 1997-12-22 | Sony Corp | Laminated gate-type non-volatile semiconductor memory device |
| TW385550B (en) * | 1998-05-27 | 2000-03-21 | United Microelectronics Corp | Electrically erasable programmable read only flash memory |
| JP3664884B2 (en) * | 1998-08-11 | 2005-06-29 | 松下電器産業株式会社 | Semiconductor memory device and manufacturing method thereof |
| JP3303789B2 (en) * | 1998-09-01 | 2002-07-22 | 日本電気株式会社 | Flash memory and its writing / erasing method |
| JP2000200840A (en) * | 1999-01-06 | 2000-07-18 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
| JP2001007225A (en) * | 1999-06-17 | 2001-01-12 | Nec Yamagata Ltd | Non-volatile semiconductor storage device and manufacture thereof |
| JP2001118939A (en) * | 1999-10-15 | 2001-04-27 | Sharp Corp | Nonvolatile semiconductor memory and manufacturing method therefor |
| JP2002118183A (en) * | 2000-10-10 | 2002-04-19 | Toshiba Corp | Non-volatile semiconductor memory |
| JP2002134634A (en) * | 2000-10-25 | 2002-05-10 | Nec Corp | Semiconductor device and its manufacturing method |
| JP2002158299A (en) * | 2000-11-17 | 2002-05-31 | Toshiba Corp | Semiconductor storage device and manufacturing method thereof |
-
2005
- 2005-02-14 KR KR1020050011803A patent/KR100675516B1/en not_active IP Right Cessation
-
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- 2006-01-24 CN CNA2006800038515A patent/CN101111939A/en active Pending
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| CN102237313A (en) * | 2010-04-29 | 2011-11-09 | 武汉新芯集成电路制造有限公司 | Flash memory device and manufacturing method thereof |
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| KR20060091332A (en) | 2006-08-21 |
| KR100675516B1 (en) | 2007-01-30 |
| JP2008529298A (en) | 2008-07-31 |
| WO2006085718A1 (en) | 2006-08-17 |
| EP1849188A1 (en) | 2007-10-31 |
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