KR20060091332A - Flash memory cell having buried floating gate and fabrication method thereof - Google Patents

Abstract

The present invention discloses a flash memory cell having a buried floating gate structure and a method of manufacturing the same. The flash memory cell of the present invention includes a control gate formed on the semiconductor substrate and formed of a first conductive film, a dielectric film formed between the surface of the semiconductor substrate and the control gate, and embedded in a semiconductor substrate under the dielectric film and having a second conductivity. A floating gate formed of a film, a floating gate formed inside the semiconductor substrate, and surrounded by a thicker tunnel oxide film at the bottom corner of the floating gate, and spaced apart between the floating gate and the tunnel oxide film in the semiconductor substrate. Includes source and drain. The junction depths of the source and drain are different, so the junction depth of the source may be shallower than the depth of the floating gate and the junction depth of the drain may be the same as the depth of the floating gate. Alternatively, the junction depth of the source and drain of the flash memory cell may be the same as that of the floating gate, such that the junction depth of the source and drain may be shallower than the depth of the floating gate, or the junction depth of the source and drain may be deeper than the depth of the floating gate. .

Flash memory cell, buried floating gate, tunnel oxide, source drain junction depth

Description

Flash memory cell having a buried floating gate structure and a method of manufacturing the same {Flash memory cell having buried floating gate and fabrication method

1 is a cross-sectional view illustrating a conventional stack gate flash cell.

FIG. 2 is a diagram illustrating an electronic model of the stack gate flash memory cell of FIG. 1.

3A and 3B are graphs illustrating characteristics of the stacked gate flash memory cell of FIG. 1.

4 is a diagram illustrating a programming operation of the stack gate flash memory cell of FIG. 1.

FIG. 5 is a diagram illustrating a flash memory cell having a buried floating gate according to a first embodiment of the present invention.

FIG. 6 is a layout diagram of a first example in which the flash memory cells of FIG. 5 are two-dimensionally arranged.

7A to 7G are cross-sectional views illustrating the process sequence according to BB ′ of FIG. 6.

8D to 8F are cross-sectional views illustrating the process sequence in accordance with AA ′ of FIG. 6.

9 is a layout diagram of a second example in which the flash memory cells of FIG. 5 are two-dimensionally arranged.

10A to 10G are cross-sectional views illustrating the process sequence according to BB ′ of FIG. 9.

11D through 11F are cross-sectional views sequentially illustrating the process according to AA ′ of FIG. 9.

12 is a view for explaining a flash memory cell having a buried floating gate according to a second embodiment of the present invention.

FIG. 13 is a view illustrating a read operation of the flash memory cell of FIG. 12.

14 is a graph illustrating characteristics of the flash memory cell of FIG. 12.

FIG. 15 illustrates a flash memory cell having a buried floating gate according to a third embodiment of the present invention.

TECHNICAL FIELD The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a flash memory cell having a buried floating gate structure and a method of manufacturing the same.

The flash memory device has a feature that information stored in a memory cell is not destroyed even when power is not supplied. Therefore, it is widely adopted in memory cards and the like used in computers. A unit cell of a typical flash memory device has a gate structure in which a floating gate and a control gate electrode are sequentially stacked.

1 is a cross-sectional view illustrating a conventional stack gate flash cell. Referring to this, in the stack gate flash memory cell 100, a ◎ -N-well 2, a P-well 4, and a trench isolation part 2 are formed in the semiconductor substrate 1. (1) A source region 5 and a drain region 6 spaced apart from each other with a channel region interposed therebetween, and a tunnel oxide film 7, a floating gate FG, and a dielectric thin film on the channel region. (9) and control gate electrodes CG and 10 are stacked in this order. The dielectric thin film 9 is composed of an oxide-nitride-oxide (ONO) film. The source region 5 and the drain region 6 are formed in an N ⁺ / N ⁻ junction structure formed using the spacer 11.

FIG. 2 is a diagram illustrating an electronic model of the stack gate flash memory cell of FIG. 1. Referring to this, C _FC is the capacitance by the ONO dielectric thin film 9 between the control gate (CG, 10) and the floating gate (FG, 8), C _S is the source junction 5 and the floating gate (FG, 8) ) and the parasitic capacitance generated between, C _D is the drain junction 6 and the floating gate (and the parasitic capacitance generated between FG, 8), C _B is the floating gate (FG, 8) and the semiconductor substrate (B, 1) between It is a parasitic capacitance that occurs at. Here, if C _T = C _FC + C _S + C _B + C _D , since C _S and C _D values are very small compared to C _FC and C _B , it is usually C _T = C _FC + C _B. The parasitic coupling ratio generated between each node can be defined as follows. The parasitic coupling ratio of the source junction 5 is a _S = C _S / C _T , the parasitic coupling ratio of the drain junction 6 is a _D = C _D / C _T , and the floating gate (FG, 8) The parasitic coupling ratio of can be represented by a _G = C _FC / C _T.

In addition, V _CG , V _FS , V _S , V _DS and V _B are the control gates CG and 10, the floating gates FG and 8, the source junction 5, the drain junction 6, and the semiconductor substrate B, respectively. , And the bias voltage across 1), where V _FS is a function of V _CG and V _DS .

A charge (charge) stored in the floating gate (FG, 8) is the less the smaller the parasitic coupling ratio (a _G) of the floating gate, the higher the V _DS can be seen that many,.

Here, since the floating gates FG and 8 are not directly electrically accessible, the floating gates FG and indirectly may be indirectly used by controlling the V _CG voltage of the control gate CG 10 which is electrically accessible. V _FG of 8) is controlled.

는 다음 과 같이 표현 된다.At this time, transition of V _T ^CG of the cell transistor

Is expressed as

는 Q_FC에 비례 하고, C_FC에 반비례 한다는 것을 알 수 있다.

It can be seen that is proportional to Q _FC and inversely proportional to C _FC .

)을 측정하여 구현한다. 독출, 프로그램 및 삭제 동작을 하기 위한 각각의 바이어스 전압 레벨은 다음과 같다.Read, program, and erase operations of the stack gate flash cell 100 may be performed by applying an appropriate bias voltage between the source, drain, gate, and bulk, thereby shifting the threshold voltage of the cell,

) Is implemented. The bias voltage levels for read, program and erase operations are as follows.

mode

Read action 0 V Vcc (4.2V) Vread (0.7V) 0 V Program behavior 0 V Vpp (9 V) V _DS (4.75V) 0 V Delete action Floating -Vpp (-7V) Floating Vpp (9 V)

In the read operation of the stack gate flash memory cell 100, as shown in FIGS. 3A and 3B, the threshold voltage V _T of a cell transitioned by charge injection is measured and the value is referred to as a reference cell. compare with the threshold voltage of the cell). To do this, apply V _CG = V _CC ◎ 4.2 V, ie V _TE <V _CG <V _TP , with the source (5) and bulk (1) of this cell grounded respectively, and V _DS = V _READ By applying a voltage of about 1.0 V, the drain current I _D of this cell transistor is measured to distinguish whether the cell is programmed or deleted.

만큼 올려 주고 이를 센싱하여 이루어진다. 스택 게이트 플래쉬 메모리 셀(100)을 프로그램하기 위하여, 소스(5)와 벌크(1)가 접지된 상태에서, V_CG = VPP ◎9 V를 가하고 V_DS ◎4.75V를 인가하게 되면, 전자가 플로팅 게이트(8)의 아래의 소스 영역(5)쪽에서 채널을 따라 드레인 영역(6)쪽으로 이동하게 된다. 이때, 전자가 채널을 따라 형성되는 수평 전장 (transverse electric field)에 의해 가속되면서 충분한 에너지를 얻게 되면 (Channel Hot Electron), 도 4에서 보는 바와 같이, 드레인 영역(6) 부근에서 수직전장(vertical electric field)에 의하여, 플로팅 게이트(FG, 8) 쪽으로 전자들이 유입된다. 유입되는 채널 핫 일렉트론(Channel Hot Electron: CHE)에 의하여 셀 트랜지스터의 문턱 전압 전압이 수학식 3에서 보는 바와 같이,

만큼 천이(shift) 된다. 이 때에 플로팅 게이트(FG, 8)로 유입되는 전류 I_G는The programming operation of the stack gate flash memory cell 100 may vary the threshold voltage of the cell transistor from V _TE to V _TP , as shown in FIG. 3B.

It is done by raising it and sensing it. In order to program the stack gate flash memory cell 100, when the source 5 and the bulk 1 are grounded, when V _CG = VPP? 9 V is applied and V _DS ? 4.75 V is applied, the electrons float. It moves from the source region 5 below the gate 8 to the drain region 6 along the channel. At this time, if electrons are accelerated by a transverse electric field formed along the channel (Channel Hot Electron), as shown in FIG. 4, the vertical electric field is near the drain region 6. By the field, electrons flow into the floating gate FG 8. As shown in Equation 3, the threshold voltage voltage of the cell transistor is caused by the channel Hot Electron (CHE) flowing therein.

Shift by. At this time, the current I _G flowing into the floating gate FG 8 is

는 프로그램 시간이고,

는

에 따라 변한다. 그리고,

는 다음과 같은 변수들에 의해 민감하게 변한다.From here,

Is the program time,

Is

Depends on. And,

Is sensitively affected by the following variables.

i) control gate voltage V _CG , drain voltage V _DS,

ii) the coupling ratio a _G and C _FC between the control gate (CG) and the floating gate (FG) _,

iii) channel length and channel width of the cell transistor

iv) temperature

는 스택 게이트 플래쉬 메모리 셀에서 유효 채널 길이(L_eff)은 작 을 수록, 터널 산화막(t_ox, 7)는 얇을수록, C_FC는 클수록, 그리고 V_CG 나 V_SD는 높을수록 커진다. 이에 따라 프로그램 시간도 빨라진다. In other words,

The smaller the effective channel length L _eff , the thinner the tunnel oxide layer t _ox , 7, the larger C _FC , and the higher V _CG or V _SD in the stack gate flash memory cell. This also speeds up program time.

In the stack gate flash memory cell 100, the programming method by CHE is performed by applying a stress voltage between the control gate CG and the drain 6 while the source 5 is grounded. Must apply high V _CG stress voltage at VDS VC VCC. At this time, if a bias voltage that is too high is applied to the control gate (CG) 10 in order to reduce the program time, the stress applied to the tunnel oxide film 7 is increased, thereby increasing the probability of failure, thereby causing problems in product reliability. Can cause.

The electrons introduced into the floating gate FG in the channel by the electric field are generated by the electric field generated by the bias voltage between the control gate CG 10 and the drain 6 during programming. Due to incidental tunneling, it exits the floating gate (FG) 8 in the form of a leakage current. The magnitude of this leakage current depends on the coupling capacitances C _FC and V _CG stress voltages. These problems are exacerbated by continuously shrinking cell transistors to increase product density and reduce program time at the same time.

만큼 낮추어 준 뒤, 이 차이값을 센 싱하여 이루어진다. 소스(5)와 드레인(6)이 각각 플로팅된 상태에서 V_CG = - Vpp ◎-7.0V 와 V_B = +Vpp ◎+9.0 V를 인가하게 되면, 플로팅 게이트(FG, 8)에 저장된 전하가 채널쪽으로 빠져 나가게 되는데, 이러한 현상을 FN 터널링(Fowler-Nordheim (FN) tunnel mechanism)이라고 한다. 이때 벌크 바이어스(V_B)를 가능하게 하기 위해서, 도 4에 도시된 바와 같이 P-월(42), P⁺-웰(41), ◎-N-웰(2) 형태의 트리플 웰 구조를 사용하기도 한다.The erase operation of the stack gate flash memory cell may change the threshold voltage of the cell transistor from V _TE to V _TP as shown in FIG. 3B.

It is lowered by and then sensed by this difference. When V _CG =-Vpp ◎ -7.0V and V _B = + Vpp ◎ +9.0 V are applied while the source 5 and the drain 6 are respectively floated, the charge stored in the floating gate FG, 8 It exits into the channel, which is called the Fowler-Nordheim (FN) tunnel mechanism. In this case, in order to enable the bulk bias (V _B ), a triple well structure in the form of a P-wall 42, a P ⁺ -well 41, and a --N-well 2 is used as shown in FIG. 4. Sometimes.

만큼 천이된다. 이 천이된

를 감지하여 셀의 삭제 여부를 판단하게 된다. 이 삭제 방식은 메모리 어레이의 아키텍쳐에 따라서, 메모리 어레이를 여러 개의 블락 들로 나누어서 블락별로 삭제하는 섹터 삭제 방식이 보편적으로 쓰이며, 이때 셀 당 프로그래밍 시간은 보통 0.2㎲ 정도이고 삭제 시간은 보통 2ms 정도이므로, 섹터를 삭제할 경우 약 100 msec 정도의 긴 시간을 필요로 한다.When the charge Q _FC stored in the floating gate FG 8 increases or decreases due to the FN tunneling phenomenon, the threshold voltage of the stack gate flash memory cell 100 may increase.

As long as the transition. This transitioned

Detect and determine whether to delete the cell. According to the architecture of the memory array, the sector erase method of dividing the memory array into blocks and deleting block by block is commonly used. In this case, the programming time per cell is usually about 0.2 ms and the erase time is about 2 ms. For example, deleting a sector requires a long time of about 100 msec.

The current generated by FN tunneling is as follows.

는 터널 산화막(7)에서의 전계(electric field)를 나타낸다. 이에 따라,Where A and B are constants,

Denotes an electric field in the tunnel oxide film 7. Accordingly,

ego,

It can be represented as.

Reexpression of Equation 6 as follows:

Here, t _OX is the thickness of the tunnel oxide film 7.

In the erase operation of negative gate bias

Appears. The current logI _G is the coupling ratio a _G and V _CG , V _S It can be seen that it is a function, especially increasing rapidly in proportion to V _CG , and rapidly decreasing in inverse proportion to the tunnel oxide film t _OX . Therefore, it can be seen that even if V _CG changes only 1V, the FN tunneling current logI _G increases by several multiples of 10, and it is also sensitive to changes in the tunnel oxide thickness t _OX . From this, it can be seen that the FN tunneling method can be used more effectively for program operation or deletion operation than the CHE method.

The stack gate flash memory cell 100 described above has the following problems.

First, the stack gate flash memory cell 100 has a flat structure in the form of a floating gate 8 / dielectric film 9 / control gate 10 due to its structure. channel), we are hitting the limit.

Secondly, the stack gate flash memory cell 100 has a double implantation process to make N ⁺ / N ⁻ junctions in the source 5 / drain 6 to minimize the short channel effect. To this end, a nitride sidewall spacer process should be added.

Third, when forming a flat stack gate, it is difficult to control the gate profile because polysilicon / ONO / polysilicon is formed by an in-situ RIE etching process to simplify the process. .

Fourth, when the stack gate flash memory cell 100 is programmed by CHE, drain drain or programming disturb occurs because the drain 6 needs to be stressed with a high bias voltage. . This is a phenomenon that occurs when hot electrons are formed by band-to-band tuning (BTBT) in the depletion region of the overlapped portion and injected into the floating gate 8.

전압이 1V 이상으로 높아지게 되면 CHE와 같은 메카니즘으로 독출 디스털브(read disturb)를 받게 되어 삭제된 셀이 프로그램된 것처럼 판단되는 문제가 발생한다.Fifth, the stack gate flash memory cell 100 performs a read operation for about 10 to 20 years under the read bias condition of Table 1.

When the voltage rises above 1 V, a mechanism such as CHE causes read disturb, which causes the deleted cell to be judged as programmed.

Sixth, the stack gate flash memory cell 100 performs a BTBT (Band-to-Band Tunneling) hot hole in the depletion region where the junction overlaps when the source junction erase operation is performed under the erase bias condition of Table 1. A hot hole is formed and flows into the floating gate FG 8 so that the tunnel oxide film 7 is greatly damaged. Accordingly, problems such as poor data reliability and cycling occur.

Seventh, if the photo gate misalignment occurs when the floating gate 8 is formed, the stack gate flash memory cell 100 generates an undercut when etching the polysilicon. The active area is exposed. Thereafter, the exposed active region is affected during the reactive ion etching (RIE) process for forming the floating gate 8, thereby causing substrate damage.

Therefore, there is a need for a flash memory cell having a new structure that can increase the density of flash memory products and at the same time can solve various problems of the stack gate flash memory cell.

It is an object of the present invention to provide a flash memory cell of an embedded floating gate structure.

Another object of the present invention is to provide a method of manufacturing the flash memory cell.

In order to achieve the above object, the flash memory cell of the present invention comprises a semiconductor substrate; A control gate formed on the semiconductor substrate and formed of a first conductive film; A dielectric film formed between the surface of the semiconductor substrate and the control gate; A floating gate embedded in the semiconductor substrate under the dielectric film and formed of a second conductive film; A tunnel oxide layer formed to surround the floating gate inside the semiconductor substrate; And a source and a drain spaced apart from each other with the floating gate and the tunnel oxide layer in the semiconductor substrate interposed therebetween.

According to preferred embodiments of the present invention, it is preferable that the flash memory cell has a uniform thickness of the tunnel oxide film surrounding the floating gate or is thicker at the bottom corner portion of the floating gate. In the flash memory cell, the junction depths of the source and the drain are different from each other, so that the junction depth of the source is shallower than the depth of the floating gate, and the junction depth of the drain is equal to the depth of the floating gate. Alternatively, the flash memory cell may be formed such that the junction depth of the source and drain is the same as that of the floating gate, the junction depth of the source and the drain is shallower than the depth of the floating gate, or the junction depth of the source and the drain is deeper than the depth of the floating gate. Do.

In order to achieve the above another object, the flash memory cell manufacturing method of the present invention comprises the steps of forming an isolation film exposing a predetermined region of the semiconductor substrate; Forming a trench on a surface of the semiconductor substrate between device isolation layers; Forming a tunnel oxide layer on the side of the trench; Forming a floating gate with a first conductive film filling the trench while being in contact with the tunnel oxide film; Forming a dielectric film on the floating gate; Forming a control gate as a second conductive film on the dielectric film; And forming source and drain regions in contact with the device isolation foil on both sides of the floating gate of the semiconductor substrate.

Preferably, the first or second conductive film is formed of polysilicon or doped polysilicon, and the dielectric film is formed of an oxide / nitride / oxide (O / N / O) film. The flash memory cell manufacturing method includes a floating gate pattern for forming a floating gate and a control gate pattern for forming a control gate to form a floating gate and a control gate, or a control gate using a floating gate pattern for forming a floating gate. Can be formed.

Thus, BFG cell of the present invention is an effective channel length (Effective Channel Length) can increase the I-scale cell-Double for creating / N ^{+ junction-down} (scale-down) is easy and, N of the source and drain regions No implant process is required. Since the floating gate is self-aligned unlike the control gate by the CMP process, the BFG cell can solve the burden of the in-situ RIE etching process, which is essential when forming a flash memory cell having a flat stack gate structure. have. In addition, the BFG cell can reduce the drain distal burn and eliminate the read distal burn by forming the drain junction depletion region where the BTBT is generated beneath the floating gate. In addition, it is possible to prevent degradation of the tunnel oxide film due to hot holes when the source junction is deleted.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings that describe exemplary embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

5 is a view for explaining a buried floating gate cell (hereinafter referred to as a "BFG cell") according to a first embodiment of the present invention. The BFG cell 50 is used to implement a highly integrated flash memory. The BFG cell 50 has a triple well structure in the form of a P-well 54b, a P ⁺ -well 54a, and a ◎ -N-well 52 to enable bulk biasing in the semiconductor substrate 51. . Instead of the triple well structure, a twin well structure having a P-well and a ◎ -N well structure may be employed. The active region where the BFG cell 50 is to be formed is separated by trench isolation 53. Source and drain regions 60a and 60b are formed at both sides of the floating gate 56 embedded in the semiconductor substrate 51. A tunnel oxide film 55 is formed between the floating gate 56 and the source and drain regions 60a and 60b. A dielectric film 57 and a control gate 58 are formed on the floating gate 56, and a nitride film spacer 59 is formed on the side of the control gate.

The operation of the BFG cell is performed under the following bias conditions. Table 2 shows a channel erase method, and Table 3 shows a source erase method.

mode

)sauce(

) Control gate

) drain(

) bulk(

) Read action 0 V Vcc (4.2V) Vread (0.7V) 0 V Program behavior 0 V Vpp (9 V) V _DS (4.75V) 0 V Delete action Floating -Vpp (-7V) Floating Vpp (9 V)

mode

)sauce(

) Control gate

) drain(

) bulk(

) Read action 0 V Vcc (4.2V) Vread (0.7V) 0 V Program behavior 0 V Vpp (9 V) V _DS (4.75V) 0 V Delete action 5 V -Vpp (-9V) Floating 0 V

FIG. 6 is a layout diagram in which the flash memory cells of FIG. 5 are two-dimensionally arranged. Referring to this, the plurality of active region patterns 61 may be arranged in parallel with each other, and the plurality of floating gate patterns 66 may be disposed along the direction crossing the active region pattern 61. The control gate pattern 68 is disposed at the same position as the floating gate pattern 66. The contact mask pattern 62 is arranged in each active region pattern 61.

Next, a flash memory cell manufacturing method will be described using the layout diagram of FIG. 6.

7A to 7G are cross-sectional views illustrating the process sequence according to BB ′ of FIG. 6, and FIGS. 8D to 8F are cross-sectional views illustrating the process sequence according to AA ′ of FIG. 6.

Referring to FIG. 7A, a pad oxide film 71 is formed on a semiconductor substrate 51, and a silicon nitride film 72 and a TEE (TetraEthylOrthoSilicate) film 73 are deposited on the pad oxide film 71.

Referring to FIGS. 7B and 7C, an active region pattern 61 (FIG. 6) is formed using an isolation layer pattern to form an active region, and then a reactive ion etching (RIE) is etched using the active region pattern 61. The first trench 74 is formed through the process. The first trench 74 is formed shallow to a depth of about 3000 mm 3. The first trench 74 is filled with an insulating material and then planarized by a chemical mechanical planarization (CMP) process to form trench isolation (STI) 53. Thereafter, the pad oxide film 71, the silicon nitride film 72, and the TEOS (Tetra Ethyl Ortho Silicate) film 73 are removed through a wet etching process.

7D and 8D, the? -N well 52 and the P-well 54 are formed in the semiconductor substrate 51 in which the trench isolation 53 is formed, and then the surface of the semiconductor substrate 51 is formed. The second trench 75 is formed on the surface of the semiconductor substrate 51 by RIE etching using the floating gate pattern 66 (see FIG. 6) in the active region where the cell gate is to be formed. Thereafter, the oxide layer of the trench isolation 53 is slightly removed through the oxide wet etching process.

Referring to FIGS. 7E and 8E, the tunnel oxide layer 55 is formed to be about 10 nm thin by using a dry / wet oxidation method over the semiconductor substrate 51 on which the second trench 75 is formed. After depositing an N ⁺ -type first polysilicon layer having a thickness of 250 nm on the tunnel oxide layer 55 by CVD (Chemical Vapor Deposition) process, the first polysilicon layer is removed to some extent by a CMP process, but the second trench 75 is removed. The first polysilicon embedded therein is left. By this process, the floating gates 56 of the cells adjacent to each other are isolated and self-aligned automatically. The floating gate pattern 66 (FIG. 6) may be used as an island type or a straight type. Thereafter, the oxide film of the trench isolation 53 is slightly removed through the oxide wet etching process.

7F and 8F, an oxide / nitride / oxide (ONO) dielectric material is deposited by a CVD process on a semiconductor substrate 51 on which the floating gate 56 is formed, and then a control gate on the ONO dielectric material. The second polysilicon to be used is deposited by the CVD method. Thereafter, using the control gate pattern 68 (Fig. 6) as a mask, the second polysilicon film and the ONO film are etched continuously through the RIE etching process to form the dielectric film 57 and the control gate 58.

Referring to FIG. 7G, source / drain regions 60a and 60b are implanted into the semiconductor substrate 51 on both sides of the floating gate 56 by implanting impurities of another conductivity type, that is, N-type impurities, with the P-well 54. ). In this case, the spacer 59 of the nitride film may be further formed on the side of the control gate 58 to form the N // N + type double structure source / drain regions 60a and 60b.

6 illustrates a case in which the floating gate pattern 66 and the control gate pattern 68 exist separately, but the floating gate pattern 66 and the control gate pattern 68 are the same. It can also be configured. Referring to FIG. 9, a plurality of active region patterns 91 are disposed in parallel to each other, and a plurality of floating gate patterns 96 are disposed along a direction crossing the active region pattern 91. The contact mask pattern 92 is arranged in each active region pattern 91.

A flash memory cell manufacturing method using the layout diagram of FIG. 9 is illustrated in FIGS. 10A to 10G and 11D to 11F. 10A to 10G are cross-sectional views illustrating the process sequence according to BB ′ of FIG. 9, and FIGS. 11D to 11F are cross-sectional views illustrating the process sequence according to AA ′ of FIG. 9. Here, FIGS. 10A to 10C are the same as FIGS. 7A to 7C described above, and detailed descriptions thereof are omitted in order to avoid duplication of description.

Referring to FIGS. 10D and 11D, the? -N well 52 and the P-well 54 are formed in the semiconductor substrate 51 in which the trench isolation 53 is formed, and then a region in which the channel is to be formed is defined. The pad oxide film 101 and the pad nitride film 102 are formed. Next, the pad oxide layer 101 and the pad nitride layer 102 are etched to the inside of the substrate using the floating gate pattern 96 (see FIG. 9) to form the second trench 105.

10E and 11E, the tunnel oxide film 55 is formed to be about 10 nm thin inside the second trench 105, and then the floating gate 56 is formed on the tunnel oxide film 55 by a CVD process. The inside of the second trench 105 to be deposited is formed of N ⁺ -type first polysilicon having a thickness of about 250 nm and etched to form a floating gate 56.

10F and 11F, deposit an Oxide / Nitride / Oxide (ONO) dielectric material 103 over the floating gate 56 and then onto the control gate 58 over the ONO dielectric material 103. The second polysilicon film to be used is deposited by the CVD method. Thereafter, the second polysilicon film and the ONO film are etched back or planarized by a CMP process. Preferably, the CMP process is used in many ways. Because when the CMP process is used to remove not only the second polysilicon layer but also a part of the pad nitride layer, only the second polysilicon on the floating gate 56 may be left, so that the control gate 58 is self-aligned. This is because it can be formed in an align method.

Referring to FIG. 10G, the pad nitride layer 102 is stripped, and sidewall spacers 59 are formed on both sidewalls of the control gate 58, and the N type source / drain regions 60a, 60b).

 In the manufacturing process of FIGS. 10 and 11, both the floating gate 56 and the control gate 58 are self-aligned. The BFG cell in which the floating gate 56 and the control gate 58 are self-aligned can solve the burden of in-situ RIE etching process, which is essential when forming a conventional stack gate cell. Rather, it eliminates the need for a double implantation process of N- / N + and the spacer 59 structure. In addition, a drain junction depletion region in which BTBT is generated is formed under the floating gate 56, thereby reducing drain disturbance and eliminating read disturbance. Can be. In addition, it is possible to prevent tunnel oxide degradation due to hot holes at the time of source injection erase.

12 is a diagram illustrating a BFG cell according to a second embodiment of the present invention. Referring to this, in comparison with the BFG cell 50 of FIG. 5, the BFG 120 is rounded at the bottom corner of the floating gate 122, so that the thickness of the tunnel oxide film 121 in contact with the portion is increased. The thickness is different, and the junction depths of the source and drain regions 120a and 120b are different from each other. In particular, the junction depth of the source region 120a is smaller than the depth of the floating gate 122, and the junction depth of the drain region 120b is formed to the depth of the floating gate 122.

When the BFG cell 120 applies V _CG = VPP ◎ 9 V and applies V _DS ◎ 4.75 V while the source 120a and the bulk 51 are grounded during the program operation, the maximum lateral field (Max Lateral) is applied. field) has a split structure in two places (A and B). Accordingly, program efficiency can be increased. As shown in FIG. 13 during the read operation, the BFG cell 120 has a limited readout disturbance since the expansion of the depletion region of the source region is limited even when the source voltage Vs is increased. There is no fear of). Accordingly, as shown in FIG. 14, the IV characteristic of the BFG cell 120 is shifted from A, which is a conventional curve, to B by an increase in the source voltage, thereby increasing the transconductance (GM), thereby increasing the BFG cell 120. The read speed is improved because the ability to determine the program or deletion is increased.

15 is a diagram illustrating a BFG cell 150 according to a third embodiment of the present invention. Referring to this, the BFG cell 150 is different from the BFG cell 50 of FIG. 5 in that the junction depth of the source and drain regions 150a and 150b is formed to be shallower than the depth of the floating gate 56. There is. The BFG cell 150 performs the F-N tunneling method for both the program operation and the erase operation. The BFG cell 150 performs F-N programming in the source region 150a and F-N deletion in the drain region 150b. Since the F-N program and the deletion are not made in the tunnel oxide film 55 in the same portion, the reliability characteristics of the deterioration side of the tunnel oxide film are good.

Operation of the BFG cell 150 is performed under the following bias conditions.

mode

)sauce(

) Control gate

) drain(

) bulk(

) Read action 0 V Vcc (4.2V) Vread (0.7V) 0 V Program behavior -Vpp (-7V) Vpp (9 V) Floating -Vpp (-7V) Delete action Floating -Vpp (-7V) Vpp (9 V) Floating

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

A BFG cell of the present invention described above is an effective channel length (Effective Channel Length) can increase the I-scale cell-Double for creating / N ^{+ junction-down} (scale-down) it is easy and, N of the source and drain regions No implant process is required. In addition, since the floating gate is self-aligned unlike the control gate by the CMP process, the BFG cell can solve the in-situ RIE etching process, which is essential when forming a flash memory cell having a flat stack gate structure. . In addition, the BFG cell can reduce the drain distal burn and eliminate the read distal burn by forming the drain junction depletion region where the BTBT is generated beneath the floating gate. In addition, it is possible to prevent degradation of the tunnel oxide film due to hot holes when the source junction is deleted.

Claims (30)

Semiconductor substrates; A control gate formed on the semiconductor substrate and formed of a first conductive film; A dielectric film formed between the surface of the semiconductor substrate and the control gate; A floating gate embedded in the semiconductor substrate under the dielectric layer and formed of a second conductive layer; A tunnel oxide layer formed to surround the floating gate in the semiconductor substrate; And And a source and a drain spaced apart from each other with the floating gate and the tunnel oxide layer interposed therebetween in the semiconductor substrate. The method of claim 1, wherein the flash memory cell And a thickness of the tunnel oxide layer surrounding the floating gate is uniform. The method of claim 1, wherein the flash memory cell And a thickness of the tunnel oxide layer surrounding the floating gate is thicker at a bottom corner of the floating gate. The method of claim 1, wherein the flash memory cell And the junction depths of the source and the drain are different from each other. The method of claim 4, wherein the flash memory cell And the junction depth of the source is shallower than the depth of the floating gate, and the junction depth of the drain is the same as the depth of the floating gate. The method of claim 1, wherein the flash memory cell And a junction depth of the source and drain is equal to a depth of the floating gate. The method of claim 1, wherein the flash memory cell And a junction depth of the source and drain is shallower than a depth of the floating gate. The method of claim 1, wherein the flash memory cell And a junction depth of the source and drain is deeper than a depth of the floating gate. The method of claim 1, wherein the dielectric film A flash memory cell comprising an O / N / O (oxide / nitride / oxide) film. Forming an isolation layer exposing a predetermined region of the semiconductor substrate; Forming a trench on a surface of the semiconductor substrate between the device isolation layers; Forming a tunnel oxide layer on the side of the trench; Forming a floating gate with a first conductive layer filling the trench while contacting the tunnel oxide layer; Forming a dielectric film on the floating gate; Forming a control gate as a second conductive layer on the dielectric layer; And And forming source and drain regions in contact with the device isolation foil on both sides of the floating gate of the semiconductor substrate. The method of claim 10, wherein the first or second conductive film A method of manufacturing a flash memory cell, characterized in that it is formed of polysilicon or doped polysilicon. The method of claim 10, wherein the dielectric film A flash memory cell manufacturing method, characterized in that it is formed of an O / N / O (oxide / nitride / oxide) film. The method of claim 10, wherein the tunnel oxide film And a uniform thickness of the tunnel oxide layer surrounding the floating gate. The method of claim 10, wherein the tunnel oxide film And a thickness of the tunnel oxide layer surrounding the floating gate is thicker at a bottom corner portion of the floating gate. The method of claim 10, wherein the source and drain regions are And the junction depths of the source and the drain are formed on both sides of the floating gate. The method of claim 15, wherein the source and drain regions are And the junction depth of the source is shallower than the depth of the floating gate, and the junction depth of the drain is equal to the depth of the floating gate. The method of claim 10, wherein the source and drain regions are And a junction depth of the source and drain is equal to a depth of the floating gate. The method of claim 10, wherein the source and drain regions are And a junction depth of the source and drain is formed to be shallower than a depth of the floating gate. The method of claim 10, wherein the flash memory cell And a junction depth of the source and drain is deeper than a depth of the floating gate. The method of claim 10, wherein the flash memory cell manufacturing method And a floating gate pattern for forming the floating gate and a control gate pattern for forming the control gate to form the floating gate and the control gate. The method of claim 10, wherein the flash memory cell manufacturing method And forming the control gate using a floating gate pattern for forming the floating gate. The flash memory cell of claim 1 or 5, wherein the flash memory cell is programmed by applying a voltage to the source region to inject charge into the floating gate. 23. The flash memory cell of claim 22, wherein binary information stored in the flash memory cell is read by applying a voltage to the source region. 8. The flash of claim 1, wherein the binary memory is programmed into the flash memory cell by applying a voltage to the source region to tunnel the charge from the source region to the floating gate. 9. Memory cells. 8. The flash memory cell of claim 1 or 7, wherein binary information stored in the flash memory cell is erased by applying a voltage to the drain region to tunnel the charge stored in the floating gate. 8. The method of claim 1 or 7, wherein binary information is stored in the floating gate by tunneling charge generated in one of the source or drain regions and using the other one of the source or the drain. And erase the binary information by tunneling charges. The flash memory cell of claim 1, wherein the floating gate is formed using a chemical mechanical planarization process. The flash memory cell of claim 1, wherein the control gate is formed using a chemical mechanical planarization process. 12. The method of claim 10, wherein forming the floating gate uses a chemical mechanical planarization process. The method of claim 10, wherein the forming of the control gate uses a chemical mechanical planarization process.

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