JP2002118183A - Non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the efficiency of writing into a floating gate and improve the resistance to a short channel effect. SOLUTION: A non-volatile semiconductor memory comprises an insulated- gate FET having a control gate 114 and floating gate 110 which is formed in a surface region of a semiconductor substrate 101. In the transistor, source silicide 105 formed of CoSi2 is formed in the source region, and drain silicide 106 formed of CoSi2 is formed in the drain region, thereby forming a Schottky junction in the source and drain region. The floating gate 110 is formed, being buried in a channel region, so as to partially overlap the Schottky junction in the laterial direction of the substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile semiconductor memory using an insulated gate field effect transistor having a control gate and a floating gate, and more particularly to a nonvolatile semiconductor memory having a Schottky junction formed in at least one of a source / drain region. The present invention relates to a nonvolatile semiconductor memory.

[0002]

2. Description of the Related Art In recent years, with the rapid development of portable information devices, nonvolatile semiconductor memories capable of retaining information without supplying power have played an important role. A typical structure of a conventional nonvolatile semiconductor memory is shown in FIG.
01 is a p-type Si substrate, 107 is a first gate insulating film (S
iO ₂ ), 110 is a floating gate, 111 is a second gate insulating film (SiO ₂ ), 114 is a control gate, 901 is n
^{A +} type diffusion layer (source) 902 is an n ⁺ type diffusion layer (drain).

[0003] This structure uses a floating gate 1 by thermal electrons.
In this method, electrons are written in the reference numeral 10. For example, the p-type Si substrate 101 and the source 901 are grounded, and
3 V and 15 V are applied to the control gate 114. Then
Electrons traveling from the source 901 are accelerated toward the drain 902, and enter a high energy state at the end of the drain 902. Of this group of electrons in the high energy state, Si /
Electrons that can cross the energy barrier at the SiO ₂ interface are transferred to the floating gate 11 by the potential of the control gate 114.
Inject at 0.

In a state where electrons are injected into the floating gate 110, the threshold value of the gate voltage for flowing the drain current increases. By associating the change of the threshold value with “0” and “1”, it is possible to hold 1-bit information.

[0005] However, this type of semiconductor memory has a problem that the efficiency of injecting electrons into the floating gate 110 is not good. That is, the velocity vector of most of the electron group traveling from the source 901 to the high energy state at the end of the drain 902 is directed to the drain direction. Therefore, less electrons are injected into the floating gate 110. Further, when the gate electrode length is reduced to realize a large-capacity memory, a depletion layer around the source 901 and the drain 902 expands below the gate electrode, and a short channel effect occurs in which the controllability of the gate is reduced. For this reason, there has been a problem in miniaturizing the element.

[0006]

As described above, conventionally, in a nonvolatile memory using an insulated gate type field effect transistor having a control gate and a floating gate, the efficiency of injecting electrons into the floating gate is not good. When the length is reduced, a short channel effect occurs.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to improve the efficiency of writing to a floating gate and to improve the short channel effect resistance. To provide memory.

[0008]

(Structure) In order to solve the above problem, the present invention employs the following structure.

That is, the present invention relates to a nonvolatile semiconductor memory in which an insulated gate field effect transistor having a control gate and a floating gate is formed in a surface region of a semiconductor substrate, wherein at least a source region and a drain region of the transistor are formed. A Schottky junction is formed on one side, and the floating gate is buried in a channel region of the transistor so as to partially overlap the Schottky junction in a surface direction of the substrate.

Here, preferred embodiments of the present invention include the following. (1) A buried insulating film is formed in the substrate so as to be located at the bottom of the transistor formation region.

(2) The substrate is of the first conductivity type, the Schottky junction is formed in both the source region and the drain region of the transistor, and at least one of the Schottky junction ends adjacent to the gate side of the transistor contacts the substrate. As described above, the second conductivity type region is formed in part of the source region and the drain region.

(3) The second conductivity type region is formed asymmetrically between the source region and the drain region of the transistor, and
One of the conductivity type regions is formed so as to include a Schottky junction end adjacent to the gate side.

(4) The bottom of the floating gate is deeper than the substrate surface, and the upper part of the floating gate is higher than the substrate surface.

(5) The semiconductor substrate is a Si substrate. (6) A silicide layer must be formed on the surface of the substrate to form a Schottky junction.

(Function) According to the present invention, since the floating gate is buried in the channel region so as to partially overlap the Schottky junction in the surface direction of the substrate, the floating gate runs from the source region to the drain region. The floating gate exists not in the horizontal direction but in front of the generated electrons, so that the electrons can easily enter the floating gate. That is,
Since most of the carriers injected from the source region contribute to writing to the floating gate, a nonvolatile semiconductor memory with high writing efficiency can be realized. Further, since a Schottky junction is formed in the source / drain region, an n ⁺ diffusion layer is not required, so that short channel effect resistance can be improved.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the illustrated embodiments.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a basic configuration of a nonvolatile semiconductor memory according to the embodiment. In the figure, 101 is a p-type Si substrate, 10
3 is a source side wall insulating film (SiO ₂ ), 104 is a drain side wall insulating film (SiO ₂ ), 107 is a first gate insulating film (SiO ₂ ), 110 is a floating gate, 111 is a second gate An insulating film (SiO ₂ ), 114 indicates a control gate, and 105 and 106 indicate silicide for forming a Schottky junction.

Although the floating gate 110 and the control gate 114 are provided on the Si substrate 101 as in the conventional example, in the present embodiment, the silicide 105 made of CoSi ₂ is used in the source region and the silicide made of CoSi _{2 is used in} the drain region. By forming 106, a Schottky junction is formed. Further, the floating gate 110 is embedded in the channel region so as to partially overlap the Schottky junction in the surface direction of the substrate.

FIG. 2 is a conceptual diagram of an electron energy band for explaining a state of writing electrons in the present embodiment. This energy band diagram shows, for example, p-type Si
This is realized by grounding the substrate 101 and the source silicide 105 and applying a voltage of 13 V to the drain silicide 106 and a voltage of 15 V to the control gate 114. Electrons are injected from the energy barrier of the source silicide 105 in the source region by quantum mechanical tunneling, accelerated in the Si region, and injected into the floating gate 110. At this time, since the floating gate 110 is buried in the channel region, the source silicide 105 is formed.
Is directly injected into the floating gate 110, thereby increasing the electron injection efficiency.

As described above, in this embodiment, since the Schottky junction is used, a strong electric field is applied to the source side,
Electrons travel from the source region to the drain region, but the floating gate 110
Is partially buried, so that the floating gate 11
0 will be located at the surface of the substrate. In this case, the floating gate exists not in the lateral direction but in front of the electrons traveling from the source region to the drain region, and the electrons can enter the floating gate very easily. Therefore, many carriers injected from the source region contribute to writing to the floating gate,
Writing efficiency can be improved. Further, since the Schottky junction is formed without forming the n ⁺ diffusion layer in the source / drain region, the short channel effect resistance can be improved.

Next, the manufacturing method of the present embodiment will be described with reference to FIGS. First, as shown in FIG.
Si ₃ N is formed on the p-type Si substrate 101 by a thermal nitridation process.
_Four films 102 are formed. Next, as shown in FIG. 3B, p-type S is formed by RIE (Reactive Ion Etching).
The i-substrate 101 and the Si ₃ N ₄ film 102 are etched into a column shape. Next, as shown in FIG.
After depositing the _two films, the SiO ₂ film is removed leaving the source side wall SiO ₂ region 103 and the drain side wall SiO ₂ region 104. Next, as shown in FIG. 3D, annealing is performed after depositing Co to form a source silicide 105 made of CoSi ₂ and a drain silicide 106 made of CoSi ₂ , and then unreacted Co is removed.

[0022] Then, as shown in FIG. 4 (e), Si ₃
The N ₄ film 102 and the underlying Si region are etched to form a trench in the gate region. At this time, the trench is formed such that the trench bottom is lower than the source silicide 105 and the drain silicide 106. Then, FIG.
As shown in (f), the first gate Si is formed by thermal oxidation.
An O ₂ film 107 is formed. Next, as shown in FIG. 4G, a polycrystalline Si film 108 and a Si ₃ N ₄ film 109 are deposited. Next, as shown in FIG.
The deposited film is flattened by ical mechanical polishing.

Next, as shown in FIG.
Etching the polycrystalline Si film 108 and the Si ₃ N ₄ film 109 to form a floating gate region 110 in the trench. That is, the polycrystalline Si film 108 is completely removed outside the trench, and partly remains inside the trench. Next, as shown in FIG. 5J, a _second gate SiO ₂ film 111 is formed on the floating gate 110 by thermal oxidation. Next, as shown in FIG.
An i film 112 and a Si ₃ N ₄ film 113 are deposited. afterwards,
The structure of FIG. 1 is formed by etching the polycrystalline Si film 112 and the Si ₃ N ₄ film 113 to form the control gate region 114 in the trench.

When etching the polycrystalline Si film 112, if the gate electrode length is long, a mask is used to selectively form the control gate electrode 114 while leaving the polycrystalline Si film 112 in the gate region. When the gate electrode length is short, the polycrystalline Si film 112 is formed thick above the gate region, so that the control gate electrode 1 can be formed without using a mask.
The polycrystalline Si film 112 can be etched so as to leave 14.

(Second Embodiment) FIG. 6 shows a second embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a basic configuration of a nonvolatile semiconductor memory according to the embodiment. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The present embodiment differs from the first embodiment described above in that a buried SiO ₂ layer 201 is formed. This buried SiO ₂ layer 201 may be selectively formed only at the bottom of the transistor formation region, or may be formed entirely in the lateral direction of the substrate. To be formed over the entire substrate in the lateral direction means that an SOI substrate is used.

The buried SiO ₂ layer 2 in this embodiment
01 is a p-type Si substrate 101 and a drain silicide 10
6 has a role of suppressing a leak current. That is,
When a positive voltage is applied to the drain silicide 106, p
A hole current flows through a Schottky junction between the silicon substrate 101 and the drain silicide 106. This current may become a drain leak current and increase power consumption. By forming the buried SiO ₂ layer 201, this leakage current can be suppressed.

In order to suppress the above-mentioned leakage current, an insulating film such as SiO ₂ is most desirable. However, the present invention is not limited to the insulating film, and SiC having a large band gap can be embedded. is there.

(Third Embodiment) FIG. 7 shows a third embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a basic configuration of a nonvolatile semiconductor memory according to the embodiment. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

This embodiment is different from the first embodiment described above in that the source n ⁺ diffusion layer 301 is formed below the source silicide 105 and the drain silicide 1
06 is that a drain n ⁺ diffusion layer 302 is formed below.

The diffusion layers 301 and 302 in the present embodiment
Represents the drain silicide 106 as in the second embodiment.
Has the role of suppressing the leakage current between the
N ⁺The role of the diffusion layer 302 is important. That is, Dray
N⁺A depletion layer spreads around the diffusion layer 302, and the p-type Si
Shot between substrate 101 and drain silicide 106
Relieves the steep shape of the key barrier. This allows
Channel probability is reduced and drain leakage current is suppressed
be able to.

Since the diffusion layers 301 and 302 are formed outside the gate-side Schottky junction ends of the silicides 105 and 106, the short channel effect resistance does not deteriorate. In addition, these diffusion layers 301,
302 denotes a source side wall S after forming CoSi ₂ silicide.
After the sidewalls are formed further outside the iO ₂ region 103 and the drain sidewall SiO ₂ region 104, they may be formed by ion-implanting impurities such as As.

(Fourth Embodiment) FIG. 8 shows a fourth embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a basic configuration of a nonvolatile semiconductor memory according to the embodiment. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

This embodiment is different from the third embodiment described above in that the source n ⁺ diffusion layer 401 and the drain n
^The point is that the diffusion layer 402 is formed asymmetrically. That is, the source n ⁺ diffusion layer 401 is formed in a region excluding the Schottky junction end adjacent to the gate side similarly to the source n ⁺ diffusion layer 301 of the third embodiment, but the drain n ^+
+ Diffusion layer 402 is formed such that the Schottky junction end adjacent to the gate side is included.

The diffusion layers 401 and 402 in the present embodiment
Similarly to the second and third embodiments, it also has a role of suppressing a leak current between the drain silicide 106 and the drain n ⁺ diffusion layer 402 is particularly important. That is, the drain n ⁺ diffusion layer 402 is the drain silicide 1
06, so that the drain leakage current can be suppressed more reliably.

Incidentally, these diffusion layers 401 and 402 are
After the formation of the CoSi ₂ silicide, the sidewalls are formed further outside the source sidewall SiO ₂ region 103 and the drain sidewall SiO ₂ region 104, and then impurities such as As are obliquely ion-implanted from the drain side.

The present invention is not limited to the above embodiments. In the embodiment, the Schottky junction is formed in both the source and drain regions. However, the present invention can be similarly applied to the case where the Schottky junction is formed in one of the source and drain regions. Further, the silicide material, gate material, and other materials of each part for forming the Schottky junction are not limited to the embodiment and can be appropriately changed according to the specifications. Furthermore, the manufacturing steps shown in FIGS. 3 to 5 do not limit the present invention in any way, and can be appropriately changed according to specifications.

In addition, various modifications can be made without departing from the spirit of the present invention.

[0039]

As described above in detail, according to the present invention, a Schottky junction is formed in at least one of the source region and the drain region of a transistor, and the floating gate is connected to the Schottky junction with respect to the surface direction of the substrate. By being embedded in the channel region so as to partially overlap with each other, the efficiency of writing to the floating gate can be increased and the short channel effect resistance can be improved. This makes it possible to realize a large-capacity nonvolatile semiconductor memory with low power consumption.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a basic configuration of a nonvolatile semiconductor memory according to a first embodiment.

FIG. 2 is a conceptual diagram of an electron energy band for explaining a state of writing of electrons in the first embodiment.

FIG. 3 is a sectional view showing a manufacturing process in the first embodiment.

FIG. 4 is a sectional view showing a manufacturing process in the first embodiment.

FIG. 5 is a sectional view showing the manufacturing process in the first embodiment.

FIG. 6 is a sectional view showing a basic configuration of a nonvolatile semiconductor memory according to a second embodiment.

FIG. 7 is a sectional view showing a basic configuration of a nonvolatile semiconductor memory according to a third embodiment;

FIG. 8 is a sectional view showing a basic configuration of a nonvolatile semiconductor memory according to a fourth embodiment.

FIG. 9 is a cross-sectional view showing a basic configuration of a conventional nonvolatile semiconductor memory.

[Explanation of symbols]

101 ... p-type Si substrate 102,109,113 ... Si ₃ N ₄ film 103 ... source sidewall SiO ₂ region 104 ... drain sidewall SiO ₂ region 105 ... source silicide (CoSi ₂₎ 106 ... drain silicide (CoSi ₂₎ 107 ... first 1 gate insulating film (SiO ₂ ) 108, 112 polycrystalline Si film 110 floating gate 111 second gate insulating film (SiO ₂ ) 114 control gate 201 embedded SiO ₂ layer 301, 401, 901 source n ⁺ diffusion layers 302, 402, 902... drain n ⁺ diffusion layers

 ──────────────────────────────────────────────────続 き Continued on front page F term (reference) 5F001 AA31 AB08 AC01 AD13 AD15 AD70 AE02 AF10 5F083 EP13 EP23 EP62 EP67 ER03 ER06 GA01 HA02 JA35 JA39 5F101 BA13 BB05 BC01 BD03 BD05 BD30 BE05 BF10 5F110 BB08 CC01 DD05 DD12 DD13EE32 EE32 FF02 FF23 GG02 GG12 GG22 HK05 HK40

Claims (5)

[Claims] 1. A nonvolatile semiconductor memory in which an insulated gate field effect transistor having a control gate and a floating gate is formed in a surface region of a semiconductor substrate, wherein at least one of a source region and a drain region of the transistor has a shot. A non-volatile semiconductor memory, wherein a key junction is formed, and the floating gate is formed so as to be embedded in a channel region of the transistor so as to partially overlap the Schottky junction with respect to a surface direction of the substrate. . 2. The nonvolatile semiconductor memory according to claim 1, wherein a buried insulating film is formed in said substrate so as to be located at a bottom of said transistor formation region. 3. The substrate is of a first conductivity type, the Schottky junction is formed in both a source region and a drain region of the transistor, and at least one of a Schottky junction end adjacent to a gate side of the transistor is formed. 2. The nonvolatile semiconductor memory according to claim 1, wherein a second conductivity type region is formed in a part of the source region and the drain region so as to be in contact with the substrate. 4. The second conductivity type region is formed asymmetrically between a source region and a drain region of the transistor, and one of the second conductivity type regions includes a Schottky junction end adjacent to a gate side. 4. The nonvolatile semiconductor memory according to claim 3, wherein the nonvolatile semiconductor memory is formed as described above. 5. A nonvolatile semiconductor memory comprising an insulated gate field effect transistor having a control gate and a floating gate in a surface region of a silicon substrate, wherein a Schottky junction is formed in a source region and a drain region of the transistor. A silicide layer is formed, and the floating gate is embedded in a channel region of the transistor so as to partially overlap the Schottky junction with respect to a surface direction of the substrate. Non-volatile semiconductor memory.