CN110047833A - Memory and its working method and forming method - Google Patents

Abstract

A kind of memory and its working method and forming method, wherein the memory includes: the first well region in the substrate, has the first Doped ions in first well region；Positioned at the second well region of the first well region top surface, there are the second Doped ions in second well region, second Doped ions are opposite with the conduction type of first Doped ions；Gate structure positioned at second well region surface, the gate structure include opposite the first side and second side；The first doped region in the second well region of first side of gate structure, has third Doped ions in first doped region, and the conduction type of the third Doped ions is opposite with the conduction type of second Doped ions；The source line being electrically connected with second well region.The energy consumption of the memory is lower.

Description

Memory and its working method and forming method

Technical field

The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of memory and its working method and formation sides Method.

Background technique

With the development of information technology, information memory capacity is sharply increased.The increase of information memory capacity promotes memory Rapid development, while also to the performance of memory, more stringent requirements are proposed.

The data of its storage inside can be saved since static memory (SRAM) does not need refresh circuit, power consumption is smaller, So that SRAM using more and more extensive.The storage unit of traditional SRAM is generally by six MOS transistors or four MOS crystal Pipe forms, and the quantity of MOS transistor is more in storage unit, causes the volume of MOS transistor larger.In order to reduce memory Volume improves integrated level, proposes a kind of single-transistor static memory (1T SRAM).

However, the energy consumption of existing single-transistor static memory is larger.

Summary of the invention

Problems solved by the invention is to provide a kind of memory and its working method and forming method, can reduce memory Energy consumption.

To solve the above problems, the present invention provides a kind of memory, comprising: substrate；The first trap in the substrate Area has the first Doped ions in first well region；Positioned at the second well region of the first well region top surface, described second There are the second Doped ions, second Doped ions are opposite with the conduction type of first Doped ions in well region；It is located at The gate structure on second well region surface, the gate structure include opposite the first side and second side；Positioned at the grid The first doped region in second well region of the first side of structure has third Doped ions, the third in first doped region The conduction type of Doped ions is opposite with the conduction type of second Doped ions；The word being electrically connected with the gate structure Line；The bit line being electrically connected with first doped region；The source line being electrically connected with second well region.

Optionally, first Doped ions are N-type ion, and second Doped ions are P-type ion, and the third is mixed Heteroion is N-type ion；Alternatively, first Doped ions are P-type ion, second Doped ions are N-type ion, described Third Doped ions are P-type ion.

Optionally, the memory includes multiple storage units, and the storage unit includes: first well region, second Well region, gate structure and first doped region.

Optionally, multiple storage units are arranged as storage array；With the grid of the storage unit of a line in the storage array Pole structure is electrically connected to each other by same wordline；The first doped region of the storage unit of same row passes through same in the storage array One bit line is electrically connected to each other；It is mutually electric by same source line with the second doped region of the storage unit of a line in the storage array Connection.

Optionally, further includes: the second doped region in second well region of described gate structure second side, described second There are the 4th Doped ions, the 4th Doped ions are identical as the conduction type of the second Doped ions and described in doped region The concentration of the 4th Doped ions is greater than the concentration of the second Doped ions in second well region in second doped region；The source line with The second doped region electrical connection.

Optionally, further includes: cover the first medium layer of the gate structure, the second doped region and the first doped region；Position The first plug in the first medium layer, first plug runs through the first medium layer, and adulterates with described first Area's contact, the bit line are located at the first medium layer and first plug surface；Positioned at the bit line and first medium layer The second dielectric layer on surface；The second plug of the second dielectric layer, second plug are through to from the first medium layer It is contacted with second doped region；The source line is located at second plug and the second medium layer surface.

Correspondingly, the present invention also provides a kind of working methods of memory, comprising: provide memory；To first trap Area applies the first current potential, makes the PN junction reverse bias between first well region and the second well region；The memory is write Enter operation, the method for said write operation includes: to apply the second current potential to the bit line, make the first doped region and the second well region it Between voltage be first voltage；Third current potential is applied to the wordline, makes voltage between gate structure and the second well region the Two voltages, the second voltage are positive and negative identical as first voltage；After said write operation, the memory is read out Operation, the method for the read operation include: to apply the first reading potential to the bit line；Apply second to the source line to read Current potential, first reading potential and the second reading potential make the PN junction forward bias between the first doped region and the second well region； After applying the first reading potential to the bit line, after applying the second reading potential to the source line, by the bit line Reading electric current, obtain read data.

Optionally, first Doped ions are N-type ion, and first current potential is greater than the current potential of second well region； Alternatively, first Doped ions are P-type ion, first current potential is less than the current potential of second well region.

Optionally, the method for said write operation further include: keep the source line hanging, or the 4th is applied to the source line Current potential, the 4th current potential are zero potential；When first Doped ions be N-type ion when, first current potential be 1.8V~ 2.2V；Second current potential is 0.7V~0.9V, and the third current potential is 0.7V~0.9V；Alternatively, second current potential be- 0.55V~-0.45V, the third current potential are -0.55V~-0.45V.

Optionally, the memory includes multiple storage units, and the storage unit includes: first well region, second Well region, gate structure and first doped region；Multiple storage units are arranged as storage array；Same a line in the storage array The gate structure of storage unit be electrically connected to each other by same wordline；The of the storage unit of same row in the storage array One doped region is electrically connected to each other by same bit line；The second doped region in the storage array with the storage unit of a line passes through Same source line is electrically connected to each other；The wordline includes the first wordline and the second wordline, and the first wordline connection carries out write-in behaviour The storage unit of work；The bit line includes the first bit line and the second bit line, and the first bit line connection carries out depositing for write operation Storage unit；It include: that the second current potential is applied to first bit line to the method that the bit line applies the second current potential；To the wordline The method for applying third current potential includes: to apply third current potential to first wordline；The method of said write operation further include: right Second bit line applies zero potential, or keeps second bit line hanging；Zero potential is applied to second wordline, or makes institute It is hanging to state the second wordline.

Optionally, first Doped ions are N-type ion, and first reading potential is less than described second and reads electricity Position；Alternatively, first Doped ions are P-type ion, first reading potential is greater than second reading potential.

Optionally, first Doped ions are N-type ion；When the first voltage is greater than zero, the second voltage is big When zero, be written data " 1 "；Alternatively, first Doped ions are P-type ion；When the first voltage is less than zero, described When two voltages are less than zero, be written data " 1 "；Obtaining the method for reading data includes: to preset when the reading electric current is greater than When electric current, the reading data are " 1 "；When the reading electric current is less than predetermined current, the reading data are " 0 ".

Optionally, first Doped ions are N-type ion；The method of the read operation further include: in the wordline Upper application zero potential, or keep the wordline hanging；First reading potential is -0.8V~-0.7V；Described second reads electricity Position is zero potential.

Optionally, the memory includes multiple storage units, and the storage unit includes: first well region, second Well region, gate structure and first doped region；Multiple storage units are arranged as storage array；Same a line in the storage array The gate structure of storage unit be electrically connected to each other by same wordline, the of the storage unit of same row in the storage array One doped region is electrically connected to each other by same bit line, and the second doped region with the storage unit of a line is mutually electric by same source line Connection；The source line includes the first source line and the second source line, and first source line connects the storage unit being read；Institute Rheme line includes third bit line and the 4th bit line, and the third bit line connects the storage unit being read；To institute's rheme The method that line applies the first reading potential includes: to apply the first reading potential to the third bit line；The is applied to the source line The method of two reading potentials includes: to apply the second reading potential to first source line, and second reading potential is read with first Current potential is taken to make the PN junction forward bias between second well region and the first doped region；The method of the read operation further include: Keep the 4th bit line hanging；Keep second source line hanging.

Technical solution of the present invention also provides a kind of forming method of memory, comprising: provides substrate；Shape in the substrate At the first well region, there are the first Doped ions in first well region；The second well region is formed in the first well region top surface, There is the second Doped ions, the conduction type phase of second Doped ions and first Doped ions in second well region Instead；Gate structure is formed on second well region surface, and forms the first doped region in second well region, the grid knot Structure includes opposite the first side and second side, and first doped region is located in the second well region of first side of gate structure, There is third Doped ions, the conduction type of the third Doped ions and second Doped ions in first doped region On the contrary；Form the wordline being electrically connected with the gate structure；Form the bit line being electrically connected with first doped region；Formation and institute State the source line of the second well region electrical connection.

Optionally, it is formed after the gate structure, forms first doped region；Form the side of first doped region Method further include: form the first mask layer for covering second well region of described gate structure second side；With first mask layer and Gate structure is that exposure mask carries out the first source and drain ion implanting to the second well region of second side, and third is injected in second well region and is mixed Heteroion, the third Doped ions are opposite with the conduction type of second Doped ions.

Optionally, further includes: the second doped region is formed in second well region, second doped region is located at the grid Second side of pole structure, has the 4th Doped ions in second doped region, the 4th Doped ions and second adulterate from The conduction type of son is identical, and the concentration of the 4th Doped ions is mixed greater than in second well region second in second doped region The concentration of heteroion.

Optionally, it is formed after the gate structure, forms second doped region；Form the side of second doped region Method includes: the second mask layer to form covering the second well region of first side of gate structure；With second mask layer and grid Structure be exposure mask to second well region carry out the second source and drain ion implanting, in second well region inject the 4th adulterate from Son, the 4th Doped ions are identical as the conduction type of second Doped ions.

Optionally, it is formed before the bit line, further includes: formed and cover the gate structure, the second doped region and first The first medium layer of doped region；The first plug is formed in the first medium layer, first plug is situated between through described first Matter layer, and contacted with first doped region；The bit line is located at the first medium layer and first plug surface；It is formed After the bit line, further includes: form second dielectric layer in the bit line and first medium layer surface；It is formed and is situated between from described first Matter layer is through to the second plug of the second dielectric layer, and second plug is contacted with second doped region；The bit line Positioned at second plug and the second medium layer surface.

Compared with prior art, technical solution of the present invention has the advantage that

In the memory that technical solution of the present invention provides, current potential can be applied to the gate structure by the wordline； Current potential can be applied to first doped region by the bit line, to pass through the current potential on gate structure and the first doped region Charge can be injected into second well region, or discharge the charge in second well region, and then described deposit can be made Reservoir storing data " 1 " and " 0 ".The memory includes the source line being electrically connected with second well region, then can be by institute It states source line and applies current potential, to apply current potential to the second well region.Due to leading for second Doped ions and third Doped ions Electric type can pass through on the contrary, the second well region and the first doped region composition diode and apply difference on the bit line and source line Current potential, the diode forward for constituting the second well region with the first doped region is connected, to form electric current in the bit line.Root The data stored in the memory can be read according to the electric current in the bit line.Due to the data in reading the memory The diode forward that process constitutes the second well region with the first doped region is connected, the pressure drop very little of the forward conduction of diode, from And keep the energy consumption of the memory lower.

Further, the memory includes: the second doped region in second well region of gate structure second side；With Second plug of second doped region contact, the source line pass through second plug and second doped region and described the The electrical connection of two well regions.Since the concentration of the 4th Doped ions in second doped region is greater than the second doping in second well region The concentration of ion, then Ohmic contact easy to form between second plug and second doped region, so as to reduce The contact resistance between the second plug and the second doped region is stated, the energy consumption of formed memory is reduced.

In the working method for the memory that technical solution of the present invention provides, the positive negative of the second voltage and first voltage Together, gate structure bottom the second well region transoid forms inversion layer, and the PN between first doped region and the second well region Tie reverse bias；Or gate structure bottom inversion layer disappears, and the PN between first doped region and the second well region Tie forward bias.When gate structure bottom the second well region transoid forms inversion layer, and first doped region and the second trap When PN junction reverse bias between area, charge is injected in the second well region of the inversion layer bottom；When the gate structure bottom Inversion layer disappears, and when PN junction forward bias between first doped region and the second well region, discharges in second well region Charge.Therefore, the memory can indicate different storage states by whether injecting charge in second well region, And then the memory can storing data " 1 " and " 0 ", realization store function.

During read operation, first reading potential and the second reading potential make the first doped region and the second well region Between PN junction forward bias, then the diode current flow that first doped region and the second well region are constituted, to make the bit line Electric current is read in middle generation.During write operation, charge is injected in the second well region of Xiang Suoshu, below the gate structure The second well region in when forming inversion layer, during read operation, the inversion layer, the first doped region and the second well region are constituted Diode, the inversion layer can increase the contact area of p type island region and N-type region in the diode, to make the reading electricity It flows larger；Conversely, when making the second well region release charge, the reading electric current is smaller during write operation.Cause This can read the data stored in the memory by the size for reading electric current.In addition, as described in the reading It in memory during data, is connected by the diode forward for constituting the second well region with the first doped region, to obtain Read data.Due to the pressure drop very little of the forward conduction of diode, to keep the energy consumption of the memory smaller.

Detailed description of the invention

Fig. 1 is a kind of structural schematic diagram of single-transistor static memory；

Fig. 2 and Fig. 3 is the structural schematic diagram of one embodiment of memory of the invention；

Fig. 4 to Fig. 7 is the structural schematic diagram of each step in one embodiment of working method of memory of the invention；

Fig. 8 is that the relationship for reading electric current and reading between voltage during memory of the invention is read is bent Line chart；

Fig. 9 to Figure 13 is the structural schematic diagram of each step in one embodiment of forming method of memory of the invention.

Specific embodiment

There are problems for storage, such as: the energy consumption of memory is higher, and performance is poor.

Now in conjunction with a kind of single-transistor static memory, the higher original of energy consumption of the single-transistor static memory is analyzed Cause:

Fig. 1 is a kind of structural schematic diagram of single-transistor static memory.

Referring to FIG. 1, the memory includes multiple storage units, the storage unit includes: substrate 10, is located at described N trap 13 and p trap 14 in substrate 10, the p trap 14 is with n trap 13 along the direction arrangement perpendicular to 10 surface of substrate；Positioned at the p The gate structure 15 on 14 surface of trap；Connect the wordline WL of the gate structure 15；Source region positioned at 15 two sides of gate structure 11 and drain region 12, the source region 11 and drain region 12 are N-shaped ion doped region；Connect the source line SL of second doped region；Connection The bit line BL in the drain region 12；Connect the trap line DNWL of the n trap.

Wherein, the read method of the memory includes: to apply positive potential on the wordline WL；On the bit line BL Apply positive potential or negative potential；Apply zero potential on the source line；The electric current in the bit line BL is measured, obtains and reads electricity Stream；Data stored in the storage unit are obtained according to the reading electric current.Due to applying positive potential on the wordline WL, institute The channel for stating gate structure bottom is opened, to make the source region 11 and drain region 12 be connected, when on the source line SL and bit line BL Voltage it is not identical when, generate on the bit line BL and read electric current.According to the sizes values for reading electric current, can obtain described The data stored in storage unit.

However, need to open 15 lower channels of gate structure since the memory is in reading process, it is described Voltage value on gate structure 15 is greater than the threshold value electricity for the transistor that gate structure 15, source region 11 and the first doped region 11 are formed Pressure, the energy consumption so as to cause the memory are larger.

To solve the technical problem, the present invention provides a kind of memories, comprising: positioned at second well region surface Gate structure, the gate structure include opposite the first side and second side；The second trap positioned at first side of gate structure The first doped region in area has third Doped ions, the conduction type of the third Doped ions in first doped region It is opposite with the conduction type of second Doped ions；The source line being electrically connected with second well region.The energy consumption of the memory It is lower.

To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention Specific embodiment be described in detail.

Fig. 2 and Fig. 3 is the structural schematic diagram of one embodiment of memory of the invention.

Fig. 2 and Fig. 3 are please referred to, Fig. 2 is that region 10 is along the sectional view of 21-22 in Fig. 3, and the present embodiment provides a kind of storages Device, comprising: substrate 200；The first well region 211 in the substrate 200 has the first doping in first well region 211 Ion；Positioned at the second well region 212 of 211 top surface of the first well region, in second well region 212 have second adulterate from Son, second Doped ions are opposite with the conduction type of first Doped ions；Positioned at 212 surface of the second well region Gate structure 201, the gate structure 201 include opposite the first side and second side；Positioned at 201 first side of gate structure The first doped region 202 in second well region 212 has third Doped ions, the third doping in first doped region 202 The conduction type of ion is opposite with the conduction type of second Doped ions；The wordline being electrically connected with the gate structure 201 WL；The bit line BL being electrically connected with first doped region 202；The source line SL being electrically connected with second well region 212.

Current potential can be applied to the gate structure 201 by the wordline WL；It can be to described by the bit line BL First doped region 202 applies current potential, thus can be to described the by the current potential on gate structure 201 and the first doped region 202 Charge is injected in two well regions 212, or discharges the charge in second well region 212, and then the memory can be made to deposit It stores up data " 1 " and " 0 ".The memory includes the source line SL being electrically connected with second well region 212, then can be by described Source line SL applies current potential, to apply current potential to the second well region 212.Due to second Doped ions and third Doped ions Conduction type, can be by the bit line BL and source line on the contrary, the second well region 212 and the first doped region 202 constitute diode Apply different current potentials on SL, the diode forward for constituting the second well region 212 with the first doped region 202 is connected, thus in institute Electric current is formed in rheme line BL.The data stored in the memory can be read according to the electric current in the bit line BL.Due to The diode forward that the process of data constitutes the second well region 212 with the first doped region 202 in reading the memory is connected, The pressure drop very little of the forward conduction of diode, to keep the energy consumption of the memory lower.

The substrate 200 includes: multiple memory cell areas and the isolated area between consecutive storage unit area.

The memory cell areas is used to form storage unit；The isolated area is for realizing between consecutive storage unit area It is electrically isolated.

The memory includes the multiple storage units for being located at the memory cell areas, and the storage unit includes: First well region 211, the second well region 212, gate structure 201 and first doped region 202.

In the present embodiment, the memory further include: in second well region 212 of described 202 second side of gate structure The second doped region 203, there are the 4th Doped ions, the 4th Doped ions are mixed with second in second doped region 203 The conduction type of heteroion is identical, and the concentration of the 4th Doped ions is greater than second well region in second doped region 203 The concentration of second Doped ions in 212；The source line SL is electrically connected with second doped region 203.

The memory further include: cover the of the gate structure 201, the second doped region 203 and the first doped region 202 One dielectric layer (not shown)；The first plug (not shown) in the first medium layer, first plug It is contacted through the first medium layer, and with first doped region 202, the bit line BL is located at the first medium layer and institute State the first plug surface；Positioned at the second dielectric layer of the bit line BL and first medium layer surface；It is passed through from the first medium layer It wears to the second plug of the second dielectric layer, second plug is contacted with second doped region 203；SL, the source line In second plug and the second medium layer surface；Grid in the first medium layer and second dielectric layer is inserted Plug, the gate plug are contacted with the gate structure, and the wordline WL is located at the gate plug and second medium layer surface.

The wordline WL connection gate plug；Bit line BL connection first plug；The source line SL connection Second plug.

The wordline WL is used to apply current potential to gate structure 201 by the gate plug；The bit line BL is for leading to It crosses first plug and current potential is applied to first doped region 202；The source line SL is used for through the second plug to described the Two doped regions 203 apply current potential.

The memory includes the second doped region 203 in 201 second well region of second side 212 of gate structure； The second plug contacted with second doped region 203, the source line SL pass through second plug and second doped region 203 are electrically connected with second well region 212.Described in the concentration of the 4th Doped ions in second doped region 203 is greater than The concentration of second Doped ions in second well region 212, then it is easy to form between second plug and second doped region 203 Ohmic contact, so as to reduce the contact resistance between second plug and the second doped region 203, reduction forms storage The energy consumption of device.

The material of second plug, the first plug and gate plug is tungsten, aluminium or copper.

In the present embodiment, along 201 extending direction of gate structure, the gate structure 201 across multiple memory cell areas, To make the gate structure 201 of multiple storage units on 201 extending direction of gate structure be connected with each other.

Multiple storage units are arranged as storage array；With the gate structure of the storage unit of a line in the storage array 201 are electrically connected to each other by same wordline WL；The first doped region 202 of the storage unit of same row passes through in the storage array Same bit line BL is electrically connected to each other；Pass through same source with the second doped region 203 of the storage unit of a line in the storage array Line SL is electrically connected to each other.

The trap line DNWL is used to provide power supply for storage unit, to prevent the data stored in the memory from disappearing It loses；The combination of the bit line BL and wordline WL is for selecting the storage unit of progress write operation；The bit line BL and source line SL Combination for selecting the storage unit that is read.

By the current potential on control gate structure 201 and the second well region 212,201 bottom of gate structure can be made The charge in charge, or release second well region 212 is injected in second well region 212.Therefore, the memory can pass through Whether charge is injected in second well region 212 to indicate different storage states, and then storing data " 1 " and " 0 ".

The PN junction that the current potential of first well region 211 is used to that the second well region 212 to be made to be formed with the first well region 211 is reversely inclined It sets, is discharged to reduce charge in second well region 212 by the first well region 211, and then prevent the data of storage from disappearing.

In the present embodiment, first Doped ions are N-type ion, and second Doped ions are P-type ion, described the Three Doped ions are N-type ion, and the 4th Doped ions are P-type ion.In other embodiments, first Doped ions For P-type ion, second Doped ions are N-type ion, and the third Doped ions are P-type ion, the described 4th adulterate from Son is N-type ion.

In the present embodiment, when injecting hole in second well region 212, the data of the storage of the storage unit are "1"；When not having injected holes in second well region 212, the data of the storage of the storage unit are " 0 ".At it In his embodiment, first Doped ions are N-type ion, when injecting hole in second well region, the storage unit Storage data be " 0 "；When not having injected holes in second well region, the data of the storage of the storage unit For " 1 ".Alternatively, first Doped ions are P-type ion, and when injecting electronics in second well region, the storage The data of the storage of unit are " 0 ", when not having injected electrons in second well region, the storage of the storage unit Data are " 1 "；Alternatively, first Doped ions are P-type ion, it is described when injecting electronics in second well region The data of the storage of storage unit are " 1 ", and when not having injected electrons in second well region, the storage unit is deposited The data of storage are " 0 ".

In the present embodiment, the principle to storage unit write-in data " 1 " includes: the storage list for making connection carry out write operation Voltage between the wordline WL and source line SL of member is greater than zero；Connection is set to carry out the bit line BL and source line of the storage unit of write operation Voltage on SL is greater than zero.The current potential for connecting the wordline WL of the storage unit without write operation is equal to the current potential of source line SL, The current potential for connecting the bit line BL of the storage unit without write operation is equal to the current potential of source line SL.In the present embodiment, each source line The current potential of SL is identical, then the wordline WL and bit line BL can uniquely determine the storage unit being written.When connection is write When entering the voltage between the wordline WL of the storage unit of operation and source line SL greater than zero, the second of 201 bottom of gate structure 212 transoid of well region forms inversion layer, while injecting hole into the second well region 212 of the inversion layer bottom.Due to connecting The voltage carried out between the bit line BL and source line SL of the storage unit of write operation is greater than zero, then the first of the storage unit is mixed PN junction reverse bias between miscellaneous area 202 and the second well region 212, and due to the PN of the first well region 211 and the formation of the second well region 212 Reverse bias is tied, injected holes is limited in second well region 212 in second well region 212, to make described deposit Data " 1 " is written in storage unit.

Process to storage unit write-in data " 0 " is the process in hole in release second well region 212, with erasing institute The process for stating data in storage unit " 1 " is identical.Specifically, to the principle of storage unit write-in data " 0 " include: make to connect into Voltage between the wordline WL and source line SL of the storage unit of row write operation is less than zero；Connection is set to carry out the storage of write operation Voltage between the bit line BL and source line SL of unit is less than zero.Connect wordline WL and the source of the storage unit without write operation Voltage between line SL is equal to zero；Connection is without the voltage etc. between the bit line BL and source line SL of the storage unit of write operation In zero.Apply identical current potential on the source line SL or keeps the source line SL hanging.It can be with by the wordline WL and bit line BL Uniquely determine the storage unit that " 0 " is written.When the connection carries out the wordline WL and source line of the storage unit of write operation When voltage between SL is less than zero, the inversion layer of 201 bottom of gate structure disappears, and the thickness of second well region 212 increases Add.Since the voltage between the bit line BL and source line SL of the storage unit of connection progress write operation is less than zero, then the storage PN junction forward bias between the first doped region 202 and the second well region 212 of unit, the electronics in first doped region 202 It injects in second well region 212.Again since the thickness of second well region 212 is larger, inject in second well region 212 Electronics is not easy to diffuse in first well region 211, and therefore, the electronics injected in second well region 212 is easy and second The storage unit is written so that the hole concentration in second well region 212 be made to reduce in hole-recombination in well region 212 Data " 0 ".

The reading process of the memory includes: bit line BL and the source of the storage unit by being read in connection Apply current potential on line SL, make the PN junction forward bias between second well region 212 and the first doped region 202, even if institute's rheme Current potential on line BL is less than the current potential on the source line SL；Connect the bit line BL and source line of the storage unit without write operation SL is hanging.The storage unit being read can be uniquely determined by the source line SL and bit line BL.On the bit line BL Current potential be less than the current potential then PN junction forward bias between second well region 212 and the first doped region 202 on the source line SL It sets, the bit line BL and source line SL conducting read electric current to generate in the bit line BL, can according to the reading electric current Obtain data stored in the storage unit.

If data stored in the storage unit are " 1 ", the hole in the second well region 212 of the storage unit is dense Spend it is higher, and in the inversion layer electronics concentration it is higher, the conduction type of institute's inversion layer is N-type.The inversion layer, first are mixed Miscellaneous area 202 and the second well region 212 constitute diode, and the inversion layer and the first doped region 202 connect with second well region 212 Touching, to increase the PN junction area of the diode；In addition, the hole concentration in second well region 212 is higher, described two The width of the PN junction depletion layer of pole pipe is smaller.To sum up, when data stored in the storage unit are " 1 ", the reading electric current It is larger；, whereas if data stored in the storage unit are " 0 ", the reading electric current is smaller.Therefore, by described The analysis for reading electric current, can read data stored in the storage unit.

Similarly, in other embodiments, first Doped ions are P-type ion；Second Doped ions be N-type from Son；The third Doped ions are P-type ion.

When being injected with electronics in second well region, the data of the storage unit storage are " 1 "；When second trap When injected electrons being not present in area, the data of the storage unit storage are " 0 ".

To storage unit write-in data " 1 " principle include: make connection carry out write operation storage unit wordline and Voltage between the line of source is less than zero；The voltage for carrying out connection between the bit line and source line of the storage unit of write operation is less than Zero.Connection is equal to zero without the voltage between the wordline and source line of the storage unit of write operation, and connection is grasped without write-in Voltage between the bit line and source line of the storage unit of work is equal to zero.Apply identical current potential on the active line of institute, or institute is active Line is hanging.The storage unit being written can be uniquely determined by the wordline and bit line.It is written when the connection When voltage between the wordline and source line of storage unit is less than zero, the second well region transoid of the gate structure bottom forms transoid Layer, while electronics is injected into the second well region of the inversion layer bottom.Due to connecting the bit line and source line of the storage unit Between voltage less than zero, then the PN junction reverse bias between the first doped region and the second well region of the storage unit, but by Injected electrons is limited in described the in the PN junction reverse bias that the first well region and the second well region are formed, second well region In two well regions, to make that data " 1 " is written in the storage unit.

Process to storage unit write-in data " 0 " be to discharge the process of electronics in second well region, and described in erasing The process of data " 1 " is identical in storage unit.Specifically, including: to carry out connection to the principle of storage unit write-in data " 0 " Voltage between the wordline and source line of write operation storage unit is greater than zero；Connection is set to carry out the bit line of write operation storage unit Voltage between the line of source is greater than zero.Apply identical current potential on the active line of institute, or the active line of institute is hanging.Pass through the wordline The storage unit being written can be uniquely determined with bit line.When connection carries out the wordline and source line of the storage unit of write operation Between voltage when being greater than zero, the inversion layer of the gate structure bottom disappears, and the thickness of second well region increases.Due to even The voltage tapped between the bit line of the storage unit of row write operation and source line is greater than zero, then the first doping of the storage unit PN junction forward bias between area and the second well region, the hole in first doped region are injected in second well region.And by Larger in the thickness of second well region, the hole injected in second well region is not easy to diffuse in first well region, Therefore, it is easy to be compound with the electronics in the second well region to inject the hole in second well region, to make in second well region Electron concentration reduce, make storage unit write-in data " 0 ".

The reading process of the memory includes: by the bit line and source line that connection is read storage unit Apply current potential, makes the PN junction forward bias between second well region and the first doped region, even if the current potential on the bit line is big Current potential on the source line；Bit line and the source line for connecting the storage unit without write operation are hanging.Pass through the source line The storage unit being read out can be uniquely determined with bit line.Current potential on the bit line is greater than the then institute of the current potential on the source line The knot forward bias between the second well region and the first doped region, the bit line and the conducting of source line are stated, to produce in the bit line It is raw to read electric current, data stored in the storage unit can be obtained according to the reading electric current.

First Doped ions are P-type ion, described when making the second well region injection electronics in writing process Storage unit stores data is " 1 ".If data stored in the storage unit are " 1 ", the second trap of the storage unit Electron concentration in area is higher, and in the inversion layer hole concentration it is higher, the conduction type of institute's inversion layer is p-type.It is described Inversion layer, the first doped region and the second well region constitute diode, the inversion layer and the first doped region with second well region Contact, to increase the PN junction area of the diode；In addition, the electron concentration in second well region is higher, described two The width of the PN junction depletion layer of pole pipe is smaller.To sum up, when data stored in the storage unit are " 1 ", the reading electric current It is larger；, whereas if data stored in the storage unit are " 0 ", the reading electric current is smaller.Therefore, by described The analysis for reading electric current, can read data stored in the storage unit.

In the present embodiment, the substrate 200 is planar substrate, such as silicon substrate, germanium substrate or silicon-Germanium substrate.In other realities It applies in example, the substrate can also include substrate and the fin in the substrate；The gate structure across the fin, And the gate structure covers the fin partial sidewall and top surface；Second well region is located in the fin, described First well region is located in one of fin and substrate or both combination.

The gate structure 201 includes: the gate dielectric layer positioned at 212 surface of the second well region；Positioned at the gate medium Grid on layer；Side wall positioned at the gate lateral wall surface.

In the present embodiment, the material of the gate dielectric layer is silica.The material of the grid be polysilicon, polycrystalline germanium or Polycrystalline silicon germanium.

In other embodiments, the material of the gate dielectric layer can be high K medium material.The material of the grid is gold Belong to.

In the present embodiment, the material of the side wall is silicon nitride.

The storage unit further include: positioned at the isolation well region of the isolated area 231, have in the isolation well region 231 Ion is isolated, the isolation ion is opposite with the conduction type of second Doped ions；Positioned at the isolation well region and storage Isolation structure 230 between the second well region of cellular zone 212 in substrate 200.

The material of the isolation structure 230 is silica, silicon nitride or silicon oxynitride.

The isolation well region 231 and isolation structure 230 are for realizing between consecutive storage unit area the second well region of A 212 It is electrically isolated.

The embodiment of the present invention also provides a kind of working method of memory.

Referring to FIG. 4, providing memory.

Memory in the present embodiment is identical as Fig. 2 in a upper embodiment and memory shown in Fig. 3, does not do herein superfluous It states.

With continued reference to Fig. 4, first well region 211 is made to connect the first current potential V₀₁, the first current potential V₀₁Make described first PN junction reverse bias between well region 211 and the second well region 212.

The first current potential V₀₁Make the PN junction reverse bias between first well region 211 and the second well region 212, so as to Enough prevent the charge in second well region 212 from discharging, to reduce electric leakage.

Specifically, in the present embodiment, by making trap line DNWL the first current potential of connection V₀₁, to make first well region 211 the first current potential V of connection₀₁。

In the present embodiment, first Doped ions are N-type ion.In other embodiments, first Doped ions For P-type ion.

In the present embodiment, the first current potential V₀₁For making the PN junction between first well region 211 and the second well region 212 Reverse bias, then the first current potential V₀₁Greater than the current potential of second well region 212.In other embodiments, described first mixes Heteroion is P-type ion, then first current potential is less than the current potential of second well region.

If the first current potential V₀₁Potential difference between the second well region 212 is too small, is unfavorable for maintaining the first well region 211 With the PN junction reverse bias between the second well region 212；If the first current potential V₀₁With the potential difference mistake between the second well region 212 It is small excessive, it is easy to increase the energy consumption of memory.Specifically, in the present embodiment, the first current potential V₀₁Between the second well region 212 Potential difference it is too small be 1.8V~2.2V, such as 2V.In the present embodiment, in subsequent write operation and read operation, make institute It states source line SL and connects zero potential, or keep the source line SL hanging, then the first current potential V₀₁For 1.8V~2.2V, such as 2V.

In conjunction with reference Fig. 5 and Fig. 6, write operation is carried out to the memory, the method for said write operation includes: to institute It states the first doped region 202 and applies the second current potential V₀₂, the second current potential V₀₂Make between gate structure 201 and the second well region 212 Voltage is first voltage；Third current potential V is applied to the gate structure 201₀₃, the third current potential V₀₃Make the first doped region 203 Voltage between the second well region 212 is second voltage, and the second voltage is positive and negative identical as first voltage.

Said write operation includes: write-in data " 1 " operation and write-in data " 0 " operation.

When the second voltage is positive and negative identical as first voltage, 201 the second well region of bottom of gate structure, 212 transoid Form inversion layer, and the PN junction reverse bias between first doped region 202 and the second well region 212；Or the grid knot The inversion layer of 201 bottom of structure disappears, and the PN junction forward bias between first doped region 202 and the second well region 212.Work as institute 201 the second well region of bottom of gate structure, 212 transoid is stated, and the PN junction between first doped region 202 and the second well region 212 is anti- To when biasing, charge is injected in the second well region 212 of the bottom；When the 201 bottom inversion layer of gate structure disappears, and institute When stating the PN junction forward bias between the first doped region 202 and the second well region 212, the charge in second well region 212 is discharged. Therefore, the memory can indicate different storage states by whether injecting charge in second well region 212, in turn Storing data " 1 " and " 0 ".

Specifically, in the present embodiment, when injecting hole in second well region 212, the storage of the storage unit Data are " 1 "；When not having injected holes in second well region 212, the data of the storage of the storage unit are “0”。

In other embodiments, first Doped ions are N-type ion, when injecting hole in second well region, The data of the storage of the storage unit are " 0 "；When not having injected holes in second well region, the storage unit Storage data be " 1 ".Alternatively, first Doped ions are P-type ion, when injecting electronics in second well region, The data of the storage of the storage unit are " 1 "；When not having injected electrons in second well region, the storage unit Storage data be " 0 ".Alternatively, stating the first Doped ions is P-type ion, and when injecting electronics in second well region, institute The data for stating the storage of storage unit are " 0 "；When not having injected electrons in second well region, the storage unit The data of storage are " 1 ".

The method of said write operation further include: the 4th current potential V is applied to source line SL₀₄, or keep the source line SL hanging.

In the present embodiment, the 4th current potential V₀₄For zero potential, or keep the source line SL hanging.Specifically, this implementation In example, the 4th current potential V₀₄For zero potential.To the source line SL apply zero potential can make the current potential on the source line SL compared with Stablize, to reduce the interference of noise.And the 4th current potential is that zero potential can reduce energy consumption.

In the present embodiment, the 4th current potential V₀₄For zero potential, or keep the source line SL hanging, then the mistake of read operation Cheng Zhong, the second current potential V₀₂With third current potential V₀₃It is positive and negative identical.

In the present embodiment, the principle to storage unit write-in data " 1 " is identical as a upper embodiment, seldom does herein superfluous It states.

In the present embodiment, first Doped ions are N-type ion.When data " 1 " is written, the second current potential V₀₂Greatly Current potential on the source line SL；The third current potential V₀₃Greater than the current potential on the source line SL.Specifically, when write-in data When " 1 ", the current potential of the source line SL is zero potential 0, the second current potential V₀₂Greater than 0, the third current potential V₀₃Greater than 0.

In the present embodiment, first Doped ions are N-type ion.When data " 0 " is written, the second current potential V₀₂It is small Current potential on the source line SL；The third current potential V₀₃Less than the current potential on the source line SL.Specifically, the source line SL Current potential is zero potential 0；When data " 0 " is written, the second current potential V₀₂Less than 0, the third current potential V₀₃Less than 0.

In other embodiments, the current potential on the source line is nonzero value.

It should be noted that the storage unit be it is multiple, multiple storage units are arranged as storage array；The storage battle array It is electrically connected to each other with the gate structure 201 of the storage unit of a line by same wordline WL in column；It is same in the storage array First doped region 202 of the storage unit of column is electrically connected to each other by same bit line BL；Depositing with a line in the storage array Second doped region 203 of storage unit is electrically connected to each other by same source line SL.

4th current potential V is applied to the source line SL₀₄Method include: make all storage units source line SL apply the 4th electricity Position V₀₄；The method for keeping the source line SL hanging includes: to keep the source line SL of all storage units hanging.

The wordline includes the first wordline and the second wordline, and the first wordline connection carries out the storage list of write operation Member；The bit line includes the first bit line and the second bit line, and the first bit line connection carries out the storage unit of write operation.

When carrying out write operation to one or more storage units, the second current potential V is applied to the bit line BL₀₂Method It include: that the second current potential V is applied to first bit line₀₂；Third current potential V is applied to the wordline WL₀₃Method include: to institute It states the first wordline and applies third current potential V₀₃。

The method of said write operation further include: zero potential 0 is applied to second bit line, or makes second bit line Vacantly；Zero potential 0 is applied to second wordline, or keeps second wordline hanging.

Since the gate structure 201 in the storage array with the storage unit of a line is mutually electrically connected by same wordline WL It connects, the gate structure 201 of the storage unit of same row is electrically insulated；The first of the storage unit of same row is mixed in the storage array Miscellaneous area 202 is electrically connected to each other by same bit line BL, with the first doped region 202 electrical isolation of the storage unit of a line, then by one Group wordline WL and bit line BL can uniquely determine a storage unit.

Therefore, in the present embodiment, the source line SL connects zero potential or hanging, then the wordline WL when storage unit connection or position When one of line BL or two kinds of current potential are zero potential 0, the storage state of the storage unit is constant.Therefore, it is with current potential Data " 1 " is written in the storage unit that the wordline WL and bit line BL of positive potential are connected simultaneously；It is the wordline WL of negative potential with current potential Data " 0 " is written with the storage unit that bit line BL is connected simultaneously.Therefore, it can be selected by the current potential of the bit line BL and wordline WL Select the storage unit for carrying out write operation.

During data " 1 " is written, if the first voltage is too small, it is easy to cause in second well region 202 Injected holes diffuses into the first doped region 202, to generate leakage current；If the first voltage is excessive, it is easy to increase Add energy consumption.Specifically, the first voltage is 0.7V~0.9V, such as 0.8V in the present embodiment.Specifically, the source line SL Bit line be that zero potential or the source line SL are hanging, then the second current potential V₀₂For 0.7V~0.9V, such as 0.8V.

In other embodiments, first Doped ions are P-type ion, when injecting electronics in second well region, It is written data " 1 ".During data " 1 " is written, the first voltage is less than 0.Specifically, the first voltage be- 0.55V~-0.45V, such as -0.5V.

During data " 1 " is written, if the second voltage is too small, it is easy to cause in second well region 212 Hole concentration it is lower, when so as to cause reading " 1 " or " 0 ", the reading current difference is away from smaller, to be easy to appear reading Error；If the second voltage is excessive, it is easy to increase the energy consumption of write-in " 1 ", and be easy to cause in second well region 212 The excessive concentration in hole is easy to keep the absolute value of current potential when wiping data excessively high, to increase the energy consumption of write-in " 0 ".This reality It applies in example, the second voltage is 0.7V~0.9V, such as 0.8V.Specifically, the current potential on the source line SL is zero potential, or Source line SL described in person is hanging, the third current potential V₀₃For 0.7V~0.9V, such as 0.8V.

In other embodiments, first Doped ions are P-type ion, when injecting electronics in second well region, It is written data " 1 ".When data " 0 " is written, the third current potential is less than 0.Specifically, the second voltage be -0.55V~- 0.45V, such as -0.5V.

In the present embodiment, when data " 0 " is written, the current potential on the source line SL is zero potential or the source line SL Vacantly；The second current potential V₀₂With third current potential V₀₃Respectively less than 0.

When data " 0 " is written, if the absolute value of the first voltage is too small, it is unfavorable in second well region 212 The release in hole, to be easy to cause the hole concentration in second well region 212 higher, thus be easy to cause reading " 1 " or When " 0 ", the reading current difference is away from smaller, to be easy to appear reading error；If the absolute value of the first voltage is excessive, It is easy to increase energy consumption.In the present embodiment, first voltage is -0.55V~-0.45V.Specifically, the current potential on the source line SL is Zero potential or the source line SL are hanging；The second current potential V₀₂For -0.55V~-0.45V.

In other embodiments, first Doped ions are P-type ion, when discharging electronics When, it is written data " 0 ".During data " 0 " is written, second current potential is greater than 0.Specifically, second current potential is 0.7V~0.9V, such as 0.8V.

When data " 0 " is written, if the absolute value of the second voltage is too small, it is not easy to so that inversion layer is disappeared, thus It is unfavorable for the release of charge in the second well region 212；And it is easy to cause the thickness of second well region 212 smaller, when write-in data When " 0 ", the electronics for entering second well region 212 from first doped region 202 is readily diffused into the first well region 211, To be unfavorable for discharging the hole in second well region 212；If the absolute value of the second voltage is excessive, it is easy to increase energy Consumption.In the present embodiment, the second voltage is -0.55V~-0.45V, such as -0.5V.Specifically, stating the current potential on the line SL of source It is hanging for zero potential or the source line SL；The third current potential V₀₃For -0.55V~-0.45V, such as -0.5V.

In other embodiments, first Doped ions are P-type ion, when discharging electronics When, it is written data " 0 ".During data " 0 " is written, the second voltage is greater than 0.Specifically, the second voltage is 0.7V~0.9V, such as 0.8V.

Referring to FIG. 7, being read to the memory, the side of the read operation after said write operation Method includes: to apply the first reading potential V to the bit line BL₁₁；Second reading potential V is applied to the source line SL₁₂, described One reading potential V₁₁With the second reading potential V₁₂Make the PN junction forward bias between the first doped region 202 and the second well region 212； First reading potential V is applied to the bit line BL₁₁Later, the second reading potential V is applied to the source line SL₁₂Later, pass through institute Reading electric current in rheme line BL obtains and reads data.

During read operation, the first reading potential V₁₁With the second reading potential V₁₂Make the first doped region 202 with PN junction forward bias between second well region 212, the then diode that first doped region 202 is constituted with the second well region 212 are led It is logical, electric current is read to make to generate in the bit line BL.During write operation, injected in the second well region of Xiang Suoshu 212 Charge, it is described anti-during read operation when forming inversion layer in the second well region 212 below the gate structure 201 Type layer, the first doped region 202 and the second well region 212 constitute diode, and the inversion layer can increase PN junction in the diode Area, to keep the reading electric current larger；Conversely, making second well region 212 discharge electricity during write operation When lotus, the reading electric current is smaller.Therefore, by the size for reading electric current, it can read and store in the memory Data.In addition, due in reading the memory during data, by making the second well region 212 and the first doped region 202 The diode forward of composition is connected, to obtain reading data.Due to the pressure drop very little of the forward conduction of diode, to make institute The energy consumption for stating memory is lower.

In the present embodiment, first Doped ions are N-type ion, the first reading potential V₁₁It is read less than described second Take current potential V₁₂.In other embodiments, first Doped ions are P-type ion, and first reading potential is greater than described the Two reading potentials.

Specifically, first Doped ions are N-type ion, the first reading potential V in the present embodiment₁₁For negative electricity Position；The second reading potential V₁₂For zero potential.In other embodiments, first reading potential is zero potential；Described Two reading potentials are positive potential.

In the present embodiment, the principle of the read operation of the memory is identical as a upper embodiment, and this will not be repeated here.

In the present embodiment, the second reading potential V₁₂With the first reading potential V₁₁Difference be read voltage.The reading Voltage is taken to be greater than zero.In other embodiments, first Doped ions are P-type ion, and the reading voltage is less than zero.

Fig. 8 is the relation curve read between electric current and reading voltage of memory of the invention during read operation Figure；Curve b is to read electric current when the data stored in storage unit are " 1 " and read the graph of relation between voltage；It is bent Line a is to read electric current when the data stored in storage unit are " 0 " and read the graph of relation between voltage.

As seen from Figure 8, the readings electric current when the data stored in storage unit are " 1 " is greater than storing in storage unit Reading electric current when data are " 0 ".Therefore, the data for reading and storing in storage unit can be obtained by the value of reading electric current.

In the present embodiment, the storage unit being read is selected by the current potential on the source line SL and bit line BL.

During read operation, the source line SL include the first source line and the second source line, first source line connect into The storage unit of row read operation；The bit line BL includes third bit line and the 4th bit line；The third bit line connection is read The storage unit of extract operation.

Specifically, the method for the read operation includes: to apply the first reading potential V to the third bit line₁₁；To described First source line applies the second reading potential V₁₂, the second reading potential V₁₂With the first reading potential V₁₁Make the first doped region 202 With the PN junction forward bias between the second well region 212；Keep second source line hanging；Keep the 4th bit line hanging.

When the combination of one of described source line SL and bit line BL and the two is hanging, connect source line SL's and bit line BL Electric current is not formed in storage unit.When the current potential of the source line SL and bit line BL that connect same storage unit make the second of storage unit When the diode current flow that well region 212 and the first doped region 202 are constituted, connects in the bit line BL of the storage unit and generate electric current.Cause This, can select the storage unit being read by the current potential on bit line BL and source line SL.

In the present embodiment, obtaining the method for reading data by the reading electric current includes: when the reading electric current is greater than When predetermined current, reading data is " 1 "；When the reading electric current is less than predetermined current, reading data is " 0 ".

In other embodiments, first Doped ions are N-type ion；When the first voltage is less than zero, described When two voltages are less than zero, be written data " 1 "；When the first voltage is greater than zero, and the second voltage is greater than zero, data are written "0"；Obtaining the method for reading data includes: when the reading electric current is less than predetermined current, and the reading data are "1"；When the reading electric current is greater than predetermined current, the reading data are " 0 ".

Alternatively, first Doped ions are P-type ion；When the first voltage is less than zero, the second voltage is less than When zero, be written data " 1 "；When the first voltage is greater than zero, and the second voltage is greater than zero, be written data " 0 "；Obtain institute Stating the method for reading data includes: when the reading electric current is greater than predetermined current, and the reading data are " 1 "；When the reading When obtaining current is less than predetermined current, the reading data are " 0 ".

Alternatively, first Doped ions are P-type ion；When the first voltage is greater than zero, the second voltage is greater than When zero, be written data " 1 "；When the first voltage is less than zero, and the second voltage is less than zero, be written data " 0 "；Obtain institute Stating the method for reading data includes: when the reading electric current is less than predetermined current, and the reading data are " 1 "；When the reading When obtaining current is greater than predetermined current, the reading data are " 0 ".

In the present embodiment, first Doped ions are N-type ion, then when the reading voltage is greater than zero, to storage Unit is read.

If the second reading potential V₁₂Absolute value it is excessive, be easy increase energy consumption.Specifically, in the present embodiment, institute State the second reading potential V₁₂For zero potential 0.

If the first reading potential V₁₁Absolute value it is too small, be easy to cause the reading electric current too small, to reduce The sensitivity of the memory；If the first reading potential V₁₁Absolute value it is excessive, be easy to increase energy consumption, and can by Fig. 8 See, the first reading potential V₁₁Absolute value it is excessive when, the reading when data of storage unit storage are " 1 " or " 0 " The difference of electric current is smaller, to be easy to appear read error.Specifically, in the present embodiment, the first reading potential V₁₁For -0.8V ~-0.7V, such as -0.75V.In other embodiments, first Doped ions are P-type ion, first reading potential Greater than zero, specifically, first reading potential is 0.7V~0.8V.

Fig. 9 to Figure 13 is the structural schematic diagram of each step of one embodiment of forming method of semiconductor structure of the present invention.

Referring to FIG. 9, providing substrate 200.

The substrate 200 includes the multiple memory cell areas A and isolated area B between consecutive storage unit area A.Respectively Memory cell areas A is used to form storage unit.

In the present embodiment, the substrate 200 is planar substrate 200, such as silicon substrate, germanium substrate or silicon-Germanium substrate.At it In his embodiment, described includes: substrate and the fin in the substrate.

The isolated area B surrounds the memory cell areas A.

With continued reference to Fig. 9, the first well region 211 is formed in the substrate 200, has first in first well region 211 Doped ions；The second well region 212 is formed in 211 top surface of the first well region, has second to mix in second well region 212 Heteroion, second Doped ions are opposite with the conduction type of first Doped ions.

In the present embodiment, the forming method further include: isolation well region 232 is formed in the isolated area B substrate 200, The isolation well region 232 is located at 211 top surface of the first well region, has isolation ion in the isolation well region 232, described The conduction type that ion is isolated is opposite with the conduction type of second Doped ions.

The isolation well region 232 is for realizing the electric isolution between the second adjacent well region 212.

It in the present embodiment, is formed after first well region 211, forms second well region 212 and isolation well region 232.

Specifically, injecting the first Doped ions in the substrate 200 by the first ion implantation technology, the first trap is formed Area 211.

The method for forming second well region 212 includes: to form the first graph layer on the isolated area B substrate 200；With First graph layer is that exposure mask carries out the second ion implanting to the substrate 200, the storage at 211 top of the first well region The second well region 212 is formed in cellular zone A substrate 200.

The method for forming the isolation well region 232 includes: to form second graph on the memory cell areas A substrate 200 Layer；Third ion implanting is carried out to the substrate 200 using the second graph layer as exposure mask, at 211 top of the first well region Isolated area B substrate 200 in formed isolation well region 232.

In the present embodiment, first Doped ions are N-type ion, such as phosphonium ion or arsenic ion；Second doping Ion is P-type ion, such as boron ion or BF₂ ⁺Ion；The isolation ion is N-type ion, such as phosphonium ion or arsenic ion.? In other embodiments, first Doped ions are P-type ion, such as boron ion or BF₂ ⁺Ion；Second Doped ions are N-type ion, such as phosphonium ion or arsenic ion；The isolation ion is P-type ion, such as boron ion or BF₂ ⁺Ion.

Referring to FIG. 10, shape in substrate 200 between the isolation well region 232 and the second well region of memory cell areas B 212 At isolation structure 230.

The material of the isolation structure 230 is silica.

It is subsequent to form gate structure on 212 surface of the second well region, and form first in second well region 212 and mix Miscellaneous area, the gate structure include opposite the first side and second side, and first doped region 202 is located at the gate structure In second well region 212 of side, there is third Doped ions, the third Doped ions and institute in first doped region 202 The conduction type for stating the second Doped ions is opposite.

The forming method further include: the second doped region, second doping position are formed in second well region 212 In second well region 212 of described gate structure second side

In the present embodiment, the gate structure, the first doped region and the second doped region are formed by preceding grid technique.At other In embodiment, the gate structure, the first doped region and the second doped region can be formed by rear grid technique.

Specifically, forming method such as Figure 11 of the gate structure, the second doped region and the first doped region in the present embodiment With shown in Figure 12.

Figure 11 is please referred to, forms gate structure 201 on 212 surface of the second well region, the gate structure 201 includes phase Pair the first side and second side.

The gate structure 201 includes the gate dielectric layer positioned at 212 surface of the second well region；Positioned at the gate dielectric layer The grid on surface；Side wall positioned at the gate lateral wall surface.

In the present embodiment, the material of the gate dielectric layer is silica.The material of the grid be polysilicon, polycrystalline germanium or Polycrystalline silicon germanium.In other embodiments, the material of the gate dielectric layer is high K medium material；The material of the grid is metal, The technique for then forming the gate structure and the first doped region includes preceding grid technique or rear grid technique.

In the present embodiment, the material of the side wall is silicon nitride or silicon oxynitride.

1 is continued to refer to figure 1, forms the first doped region 202 in the second well region 212 of 202 first side of gate structure, There is third Doped ions, the conduction type of the third Doped ions and second doping in first doped region 202 The conduction type of ion is opposite.

The method for forming first doped region 202 includes: to form the second trap for covering described 201 second side of gate structure First mask layer in area 212；It is second well region of the exposure mask to second side with first mask layer and the gate structure 201 212 carry out the first source and drain ion implanting, and third Doped ions, the third Doped ions are injected in second well region 212 It is opposite with the conduction type of second Doped ions.

In the present embodiment, second Doped ions are P-type ion, and the third Doped ions are N-type ion, such as phosphorus Ion or arsenic ion.In other embodiments, second Doped ions be N-type ion, the third Doped ions be p-type from Son, such as boron ion or BF₂ ⁺Ion.

Figure 12 is please referred to, forms the second doped region 203, institute in second well region 212 of described 202 second side of gate structure State in the second doped region 203 have the 4th Doped ions, the conduction type of the 4th Doped ions with described second adulterate from The conduction type of son is identical.

The method for forming second doped region 203 includes: to form the second trap for covering 201 first side of gate structure Second mask layer in area 212；It is that exposure mask carries out the second well region of second side 212 with second mask layer and gate structure 201 Second source and drain ion implanting injects the 4th Doped ions, the 4th Doped ions and described the in second well region 212 The conduction type of two Doped ions is identical.

In the present embodiment, second Doped ions are P-type ion, and the 4th Doped ions are P-type ion, such as boron Ion or BF₂ ⁺Ion.In other embodiments, second Doped ions are N-type ion, and the 4th Doped ions are N-type Ion, such as phosphonium ion or arsenic ion.

The first well region 211, the second well region 212, gate structure 202,203 and of the second doped region of one memory cell areas A First doped region 202 constitutes a storage unit.

The semiconductor structure includes multiple memory cell areas A, and multiple memory cell areas A are arranged as storage array； The number of the storage unit be it is multiple, multiple storage units are arranged as storage array.

In the present embodiment, the gate structure 201 in the storage array with the memory cell areas of a line, to make Gate structure 201 with the storage unit of a line is connected with each other.

In other embodiments, the substrate includes substrate and the fin in the substrate.The gate structure is horizontal Across the fin, and cover the fin partial sidewall and top surface.First well region is located at one in substrate and fin In person or both combination；Second well region is located in fin.

Figure 13 is please referred to, the wordline (not shown) being electrically connected with the gate structure 201 is formed；It is formed and described the The bit line BL of one doped region 202 electrical connection；Form the source line SL being electrically connected with second well region 212；It is formed and described first The trap line (not shown) that well region 211 is electrically connected.

Gate structure 201 in the storage array with the storage unit of a line is electrically connected with same wordline；The storage It is electrically connected with the second doped region 203 of the storage unit of a line with same source line SL in array；Same row in the storage array The first doped region 202 of storage unit be electrically connected with same bit line BL.

Forming method further include: formed and cover the gate structure 201, the second doped region 203 and the first doped region 202 Dielectric layer；The second plug 243 is formed in the dielectric layer, second plug 243 is contacted with second doped region 203； The source line SL is located at 243 surface of the second plug.

In the present embodiment, the dielectric layer includes: the covering gate structure 201, the second doped region 203 and the first doping The first medium floor 251 in area 202；Second dielectric layer 252 on the first medium layer 251；Positioned at the first medium The first plug in layer 251, first plug run through the first medium layer, and first plug 241 and described first Doped region 202 contacts；Gate plug and the second plug 243 in the first medium layer 251 and second dielectric layer 252, Second plug 243 is through to the second dielectric layer 252 from the first medium layer 251, and second plug 243 with Second doped region 203 contacts, and the gate plug is through to the second dielectric layer 252 from the first medium layer 251, And the gate plug is contacted with the gate structure 201.

The bit line BL is located at the first medium layer 251 and 241 surface of the first plug；The wordline WL is located at institute State 252 surface of gate plug and the second dielectric layer；The source line SL is located at the second dielectric layer 252 and described second and inserts Fill in 243 surfaces.

Specifically, forming the dielectric layer, the second plug 243, source line SL, the first plug 241, bit line in the present embodiment The method of BL, gate plug and wordline include: to form the covering gate structure 201, the second doped region and the first doped region First medium layer 251；The first contact hole is formed in the first medium layer 251, the first contact hole bottom-exposed goes out institute State the first doped region 202；The first plug 241 is formed in first contact hole；In first plug 241 and described first 251 surface of dielectric layer forms bit line BL；Second dielectric layer 252 is formed in the first medium layer 251 and the surface the bit line BL； Form the second contact hole that second dielectric layer 252 is through to from the first medium layer 251, the second contact hole bottom-exposed The gate structure 201 out；The third contact hole that second dielectric layer 252 is through to from the first medium layer 251 is formed, it is described Third contact hole bottom-exposed goes out second doped region 203；The second plug 243 is formed in the third contact hole；Institute It states 252 surface of second dielectric layer and 241 surface of the gate plug and forms wordline WL；Second is formed in the third contact hole Plug 243；Source line SL is formed on 252 surface of second dielectric layer and 243 surface of the second plug.

The wordline WL is not contacted with the source line SL.

Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute Subject to the range of restriction.

Claims (19)

1. a kind of memory characterized by comprising

Substrate；

The first well region in the substrate has the first Doped ions in first well region；

Positioned at the second well region of the first well region top surface, there are the second Doped ions in second well region, described the Two Doped ions are opposite with the conduction type of first Doped ions；

Gate structure positioned at second well region surface, the gate structure include opposite the first side and second side；

The first doped region in the second well region of first side of gate structure is mixed with third in first doped region Heteroion, the conduction type of the third Doped ions are opposite with the conduction type of second Doped ions；

The wordline being electrically connected with the gate structure；

The bit line being electrically connected with first doped region；

The source line being electrically connected with second well region.

2. memory as described in claim 1, which is characterized in that first Doped ions are N-type ion, and described second mixes Heteroion is P-type ion, and the third Doped ions are N-type ion；

Alternatively, first Doped ions are P-type ion, second Doped ions are N-type ion, the third Doped ions For P-type ion.

3. memory as described in claim 1, which is characterized in that the memory includes multiple storage units, the storage Unit includes: first well region, the second well region, gate structure and first doped region.

4. memory as claimed in claim 3, which is characterized in that multiple storage units are arranged as storage array；The storage Gate structure in array with the storage unit of a line is electrically connected to each other by same wordline；Same row in the storage array First doped region of storage unit is electrically connected to each other by same bit line；With the of the storage unit of a line in the storage array Two doped regions are electrically connected to each other by same source line.

5. memory as described in claim 1, which is characterized in that further include: positioned at the second of described gate structure second side The second doped region in well region, has the 4th Doped ions in second doped region, and the 4th Doped ions are mixed with second The conduction type of heteroion is identical, and the concentration of the 4th Doped ions is greater than the in second well region in second doped region The concentration of two Doped ions；The source line is electrically connected with second doped region.

6. memory as claimed in claim 5, which is characterized in that further include: cover the gate structure, the second doped region and The first medium layer of first doped region；The first plug in the first medium layer, first plug is through described the One dielectric layer, and contacted with first doped region, the bit line is located at the first medium layer and first plug surface； Positioned at the second dielectric layer of the bit line and first medium layer surface；The second dielectric layer is through to from the first medium layer The second plug, second plug contacts with second doped region；The source line is located at second plug and described Second medium layer surface.

7. a kind of working method of memory characterized by comprising

Memory as described in claim 1 to 6 any one is provided；

First current potential is applied to first well region, makes the PN junction reverse bias between first well region and the second well region；

Write operation is carried out to the memory, the method for said write operation includes: to apply the second current potential to the bit line, is made Voltage between first doped region and the second well region is first voltage；To the wordline apply third current potential, make gate structure with Voltage between second well region is second voltage, and the second voltage is positive and negative identical as first voltage；

After said write operation, the memory is read, the method for the read operation includes: to institute's rheme Line applies the first reading potential；Second reading potential, first reading potential and the second reading potential are applied to the source line Make the PN junction forward bias between the first doped region and the second well region；After applying the first reading potential to the bit line, to institute After stating source line the second reading potential of application, passes through the reading electric current in the bit line, obtain and read data.

8. the working method of memory as claimed in claim 7, which is characterized in that first Doped ions are N-type ion, First current potential is greater than the current potential of second well region；

Alternatively, first Doped ions are P-type ion, first current potential is less than the current potential of second well region.

9. the working method of memory as claimed in claim 7, which is characterized in that the method for said write operation further include: Keep the source line hanging, or the 4th current potential is applied to the source line, the 4th current potential is zero potential；

When first Doped ions are N-type ion, first current potential is 1.8V~2.2V；

Second current potential is 0.7V~0.9V, and the third current potential is 0.7V~0.9V；Alternatively, second current potential be- 0.55V~-0.45V, the third current potential are -0.55V~-0.45V.

10. the working method of memory as claimed in claim 7, which is characterized in that the memory includes that multiple storages are single Member, the storage unit include: first well region, the second well region, gate structure and first doped region；Multiple storages are single Identical permutation is storage array；Gate structure in the storage array with the storage unit of a line is mutually electrically connected by same wordline It connects；The first doped region of the storage unit of same row is electrically connected to each other by same bit line in the storage array；The storage It is electrically connected to each other with the second doped region of the storage unit of a line by same source line in array；

The wordline includes the first wordline and the second wordline, and the first wordline connection carries out the storage unit of write operation；Institute Rheme line includes the first bit line and the second bit line, and the first bit line connection carries out the storage unit of write operation；To institute's rheme The method that line applies the second current potential includes: to apply the second current potential to first bit line；Third current potential is applied to the wordline Method includes: to apply third current potential to first wordline；

The method of said write operation further include: zero potential is applied to second bit line, or keeps second bit line hanging；It is right Second wordline applies zero potential, or keeps second wordline hanging.

11. the working method of memory as claimed in claim 7, which is characterized in that first Doped ions be N-type from Son, first reading potential are less than second reading potential；

Alternatively, first Doped ions are P-type ion, first reading potential is greater than second reading potential.

12. the working method of memory as claimed in claim 7, which is characterized in that first Doped ions be N-type from Son；When the first voltage is greater than zero, and the second voltage is greater than zero, be written data " 1 "；Alternatively, described first adulterate from Son is P-type ion；When the first voltage is less than zero, and the second voltage is less than zero, be written data " 1 "；

Obtaining the method for reading data includes: when the reading electric current is greater than predetermined current, and the reading data are "1"；When the reading electric current is less than predetermined current, the reading data are " 0 ".

13. the working method of memory as claimed in claim 12, which is characterized in that first Doped ions be N-type from Son；The method of the read operation further include: apply zero potential in the wordline, or keep the wordline hanging；

First reading potential is -0.8V~-0.7V；Second reading potential is zero potential.

14. the working method of memory as claimed in claim 7, which is characterized in that the memory includes that multiple storages are single Member, the storage unit include: first well region, the second well region, gate structure and first doped region；Multiple storages are single Identical permutation is storage array；Gate structure in the storage array with the storage unit of a line is mutually electrically connected by same wordline It connects, the first doped region of the storage unit of same row is electrically connected to each other by same bit line in the storage array, with a line Second doped region of storage unit is electrically connected to each other by same source line；

The source line includes the first source line and the second source line, and first source line connects the storage unit being read；Institute Rheme line includes third bit line and the 4th bit line, and the third bit line connects the storage unit being read；

It include: that the first reading potential is applied to the third bit line to the method that the bit line applies the first reading potential；To institute Stating source line to apply the method for the second reading potential includes: to apply the second reading potential to first source line, and described second reads Current potential and the first reading potential make the PN junction forward bias between second well region and the first doped region；

The method of the read operation further include: keep the 4th bit line hanging；Keep second source line hanging.

15. a kind of forming method of memory characterized by comprising

Substrate is provided；

The first well region is formed in the substrate, and there are the first Doped ions in first well region；

The second well region is formed in the first well region top surface, there are in second well region the second Doped ions, described the Two Doped ions are opposite with the conduction type of first Doped ions；

Gate structure is formed on second well region surface, and forms the first doped region, the grid in second well region Structure includes opposite the first side and second side, and first doped region is located at the second well region of first side of gate structure In, there is third Doped ions, the conduction of the third Doped ions and second Doped ions in first doped region Type is opposite；

Form the wordline being electrically connected with the gate structure；

Form the bit line being electrically connected with first doped region；

Form the source line being electrically connected with second well region.

16. the forming method of memory as claimed in claim 15, which is characterized in that formed after the gate structure, shape At first doped region；The method for forming first doped region further include: formed and cover described gate structure second side First mask layer of the second well region；First is carried out to the second well region of second side using first mask layer and gate structure as exposure mask Source and drain ion implanting injects third Doped ions, the third Doped ions and second doping in second well region The conduction type of ion is opposite.

17. the forming method of memory as claimed in claim 15, which is characterized in that further include: in second well region Form the second doped region, second doped region is located at second side of the gate structure, has the in second doped region Four Doped ions, the 4th Doped ions are identical as the conduction type of the second Doped ions, and in second doped region The concentration of four Doped ions is greater than the concentration of the second Doped ions in second well region.

18. the forming method of memory as claimed in claim 17, which is characterized in that formed after the gate structure, shape At second doped region；The method for forming second doped region includes: to form covering first side of gate structure second Second mask layer of well region；Using second mask layer and gate structure as exposure mask to second well region carry out the second source and drain from The 4th Doped ions, the 4th Doped ions and second Doped ions are injected in son injection in second well region Conduction type is identical.

19. the forming method of memory as claimed in claim 17, which is characterized in that formed before the bit line, further includes: Form the first medium layer for covering the gate structure, the second doped region and the first doped region；The shape in the first medium layer At the first plug, first plug runs through the first medium layer, and contacts with first doped region；The bit line is located at The first medium layer and first plug surface；

It is formed after the bit line, further includes: form second dielectric layer in the bit line and first medium layer surface；It is formed from institute The second plug that first medium layer is through to the second dielectric layer is stated, second plug is contacted with second doped region； The bit line is located at second plug and the second medium layer surface.