CN106030718A - Methods of retaining and refreshing data in a thyristor random access memory - Google Patents

Methods of retaining and refreshing data in a thyristor random access memory Download PDF

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Publication number
CN106030718A
CN106030718A CN201580010678.0A CN201580010678A CN106030718A CN 106030718 A CN106030718 A CN 106030718A CN 201580010678 A CN201580010678 A CN 201580010678A CN 106030718 A CN106030718 A CN 106030718A
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memory cell
array
electric current
thyristor
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H·栾
B·贝特曼
V·阿克赛尔拉德
C·程
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Kilopass Technology Inc
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Kilopass Technology Inc
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Priority claimed from US14/590,834 external-priority patent/US9449669B2/en
Application filed by Kilopass Technology Inc filed Critical Kilopass Technology Inc
Priority claimed from PCT/US2015/052505 external-priority patent/WO2016049606A1/en
Publication of CN106030718A publication Critical patent/CN106030718A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/10—DRAM devices comprising bipolar components
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/39—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/402—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh
    • G11C11/4026—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh using bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66363—Thyristors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/87—Thyristor diodes, e.g. Shockley diodes, break-over diodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)

Abstract

A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read, write, retain and refresh data stored therein.

Description

The method of the data kept and refresh in thyristor random access memory
Cross-Reference to Related Applications
Entitled " the Thyristor Volatile Random Access that present patent application relates to same date to be submitted to Memory and Methods of Manufacture " U.S. Patent application No.14/841140, same date submit to topic For " Methods of Reading and Writing Data in a Thyristor Random Access Memory " Entitled " the Power Reduction in Thyristor that U.S. Patent application No.14/841521, same date submit to Random Access " U.S. Patent application No.14/841615；All these applications are desirable that and enjoy in June 29 in 2015 Entitled " High-Density Volatile RAMs, the Method of Operation and Manufacture that day submits to Thereof " the priority of U.S. Provisional Patent Application No.62/186336, and be submit on January 6th, 2015 entitled The U. S. application of " Cross-Coupled Thyristor SRAM Circuits and Methods of Operation " The cip application of No.14/590834, its U.S. Provisional Patent Application No.62/ requiring to enjoy JIUYUE in 2014 submission on the 25th The priority of 055582；The most all applications are incorporated herein.
Background technology
The present invention relates to IC-components, and in particular to being commonly called dynamic random access memory (DRAM) volatile random access memory.
DRAM is a type of random access memory integrated circuit, in the most frequently used commercial implementation, its The separate capacitors of the transistor being coupled in integrated circuit stores each position of data.Capacitor can be electrically charged or put Electricity.The state of charge or discharge is interpreted the value of position, i.e. " 0 " and " 1 ".Between Past 30 Years, one electric capacity of a transistor The unit of device has been the most commercial memory cell used in DRAM device.Photoetching scaling and increase process complexity are Achieve, every about 3 years, the figure place of the memorizer in DRAM is turned over four times, but, individual memory cell is the least, dimension Hold the electric capacity of each unit and to reduce charge leakage be to hinder the subject matter that reduces further of size.
In response to these challenge and other problem, it has been proposed that the DRAM memory cell framework of replacement.One is so Method be referred to as buoyancy aid DRAM (FBDRAM).FBDRAM is the single MOSFET being implemented on silicon-on-insulator (SOI) (Okhonin, Int.SOI Conf., 2001) or be implemented in there is (Ranica, VLSI in three traps of buried N implant Technology, 2004).The main body of transistor defines the capacitor against dielectric substrate.This technology not yet solves its data Preserving problems, especially in the size reduced.
Another kind of method negative differential resistance based on the PNPN thyristor behavior of new DRAM framework.Design at these In, employ active or passive gate.Such as, the thin Capacitance Coupled thyristor described in United States Patent (USP) 6462359 uses Lateral PNP N thyristor in SOI substrate, wherein coupled gates is used for improving switching speed.Regrettably, should The horizontal outward appearance of design, together with its demand to grid, causes memory cell to be noticeably greater than conventional one electricity of a transistor The DRAM cell structure of container.
Liang describes PNPN thyristor unit in United States Patent (USP) 9013918, and it is configured in silicon substrate top also Work in forward and reverse breakdown district, to write data in unit.Regrettably, the rear end at standard CMOS process makes Adding thermal cycle and etching step with extension or CVD semiconductor layer, this can reduce its that be relatively early formed on same substrate The performance of its device and productivity.Propose in terms of technology controlling and process and power consumption additionally, work in the PNPN device punctured in mechanism Challenge.
Needing the DRAM memory cell less than conventional one capacitor of a transistor, it is easily on 20nm design rule Then following scaling, processes compatibility with the body silicon of standard, and consumes less static state and dynamic power.
Summary of the invention
The invention provides the volatile memory array of a kind of embodiment being suitable to dynamic random access memory, its Middle vertical PNP N thyristor is formed in body silicon substrate and by the shallow trench of the insulant on a direction with vertical The deeper groove of the insulant on direction and be isolated from each other.Memory cell array is arranged to cross point grid and by metal Conductor and bury heavily doped layer and interconnect.
In one embodiment, memory array includes line and alignment, and each thyristor has and is connected to The anode of one of line and the negative electrode being coupled to alignment.Substrate is preferably P conduction type, has the N extended in a first direction Conduction type buried layer, to provide the negative electrode being coupled to this alignment of alignment and thyristor.P alternately on buried layer leads Electricity type and N conductive type layer provide the base stage of thyristor, and top P conductive type layer provides the sun of thyristor Pole.Conductive layer at the second party upwardly extending anode that be coupled to thyristor orthogonal with first direction provides row Line.If desired, insulant is formed grid, to provide NMOS and PMOS transistor, is used for improving switching speed.
A kind of method of manufacturing array includes introducing N conductivity type dopant in P conductive type semiconductor substrate to carry For the step of buried layer, think that vertical thyristor forms alignment and negative electrode.Then formed outside P conduction type on buried layer Prolong layer.Then etching eliminates all of epitaxial layer and the buried layer part with exposure substrate, to form parallel deep trench, so Deep trench filled by the insulant of rear utilization such as silicon dioxide.Etching epitaxial layer is perpendicular to deep trench to be formed the most again Relatively shallow trench.After utilizing insulant to fill shallow trench, base stage and the doped anode to thyristor, and form the phase The electrical contacts hoped and adapter.
A kind of memory array that operates comprises the steps: with the method that selected thyristor is programmed for " conducting " Apply positive potential to the line being connected with selected thyristor, and apply relatively low to the alignment being connected with selected thyristor Electromotive force, wherein the difference between positive potential and relatively low potential is more than the electric potential difference needed for conducting thyristor.All unselected The electromotive force that line is applied in is not enough to change the state of other thyristor any.In order to turn off selected thyristor, to Line applies low potential, and applies the positive potential that be enough to be switched off to alignment.The electromotive force that all unselected lines are applied in is not Be enough to change the state of other thyristor any.
Apply positive potential to line and in the case of alignment applies relatively low potential, read selected thyristor.Just Difference between electromotive force and relatively low potential be enough to move more alignment in the case of selected thyristor is programmed to conducting High potential, but not enough so that alignment is moved to more by thyristor in the case of selected thyristor is programmed to turn off High potential.The electromotive force putting on unselected rowaand column lines is not enough to change its data.Electromotive force on line and alignment is maintained Be enough to make the thyristor of conducting continue conducting, but be not enough to the thyristor conducting that will turn off, this maintains in array The data of storage.
Additionally provide a kind of technology for reducing the electric current being accessed in the line carrying out operating.It is coupled to line Memory cell be divided into group, and be by only executing to one group every time for performing the alignment of operation on memory cell Add what electromotive force necessary to this operation was implemented.Other alignments all maintain relatively low potential.Then perform under operation, and selection One group.
A kind of method for refreshes memory array is made up of following operation: array is divided into sector, and passes through example As provided refresh line, so that by being only switchably connected to by those lines to be refreshed in sector, refresh line is next to be applied to sector Curtage pulse, thus it is refreshed by ground, sector one by one.
Because the thyristor meeting power consumption of conducting, it is possible to by using check bit more closely balance conducting and close The quantity of disconnected thyristor memory cell controls the power consumption in array.Such as, two check bit can be for storage Word defines four kinds of states, and they represent first four of the word not changing the word of storage, reversion storage, invert rear the four of the word stored All positions of the word of position and reversion storage.The method allows the word of storage averagely to have conducting and the pass of about the same quantity Disconnected thyristor.
Considering detailed description below and during accompanying drawing, other objects, features and advantages of the present invention will become to show and Being clear to, in all of the figs, similar reference numerals represents similar features.
Accompanying drawing explanation
Figure 1A is the circuit diagram of single thyristor memory cell.
Figure 1B is the equivalent circuit diagram used in these texts and pictures.
Fig. 2 A is the circuit diagram of 2 × 2 memory cell arrays.
Fig. 2 B is shown in integrated circuit the layout of the topological structure of 2 × 2 memory cell arrays implemented.
Fig. 3 A-9A is the sectional view of the process illustrating the memory cell for manufacturing Fig. 1, it is shown that along from Fig. 2 B's The cross section of line A～A'.
Fig. 3 B-9B is the sectional view of the process illustrating the memory cell for manufacturing Fig. 1, it is shown that along from Fig. 2 B's The cross section of line B～B'.
Figure 10 is the flow chart of the alternative Process of the process illustrating Fig. 3-9.
Figure 11 A and 11B puts on memory cell array when being and be shown in selected memory cell write " 0 " The diagram of electromotive force.
Figure 12 puts on the electromotive force of memory cell array when being and be shown in selected memory cell write " 1 " Diagram.
Figure 13 A and 13B is the electromotive force being shown in and putting on memory cell array when reading selected memory cell Diagram.
Figure 14 is to be shown as keeping the data of storage in memory cell to put on the electromotive force of memory cell array Diagram.
Figure 15 A-15B shows thyristor memory cell, has in the groove adjacent with thyristor NMOS side wall grid；The view in transverse section of Figure 15 A display unit, and the longitdinal cross-section diagram of Figure 15 B display unit.
Figure 16 is the circuit diagram of the cell array being shown with the grid shown in Figure 15 A-B.
Figure 17 A-17B shows thyristor memory cell, has in the groove adjacent with thyristor PMOS side wall grid；The view in transverse section of Figure 17 A display unit, and the longitdinal cross-section diagram of Figure 17 B display unit.
Figure 18 is the circuit diagram of the cell array being shown with the grid shown in Figure 17 A-B.
Figure 19 A-19B shows and rolls wordline access with the method reducing row electric current；Figure 19 A shows a step of the method Suddenly, wherein select first group for accessing, and Figure 19 B show next step, wherein select second group for accessing.
Figure 20 is to illustrate to refresh the circuit diagram of the method for the data of storage in memorizer method sector.
Figure 21 is the circuit diagram being shown with the method that dummy carrys out sensing memory unit.
Detailed description of the invention
1, individual memory cell
The invention provides a kind of memory cell based on thyristor, the method for manufacturing cell, and operate this The method planting cellular array.Memory cell is for dynamic random access memory (DRAM) integrated circuit and embedded in Time in the circuit of DRAM memory particularly useful.Figure 1A is coupling between anode access line (AL) and negative electrode access line (KL) The circuit diagram of thyristor.Thyristor is made up of two cross-linked bipolar transistors 10 and 12.PNP transistor 10 Emitter stage be coupled to anode access line, and the emitter stage of NPN transistor 12 is coupled to negative electrode access line.As indicated, two crystalline substances Colelctor electrode and the base stage of body pipe are coupled.Figure 1B is the equivalent circuit showing the thyristor 15 using ordinary symbol Figure.This symbol is used in following follow-up figure.
Fig. 2 A show be coupled into lattice with formed memory array four thyristors 15a, 15b, 15c and The array of 15d.Thyristor 15a and 15b is connected to same line AL 1, but is connected to different alignment KL 1 and KL 2. Similarly, thyristor 15c and 15d is connected to same line AL2, but is connected to different alignment KL1 and KL2.
Fig. 2 B is the layout of the layout illustrating the circuit being shown as integrated circuit in Fig. 2 A.Four thyristors are vertical Thyristor, has anode 20 in the corner of layout.Deep silicon dioxide groove 22 by the thyristor in left side and right side that Keep apart, and shallow trench 21 by top thyristor and lower section, those are kept apart.Show these grooves in more detail below. Conductor wire 24 provides a store for the line of device array, and is coupled to the anode of thyristor.Similar line (does not shows Go out) extend across the anode of thyristor in the row above line 24.This figure is additionally shown in following follow-up figure use Section A～the position of A' and B～B'.
2, manufacture process
Fig. 3 A and 3B is the diagram of the beginning of the process for describing the structure shown in the top view for manufacturing Fig. 2 B. In the first step of this process, the N conductivity type dopant of such as arsenic is utilized to be mixed by the selection area of P conduction type silicon substrate 30 Miscellaneous to from 1 × 1019To 5 × 1020The concentration of scope.Semiconductor substrate layer 30 can include single-crystal semiconductor material, such as silicon Or sige alloy.Introducing N conductivity type dopant 32 by known semiconductor fabrication (such as, ion implanting), it is such as Shown extends to reach in substrate 30 degree of depth of 200nm～500nm.Because this buried N type is adulterated by whole cell array region It is open, so there is no difference between the two width sectional views of Fig. 3 A and 3B.
It follows that as illustrated in figures 4 a and 4b, also use known semiconductor fabrication process technology at the top of rectangular structure Form thickness silicon epitaxial layers 35 between about 300nm and 500nm.Epitaxial layer 35 can be intrinsic, or doping in situ Become P conduction type.
Fig. 5 A and 5B shows the next step of this process.First, the upper surface across semiconductor structure grows or deposition Thin silicon dioxide (pad) layer 36.At the top of layer 36, known Technology is used to form silicon nitride layer 38.Use mask (not shown), etches opening to expose the upper surface of epitaxial layer 35, upper surface through silicon nitride layer 38 and pad oxide layer 36 Place's deep trench to be formed 39.In the case of removing or do not remove photoresist, use patterning pad is as hard mask, so Rear execution reactive ion etching (RIE) step, extends through the deep trench 39 of memory cell area, such as such as Fig. 2 B with etching Top view shown in.These deep trench extend downwardly into substrate 30 through the layer of top.Noting, deep trench is parallel to each other, and Thus do not appear in the cross section shown in Fig. 5 B.
As Fig. 6 A next shown in, fill deep trench 39 with the insulant of such as silicon dioxide 42.This is by first The silicon face of the sidewall of groove and the exposure of bottom grows what thin pad oxide realized.Then, such as, use highly dense Degree plasma (HDP) strengthens chemical gaseous phase deposition (CVD), with silicon dioxide by trench fill to suitable thickness, generally at knot The upper surface of structure extends above.Utilize the known chemically mechanical polishing (CMP) of high selectivity lapping liquid to surface it follows that use It is planarized, and removes the too much trench oxide reaching down to pad nitride.Then, as shown in Figure 6B, perform separately One masks and etch relatively shallow trench 40.It may be noted that the degree of depth of relatively shallow trench extends to N conductive type epitaxial layer 32, and Do not extend downward P type substrate.
It follows that as shown in Figure 7 B, by the way of same as above, make relatively shallow trench aoxidize, then use dioxy SiClx 45 fills groove.With silica-filled groove and after making trench planarization by CMP, reuse the wet of routine Method or dry etching etch away the upper strata of silicon dioxide and silicon nitride.
Fig. 8 A and 8B shows the subsequent step of process.Use ion implanting step by P conduction type 52 and N conduction type 54 impurity introduce in the upper surface of quasiconductor, create PNPN thyristor structure.N conductive type impurity is preferably arsenic, and P leads Electricity type dopant is preferably boron, such as boron difluoride.After forming region 52, such as the refractory metal such as titanium, cobalt or nickel is sunk Amass on upper surface.Then rapid thermal annealing (RTP) is performed to create conducting metal in such as region 50 semiconductor regions such as grade Silicide, to provide the Ohmic contact of the anode 50 with thyristor.Then unreacted metal is removed by wet etching. Buried N type region 32 provides negative electrode to connect.
Fig. 8 B also show the conductor wire 58 providing the line linked together by the anode of the thyristor of a line. Using known semiconductor fabrication to be formed can be these conductors of metal, metal silicide or DOPOS doped polycrystalline silicon.In order to For the sake of Jian Dan, show row line conductor the most in the fig. 8b, and row line conductor not shown in this paper subsequent drawings.
Fig. 9 A and 9B shows the alternative embodiment for anode construction 56.As shown, it is possible to use the source electrode of raising/ Drain technology, forms anode by selective epitaxial growth silicon on the upper surface of structure.Can in situ or use mask and Territory, p type island region 52 is doped by implantation step.According to previous embodiment, it is possible to use refractory metal and annealing steps form anode Electrode.The source/drain technology improved provides the advantage allowing relatively shallow trench, but remains able to realization and be respectively used to N and P The exceptional space in region 54 and 35.
Figure 10 is the flow chart illustrating the alternate embodiment for manufacturing vertical thyristor.Mentioned above for manufacturing One of the method for vertical thyristor may be disadvantageously, the p-type base stage that the injects and (region in Fig. 8, N-type base territory 52 and 54) it is likely to be due to higher-energy inject ion scattering and channel punchthrough and there is peak concentration and thickness limit.Figure 10 shows Go out and may more meet desired base implant distribution curve for realization, maintained the alternative Process of flat silicon surface simultaneously.
Process starts from step 60 buried layer N-type and injects about as described in Fig. 3.The most in a step 61, as Shown in Fig. 4, step up the epitaxial silicon of superficial growth expectation thickness (such as 80nm-130nm).The most in step 62, light is utilized Cause resist or the neighboring area of integrated circuit is sheltered by other material.The most in step 65, with suitable adulterant Implanting p-type base region (region 35 in Fig. 5).Then mask material (step 66) is removed from wafer, and then across wafer Another epitaxial layer of upper surface growth expectation thickness (such as 120nm-200nm), and this epitaxial layer is doped to N-type with shape Become N-type base territory.Finally, alternative Process returns to the formation of the trench isolation region as described in figure 5 above-8.
3, the operation of memory cell array
Figure 11 A shows a part for the bigger array of the memory cell using above-described thyristor.Should Figure will allow the memory array explaining operation arbitrary dimension to read, to write, to refresh and to operate storage battle array otherwise The method of row.Although showing 3 × 3 arrays, it should be noted that, the invention is not restricted to any certain amount of anode and negative electrode is deposited Line taking or memory cell.In this example memory array, individual memory cell 72 be each connected to anode line AL and Cathode line KL.Such as, memory cell 72kn is connected to anode line ALk and cathode line KLn.
In Figure 11 A and in follow-up each figure, in " selecting " memory cell of memory array operation is Heart unit 72jm.The purpose of operation described about Figure 11 A be to selected unit write one data (logical zero) and not Hinder the content of other memory cell.For illustrative purposes, show at other of array for each unit in the drawings The sample data of storage in unit.Such as, unit 72im is " conducting " of storage " 0 ", and unit 72kn " closing for storage " 1 " Disconnected ".
Each anode line and cathode line in Figure 11 show and put on this line to implement desired operation to unit The voltage of 72jm write logic state " 0 " (thyristor " turns on ").It should be noted that, voltage range described herein only goes out In the purpose illustrated, because the precise voltage used in particular implementation depends on the geometry designs of reality, and also depend on In the exact doping concentration for meeting target product specification.As long as additionally, the voltage difference between anode line and cathode line keeps Identical, it is possible to move up or down each voltage level.
In order to write " 0 ", unselected anode line ALi and ALk is maintained at the electromotive force of about 1.8-2.1 volt, and will choosing Fixed anode line ALj brings up to 2.4-3 volt.Unselected cathode line KL1 and KLn are maintained at 1.2-1.5 volt, and by selected Cathode line KLm pulls down to earth potential.The effect of these electromotive forces is the anode across selected thyristor 72jm and negative electrode applying The electromotive force of 2.4-3 volt, this electromotive force be enough to turn on thyristor 72jm, represents " 0 " state.Unselected AL and unselected All unit at KL have the electromotive force of about 0.6 volt between its anode and negative electrode, and it is designed to stand-by or keeps voltage, The data that those thyristors are stored are constant.The AL unselected for KL/ of the KL unselected for selected AL/ or selected The unit at place, sees the electromotive force of 1.2V-2.1V between its anode and negative electrode, and its upper limit is by the triggering of " 0 " state to one state Voltage determines.
One of write " 0 " biasing scheme of Figure 11 A may shortcoming be from " 0 " unit on selected ALj or KLm The leakage in the dark of (72im and 72jl), because the voltage difference between its anode and negative electrode is higher than stand-by voltage.In another enforcement In example, Figure 11 B shows write " 0 " operation of the replacement using semi-selection scheme.In this alternative method, all unselected AL and KL is biased at the half of selected anode voltage level.As a result, the list at unselected AL and unselected KL Unit is biased in 0 volt between its respective anode and negative electrode.
Figure 12 is the circuit diagram of the exemplary memory cell array using same-sign with Figure 11 A and 11B, to illustrate use In the electromotive force to selected memory cell 72jm write logical one.Show in order to write " 1 " on thyristor 72jm Each anode and cathode line on electromotive force.Unselected cathode line KL1 and KLn are maintained at earth potential, and by unselected Anode line is maintained at the electromotive force of 0.5-0.7 volt.In the first embodiment, selected cathode line is increased to 1.8-2.0 volt, selected Anode line be pulled to earth potential.Alternatively, for beneficially decoder and driver design, can be to the electromotive force at AL and KL Carry out level shift.For example, it is possible to the bias on selected ALj and unselected KL is brought up to 0.6V from 0V, and also will Bias on selected KLm and unselected AL increases 0.6V.
Figure 13 A is the circuit diagram of the memory cell array using same-sign with Figure 12, to illustrate for reading storage Electromotive force on the anode of the logic state of device unit and cathode line.In this case, unselected anode line ALi and ALk is protected Hold the electromotive force at 0.5-0.7 volt, and by all cathode line (selected and unselected the two) ground connection.Selected anode line is carried Up to 1.0-1.4 lies prostrate.
If selected thyristor 72jm is programmed to " conducting " in advance, i.e. " 0 " logic state, then its anode and The electromotive force applied between negative electrode is by this thyristor of conducting, and moves cathode line KLm to high potential.It is coupled to cathode line The raising of the known sensing amplifier detection electromotive force of KLm.Electromotive force increases and is interpreted to indicate thyristor to be in " 0 " logic State.On the other hand, if selected thyristor 72jm is programmed to " shutoff " in advance, i.e. " 1 " logic state, then its The electromotive force applied between anode and negative electrode will be not enough to switch it on.In this case, sensing amplifier will not detect the moon The electromotive force of polar curve KLm has any raising.Cathode line electromotive force is not changed in being interpreted to indicate thyristor to be in " 1 " logic shape State.Alternatively, it is also possible to from the logic state of the memory cell that anode line sensing is selected, because identical electric current flows into anode And flow out from negative electrode.
Figure 13 B shows for reading another embodiment of the logic state of storage in memory cell.In the method, Read permutation in one cycle.All unselected cathode line (KL) are biased in 0.5-0.7V or its stand-by level, and Selected anode line is precharged to the predetermined read voltage level of more than stand-by voltage.Exemplary range is 1～1.4V, and it drives The cell current that action spot is enough passes through the unit of storage " 0 " data.The sensing amplifier detection of the AL being coupled to select is patrolled for " 0 " Any electromotive force of the state of collecting declines.On the contrary, if the unit on selected anode line is programmed in advance to " shutoff ", then detect Logic state " 1 ".Accordingly, because the former of non-conducting unit declines hence without electromotive force.It is it desired to only read having in these row The unit of limit quantity, then unselected AL is biased in 0.5-0.7V, thus reduces leakage.
Individual thyristor in array will the most gradually lose the data of its storage due to leakage current.To the greatest extent Manage this leakage considerably less than the leakage occurred in conventional one capacitor DRAM memory cell of a transistor, but in order to gram Take leakage current, array can be placed in dormant state, thus keep the data of storage.Figure 14 shows and puts on anode and the moon Polar curve is to keep the electromotive force of the data of storage in thyristor memory cell array.In a state, all anode lines are protected Hold and lie prostrate at 0.5-0.7, and all cathode line all ground connection.Under this condition, " shutoff " thyristor is unaffected, and " leads Logical " thyristor by trickle charge to " conducting " state.Because this dormant state continuous consumption electric power, so make lock stream brilliant Body pipe remains stand-by and allows to exist between electric discharge periodic refresh array compromise.We preferred embodiment in, often Second by whole array refresh 1 to 10 times.This low present invention's of refreshing frequency required more than DRAM based on conventional FET Advantage especially.
Figure 15 A and 15B shows another embodiment of the thyristor memory cell of the present invention.In this embodiment In, increase sidewall NMOS gate 80 to the deep trench of structure.Remaining region of structure is identical with above for described in Fig. 4-8. The benefit increasing grid 80 is to increase writing speed and reduce write voltage.Because increasing grid to increase process complexity, institute The application-specific desired by memory array is depended on the use of grid.
Can be by being first carried out to be formed grid 80 in deep trench above for the deep silicon etch as described in Fig. 5.So The sidewall of rear oxidation groove, is consequently formed gate oxide, and gate electrode is kept apart by it with doped region 32,59 and 57.Then Such as utilize silicon dioxide that groove is partially filled with by chemical vapor deposition method.Then across described structure depositing conformal The polysilicon layer of doping.Anisotropic etch step eliminate the whole conformal polysilicon layer in addition to shown in Figure 15 A it After, perform another trench fill and operate to complete trench fill.Chemically mechanical polishing or other technology is the most such as used Perform suitable planarization steps.The most in this process, make and electrically connect so that grid 80 is coupled, thus control gate polar curve (GL)。
Figure 16 is the circuit diagram of the array of the thyristor memory cell 72 showing and adding grid 80 as mentioned above. Grid 80 is short circuit NPN transistor 82 when being turned on by gate lines G L, and the base stage of PNP transistor 83 is connected to cathode line KL.Should Mode has above-mentioned advantage and reduces write voltage and allow to write quickly data.
Figure 17 shows another of vertical brake stream transistor unit in deep trench with two sidewall PMOS grids 86 Embodiment.These unit are formed by the way of the same with above-described grid 80.Buried gate 86 can be connected to pickup At region and be coupled to gate line (GL).By with above-described the same in the way of form these grids.At deep silicon trench etch After step, form trench-gate oxide.Then with silicon dioxide, trench portions is filled into higher than N-negative electrode/P-base junction The degree of depth.Then the conformal conductive grid layer of such as DOPOS doped polycrystalline silicon is formed.Then grid layer is carried out anisotropic etching with Form the side wall grid that N-type base stage is completely covered.Finally, utilize silica-filled groove, then use known technology pair Groove is planarized.
Figure 18 is the circuit diagram of the memory array of the PMOS grid 86 using Figure 17.Grid 86 is being turned on by gate lines G L Time short circuit PNP transistor 83, the base stage of NPN transistor 82 is connected to anode line AL.The method with above with respect to NMOS gate Described has identical advantage.
Thyristor array is used to be potentially prone to during accessing operation need relatively as of memory cell High row electric current reads memory cell.(used here as " OK " word as the synonym of anode, use " arranging " as negative electrode Synonym.Wordline and bit line can also be used.) in order to reduce the demand to higher row electric current, use us to be referred to as rolling The technology of wordline.In conjunction with Figure 19, the method is described.
Figure 19 A shows the row of the thyristor memory cell in memory array.This row is by being divided into M group unit N row memory cell constitute.Left end at this row shows one group of 4 unit.Being one group uses 4 unit only to show Example；In actual integrated circuit, one group will exceed well over 4 unit.For access unit, such as, in order to read from them Data or to they write data, to all members of this group alignment apply voltage VSelected.Other alignments all receive electricity Gesture VHold, wherein VHold is higher than VSelected.As a result, selected group will have an electric current:
I group selected=M*I Selected, wherein I Selected is the electric current for a unit.
In this row, remaining N/M-1 group unit will have an electric current:
I group hold=(N/M-l) * M*I hold, wherein I Hold is the electric current for a unit.
When using memory array, flow process is to apply the selected electromotive force for desired operation, simultaneously by institute to first group Remaining group is had to be biased into " hold ".Once complete the desired operation to first group, just the bias on first group is become " hold ", and the bias in next group is become selected electromotive force, such as shown in Figure 19 B.By repeating removing in wordline The unit of all groups outside selected group is maintained at these steps this operation of group ground repetition one by one of " hold " electromotive force, reduces Row electric current.Our this technology is called " rolling " wordline.
The memory cell of electric current and voltage relationship for having nonlinearity, permissible for the holding electric current of unit The several orders of magnitude lower than the reading electric current of selected unit.For example, it is assumed that a line has 128 row being divided into 8 groups, often group has 16 Individual unit.In typical embodiment, selected electric current would be about 10 μ A, and keeps electric current to would be about 10pA, differs six The individual order of magnitude.Therefore:
In the case of not rolling: I row=128*l0uA=1.28mA
In the case of rolling: I row=16*l0uA+ (128-16) * 10p Α=160uA
Thus, by the way roll wordline provide word line current 88% reduction, and 8 times roll access with Access complete row.
Because each thyristor unit " turned on " in memory array will consume some electric currents, so memory array The current drain of row and the quantity of this " conducting " unit depend on the particular data being just stored in array.This have by Power consumption is associated with in memorizer the undesired effect of the real data of storage.Can use target is by the unit of about 50% Remain the data encoding of logical one to reduce this standby current.
For example, it is contemplated that have 8 words of 2 extra parity.
Check bit=00 is unchanged
Check bit=01 reversion is low 4
Check bit=10 reversion is high 4
Check bit=11 invert all positions
In the following example, check bit is the front two before the word stored of data and is italic.
Example 1: all is all one: 1111-1111 to become 10-0000-1111, thus 8 one become 5 one.
Example 2:50%+1 one: 1010_1011 becomes 01_1010_0100, thus 5 one become 4 one.
Example 3:50% is one: 1010_1010 to become 00_1010_1010, thus 4 one become 4 one.
Example 4:50%-1 one: 0010_1010 becomes 00_0100_1010, thus 3 one become 3 one.
Example 5: all is all zero: 0000_0000 to become 10_1111_0000, thus 0 one becomes 5 one.
Example 6:5 one: 0011_1011 becomes 11_1100_0100, thus 5 one become 3 one.
Array standby current to be maintained relative constancy level by data above coding techniques or other similar approach In the case of be useful, and for current source control dormant operation.Conventional logic circuits may be used for detecting the quantity of 1 and position Put, perform desired reversion (or not performing) and increase check bit to the data of storage.
In the embodiment being associated with Figure 14, keep voltage or electric current by thyristor memory array by supply The data of middle storage maintain stand-by, from without refreshing.Under these condition of readiness, keep all storages of " 0 " data The electric current that device cell conducts is the lowest but limited.Owing to keeping electric current and keeping the exponential relationship between voltage, it is advantageous that make Treating that the used time makes unit holding activity with current source.In our patent application earlier, such as, submit on January 6th, 2015 The U.S. of entitled " Cross-Coupled Thyristor SRAM Circuits and Methods of Operation " is special Profit application 14/590834 describes a kind of method, by quoting, this patent application is expressly incorporated herein.There we describes and makes With constant-current source by array bias voltage to the optimum technology keeping voltage that data keep maintaining low standby current.Although in conjunction with SRAM memory discusses this method, but it can be used for other volatile memory based on thyristor, such as Described herein those.
In above-mentioned biasing scheme, keep the electric current that all memory cells conduction of " 0 " data is the lowest but limited, with Just maintain array data and without refresh.Alternative method is that the electric current of offer is adjusted to lower value, and this value is not enough to indefinite duration Ground maintains data integrity, but be enough to maintain data integrity in minimum " holding " cycle (such as 1ms).The method allows to treat With being substantially reduced of electric current.But, in order to maintain the integrity of data indefinitely, ground, sector performs background refreshing behaviour one by one Make, the most at short notice the holding electric current for sector settings is increased to high value, to be re-established more by unit level Good value, but then decrease back to normal standby current.This allows all unit in simultaneously refreshed sector rather than as current Conventional DRAM is utilized to refresh line by line as being done.Additionally, refresh without interference with normal read/write operations so that refresh behaviour Make in outside invisible.Figure 20 illustrates the method.
The figure shows how a refresh pulse can refresh whole sector.It is applied to line when cmos switch 92 turns on The refresh pulse of 90 is by the sector of refreshing memory cells 72.This example illustrate stand-by/refreshing that electric current controls, but, can Same Way to be applied to voltage-controlled stand-by/refreshing.
Figure 21 is the circuit diagram illustrating a kind of technology for reading data from thyristor array.Sensing amplifier 95 There is an input of the string memory cell 72 being connected to memory array.Another input of sensing amplifier 95 is connected to The illusory memory cell of string 94.Memory cell 72 and dummy cell 94 have the alignment being precharged to 0 volt.Reading behaviour During work, if unit is " 0 ", the electromotive force making alignment is moved up by the state of the memory cell 72 of programming, if or Unit is " 1 ", the electromotive force of alignment will be made close to 0V.The alignment of illusory memory cell by current source with the row in selected array is Sensing amplifier 95 produces the speed of the 1/2 of the speed of differential data and moves up.If selected unit is " 0 ", then select Row will increase to more than dummy column.If selected unit is " 1 ", then dummy column will increase to more than select column.Then may be used Sensing amplifier output to be construed to " 1 " or " 0 " of the data that instruction is stored.
This description of invention has been given for purpose of illustration and description.It is not intended to carry out exhaustive or by this Bright it is limited to described precise forms, and according to teachings above, many modifications and variations are all possible.Select and describe Embodiment is to explain the principle of invention and actual application thereof best.This description will make those skilled in the art can Utilize best and invention in practicing various embodiments and be suitable to the various amendments of special-purpose.The scope of the present invention is by following Claim limits.

Claims (10)

1. the method operating volatile memory display, described volatile memory array has anode line, cathode line and hangs down The array of straight thyristor, described vertical thyristor has and is coupled to the anode of described anode line and having and is coupled to The negative electrode of described cathode line, described method is for keeping the data of storage, described method bag in all of described thyristor Include:
The first electromotive force is applied to all anode lines；
The second electromotive force is applied to all cathode line；Wherein
Difference between described first electromotive force and described second electromotive force be enough to make the thyristor of conducting to continue to turn on.
Method the most according to claim 1, wherein:
Described first electromotive force is about 0.5-0.7 volt；And
Described second electromotive force is about 0.0 volt.
3., in the crosspoint array of memory cell, each memory cell only has a thyristor, described lock stream Transistor is connected between wordline and bit line, a kind of method of data maintained in described array, and described method includes:
The sector of the memory cell in described array is for induced current, and described electric current has the first amplitude, described first value It is not enough to maintain indefinitely the data of the described sector in described memory cell；
The described electric current of the described sector of memory cell is brought up to the second amplitude, with in data from described memory cell The data in the described sector of described memory cell are refreshed in described sector before losing；And
Described electric current is reduced to described first amplitude；
Repeat improve current step and reduce current step；
Thus, while described data are maintained in described array indefinitely, it is fed to the described electric current of described sector Reduce over time.
Method the most according to claim 3, also includes:
In the case of the described electric current supplying the first amplitude to described sector, before determining that described memory cell loses data Minimum time section；And
In described raising current step, determined by described electric current was brought up in the time period described second amplitude.
Method the most according to claim 3, wherein, the array of described memory cell includes multiple sector, and also bag Include and electric current is supplied step, electric current improves step, electric current reduces step and repeats all fans that step is applied in described array District.
Method the most according to claim 5, wherein, is applied to described battle array according to particular sequence by described electric current raising step Each sector of the memory cell in row, to avoid improving the electric current more than in a sector simultaneously.
Method the most according to claim 5, also includes:
In the case of the electric current supplied is the first amplitude, determine described memory cell in any sector lose data it Front minimum time section；And
In described raising current step, determined by for each sector, described electric current brought up to described in the time period Two amplitudes.
Method the most according to claim 7, wherein, is applied to described battle array according to particular sequence by described electric current raising step Each sector of the memory cell in row, to avoid improving the electric current more than in a sector simultaneously.
9. there is anode line, cathode line and be divided into the volatibility of array of vertical brake stream transistor memory cell of sector In memory array, described thyristor memory cell has the anode being coupled to anode line and the moon being coupled to cathode line Pole, a kind of method refreshing the data in the sector being stored in described memory array includes:
All of described anode line in selected sector is coupled to refresh line；And
Current impulse is applied to described refresh line.
Method the most according to claim 9, wherein, described refresh line is switchably coupled to multiple fans of described array Described anode line in district, and described method is further comprising the steps of: before applying described current impulse, will be except described choosing Determine all of the plurality of sector outside sector to disconnect with described refresh line.
CN201580010678.0A 2014-09-25 2015-09-25 Methods of retaining and refreshing data in a thyristor random access memory Pending CN106030718A (en)

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US14/590,834 US9449669B2 (en) 2014-09-25 2015-01-06 Cross-coupled thyristor SRAM circuits and methods of operation
US201562186336P 2015-06-29 2015-06-29
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