CN106030715A - Thyristor volatile random access memory and manufacturing method - Google Patents

Abstract

A volatile memory array using vertical thyristors is disclosed together with methods of fabricating the array.

Description

Thyristor volatile random access memory and manufacturing method

Cross References to Related Applications

This patent application is related to U.S. Patent Application No.14/841521 entitled "Methods of Reading and Writing Data in a Thyristor Random Access Memory" filed on the same date, and to "Methods of Retaining and Refreshing Data in a Thyristor Random Access Memory" filed on the same date. Access Memory,” U.S. Patent Application No. 14/841,578, and U.S. Patent Application No. 14/841,615, entitled “Power Reduction in Thyristor Random Access,” filed on the same date; Priority to U.S. Provisional Patent Application No. 62/186336, entitled "High-Density Volatile RAMs, Method of Operation and Manufacture Thereof," and filed on January 6, 2015, and entitled "Cross-Coupled Thyristor SRAM Circuits and Methods continuation-in-part of U.S. Application No. 14/590834, which claims priority to U.S. Provisional Patent Application No. 62/055582, filed September 25, 2014; incorporated by reference for all Application is incorporated herein.

Background technique

The present invention relates to integrated circuit devices, and in particular, to volatile random access memory, commonly referred to as dynamic random access memory (DRAM).

DRAM is a type of random access memory integrated circuit that, in the most common commercial implementation, stores each bit of data in separate capacitors coupled to transistors within the integrated circuit. Capacitors can be charged or discharged. The state of charging or discharging is interpreted as the value of the bits, namely "0" and "1". Over the past 30 years, the one-transistor-one-capacitor cell has been the most commercially available memory cell used in DRAM devices. Lithographic scaling and increased process complexity have enabled a quadrupling of the number of bits of memory in DRAM approximately every three years, however, individual memory cells are now very small, maintaining the capacitance of each cell and reducing charge leakage are barriers The main problem with further size reduction.

In response to these challenges and other issues, alternative DRAM memory cell architectures have been proposed. One such approach is known as floating body DRAM (FBDRAM). FBDRAM is a single MOSFET built on silicon-on-insulator (SOI) (Okhonin, Int. SOI Conf., 2001) or in a triple well with buried N implants (Ranica, VLSI Technology, 2004). The body of the transistor forms a capacitor against an insulating substrate. The technology hasn't solved its data retention issues, especially at reduced sizes.

Another approach to new DRAM architectures is based on the negative differential resistance behavior of PNPN thyristors. In these designs, active or passive gates are used. For example, the thin capacitively coupled thyristor described in US Patent 6,462,359 uses a lateral PNPN thyristor on an SOI substrate with a coupled gate for increased switching speed. Unfortunately, the lateral appearance of this design, together with its gate requirements, results in a memory cell that is significantly larger than conventional one-transistor-one-capacitor DRAM cell structures.

Liang in US Patent 9013918 describes a PNPN thyristor cell constructed on top of a silicon substrate and operating in both forward and reverse breakdown regions to write data into the cell. Unfortunately, the use of epitaxial or CVD semiconductor layers at the back end of standard CMOS processes adds thermal cycling and etching steps, which can degrade the performance and yield of other devices formed earlier on the same substrate. Furthermore, PNPN devices operating in the breakdown regime pose challenges in terms of process control and power consumption.

There is a need for DRAM memory cells that are smaller than conventional one transistor one capacitor, scale easily below 20nm design rules, are compatible with standard bulk silicon processing, and consume less static and dynamic power.

Contents of the invention

The present invention provides a volatile memory array suitable for a dynamic random access memory embodiment in which vertical PNPN thyristors are formed in a bulk silicon substrate through shallow trenches of insulating material in one direction and vertical are isolated from each other by deeper trenches of insulating material in the direction. An array of memory cells is arranged in a cross-point grid and interconnected by metal conductors and buried heavily doped layers.

In one embodiment, the memory array includes row lines and column lines, and each thyristor has an anode connected to one of the row lines and a cathode coupled to the column line. The substrate is preferably of P conductivity type with a buried layer of N conductivity type extending in a first direction to provide a column line and a cathode of the thyristor coupled to the column line. Alternating layers of P conductivity type and N conductivity type on the buried layer provide the base of the thyristor, and the upper layer of P conductivity type provides the anode of the thyristor. A conductive layer coupled to the anodes of the thyristors extending in a second direction orthogonal to the first direction provides a row line. If desired, gates are formed in insulating material to provide NMOS and PMOS transistors for improved switching speed.

A method of fabricating an array includes the step of introducing N-conductive type dopants into a P-conductive type semiconductor substrate to provide a buried layer to form column lines and cathodes for vertical thyristors. Then a P conductivity type epitaxial layer is formed on the buried layer. All epitaxial and buried layers are then etched away to expose portions of the substrate to form parallel deep trenches, which are then filled with an insulating material such as silicon dioxide. The epitaxial layer is then etched again to form shallower trenches perpendicular to the deep trenches. After filling the shallow trenches with an insulating material, the base and anode of the thyristor are doped and the desired electrical contacts and connectors are formed.

A method of operating a memory array to program selected thyristors "on" includes the steps of applying a positive potential to a row line connected to the selected thyristor and applying a positive potential to a row line connected to the selected thyristor. A lower potential is applied to the column lines, where the difference between the positive potential and the lower potential is greater than the potential difference required to turn on the thyristor. All unselected lines are applied with insufficient potential to change the state of any other thyristors. To turn off selected thyristors, a low potential is applied to the row wires and a positive potential is applied to the column wires sufficient to turn them off. All unselected lines are applied with insufficient potential to change the state of any other thyristors.

Selected thyristors are read with a positive potential applied to the row lines and a lower potential applied to the column lines. The difference between the positive potential and the lower potential is sufficient to pull the column line to the higher potential if the selected thyristor is programmed to be on, but is not sufficient if the selected thyristor is programmed to be off low enough for the thyristor to pull the column line to a higher potential. The potential applied to unselected row and column lines is insufficient to change their data. Maintaining the potential on the row and column lines is sufficient to keep the on thyristors on, but not high enough to turn on the off thyristors, which preserves the data stored in the array.

A technique for reducing current in a row line to be accessed for operation is also provided. Memory cells coupled to row lines are divided into groups, and column lines for performing operations on the memory cells are implemented by applying a potential necessary for the operation to only one group at a time. All other column lines are maintained at lower potentials. Then execute the action and select the next group.

A method for refreshing a memory array consists of dividing the array into sectors and providing refresh lines to the sectors by, for example, providing refresh lines by switchably connecting only those row lines in the sectors to the refresh lines. A current or voltage pulse is applied to a sector to refresh it sector by sector.

Because turned-on thyristors consume power, power consumption in the array can be controlled by using parity bits to more closely balance the number of turned-on and turned-off thyristor memory cells. For example, two parity bits can define four states for a stored word, which represent unchanged stored word, inverted first four bits of stored word, inverted last four bits of stored word, and inverted stored word. all bits of the word. This approach allows stored words to have on average about the same number of on and off thyristors.

Other objects, features and advantages of the present invention will become apparent upon consideration of the following detailed description and accompanying drawings, throughout which like reference numerals indicate like features.

Description of drawings

Figure 1A is a circuit diagram of a single thyristor memory cell.

Figure 1B is the equivalent circuit diagram used in this figure.

2A is a circuit diagram of a 2x2 memory cell array.

2B is a layout diagram showing the topology of a 2x2 array of memory cells implemented in an integrated circuit.

3A-9A are cross-sectional views illustrating a process for fabricating the memory cell of FIG. 1, showing a cross-section along line A-A' from FIG. 2B.

3B-9B are cross-sectional views illustrating a process for fabricating the memory cell of FIG. 1, showing a cross-section along line BB' from FIG. 2B.

10 is a flowchart illustrating an alternative process to the process of FIGS. 3-9.

11A and 11B are diagrams showing potentials applied to a memory cell array when "0" is written into a selected memory cell.

FIG. 12 is a diagram showing potentials applied to a memory cell array when "1" is written into a selected memory cell.

13A and 13B are diagrams showing potentials applied to a memory cell array when a selected memory cell is read.

FIG. 14 is a diagram showing potentials applied to a memory cell array to hold data stored in the memory cells.

15A-15B illustrate a thyristor memory cell with an NMOS sidewall gate in the trench adjacent to the thyristor; FIG. 15A shows a lateral cross-sectional view of the cell, and FIG. 15B shows a longitudinal cross-sectional view of the cell.

FIG. 16 is a circuit diagram showing a cell array using the gates shown in FIGS. 15A-B .

17A-17B show a thyristor memory cell with a PMOS sidewall gate in the trench adjacent to the thyristor; FIG. 17A shows a lateral cross-sectional view of the cell, and FIG. 17B shows a longitudinal cross-sectional view of the cell.

Fig. 18 is a circuit diagram showing a cell array using the gates shown in Figs. 17A-B.

Figures 19A-19B show a method of rolling word line access to reduce row current; Figure 19A shows one step of the method, where the first group is selected for access, and Figure 19B shows the next step, where the second group is selected Groups are used for access.

FIG. 20 is a circuit diagram illustrating a method of refreshing data stored in a memory sector.

FIG. 21 is a circuit diagram illustrating a method of sensing a memory cell using a dummy bit line.

detailed description

1. Individual memory unit

The present invention provides a thyristor-based memory cell, a method of fabricating the cell, and a method of operating an array of such cells. Memory cells are particularly useful when used in dynamic random access memory (DRAM) integrated circuits and circuits in which DRAM memory is embedded. FIG. 1A is a circuit diagram of a thyristor coupled between an anode access line (AL) and a cathode access line (KL). The thyristor consists of two cross-coupled bipolar transistors 10 and 12 . The emitter of PNP transistor 10 is coupled to the anode access line, while the emitter of NPN transistor 12 is coupled to the cathode access line. As shown, the collectors and bases of the two transistors are coupled together. FIG. 1B is an equivalent circuit diagram showing a thyristor 15 using conventional symbols. This symbol is used in subsequent figures below.

Figure 2A shows an array of four thyristors 15a, 15b, 15c and 15d coupled in a grid pattern to form a memory array. Thyristors 15a and 15b are connected to the same row line AL1, but to different column lines KL1 and KL2. Similarly, thyristors 15c and 15d are connected to the same row line AL2, but to different column lines KL1 and KL2.

FIG. 2B is a layout diagram showing the layout of the circuit shown as an integrated circuit in FIG. 2A. The four thyristors are vertical thyristors with anodes 20 at the corners of the layout. Deep silicon dioxide trenches 22 isolate the thyristors on the left from those on the right, while shallow trenches 21 isolate the thyristors above from those below. These grooves are shown in more detail below. Conductive lines 24 provide the row lines for the memory array and are coupled to the anodes of the thyristors. Similar row lines (not shown) extend across the anodes of the thyristors in the row above row line 24 . This figure also shows the location of sections A-A' and BB' used in subsequent figures below.

2. Manufacturing process

3A and 3B are diagrams used to describe the beginning of a process for fabricating the structure shown in the top view of FIG. 2B. In the first step of the process, selected regions of the P conductivity type silicon substrate 30 are doped with an N conductivity type dopant such as arsenic to a concentration ranging from 1×10 ¹⁹ to 5×10 ²⁰ . The semiconductor substrate layer 30 may include a single crystal semiconductor material, such as silicon or a silicon-germanium alloy. N conductivity type dopants 32 are introduced by known semiconductor fabrication techniques (eg, ion implantation), extending into substrate 30 as shown to a depth of 200nm-500nm. Since the entire cell array area is open to the buried N-type doping, there is no difference between the two cross-sectional views of Figures 3A and 3B.

Next, as shown in FIGS. 4A and 4B , an epitaxial silicon layer 35 with a thickness between approximately 300 nm and 500 nm is also formed on top of the underlying structure using known semiconductor fabrication process techniques. The epitaxial layer 35 may be intrinsic, or in-situ doped to a P conductivity type.

Figures 5A and 5B illustrate the next step in the process. First, a thin silicon dioxide (pad) layer 36 is grown or deposited across the upper surface of the semiconductor structure. On top of layer 36, silicon nitride layer 38 is formed using known process techniques. Using a mask (not shown), openings are etched through silicon nitride layer 38 and pad oxide layer 36 to expose the upper surface of epitaxial layer 35 where deep trenches 39 are to be formed. Using the patterned pad as a hard mask with or without removing the photoresist, a reactive ion etching (RIE) step is then performed to etch a deep trench 39 extending through the memory cell area, for example as shown in FIG. 2B shown in the top view. These deep trenches extend down to the substrate 30 through the layers above. Note that the deep trenches are parallel to each other, and thus do not appear in the cross-section shown in FIG. 5B.

As next shown in FIG. 6A , deep trenches 39 are filled with an insulating material such as silicon dioxide 42 . This is achieved by first growing a thin liner oxide on the exposed silicon surfaces on the sidewalls and bottom of the trench. The trenches are then filled to an appropriate thickness with silicon dioxide, for example, using high density plasma (HDP) enhanced chemical vapor deposition (CVD), typically extending over the upper surface of the structure. Next, the surface is planarized and excess trench oxide down to the pad nitride is removed using well-known chemical mechanical polishing (CMP) using a highly selective slurry. Then, as shown in FIG. 6B , another masking step is performed and the shallower trench 40 is etched. It should be noted that the depth of the shallower trench extends to the N conductivity type epitaxial layer 32 and does not extend down to the P type substrate.

Next, as shown in FIG. 7B , the shallower trenches are oxidized and then filled with silicon dioxide 45 in the same manner as described above. After the trenches are filled with silicon dioxide and planarized by CMP, the upper layers of silicon dioxide and silicon nitride are etched away again using conventional wet or dry etching.

Figures 8A and 8B illustrate the next steps in the process. P conductivity type 52 and N conductivity type 54 impurities are introduced into the upper surface of the semiconductor using an ion implantation step, creating a PNPN thyristor structure. The N conductive type impurity is preferably arsenic, and the P conductive type impurity is preferably boron, such as boron difluoride. After forming region 52, a refractory metal such as titanium, cobalt or nickel is deposited onto the upper surface. A rapid thermal anneal (RTP) is then performed to create a conductive metal suicide in the semiconductor region, such as region 50, to provide an ohmic contact to the anode 50 of the thyristor. Unreacted metal is then removed by wet etching. Buried N-type region 32 provides the cathode connection.

Also shown in Figure 8B is a conductive line 58 that provides a row line connecting the anodes of the thyristors of a row together. These conductors, which may be metal, metal suicide, or doped polysilicon, are formed using well-known semiconductor fabrication techniques. For simplicity, only the row line conductors are shown in FIG. 8B and are not shown in subsequent figures herein.

An alternative embodiment for the anode structure 56 is shown in FIGS. 9A and 9B . As shown, the anode can be formed by selectively epitaxially growing silicon on the upper surface of the structure using enhanced source/drain technology. P-type region 52 can be doped in situ or using a masking and implantation step. According to the foregoing embodiments, the anode electrode may be formed using a refractory metal and an annealing step. The improved source/drain technology offers the advantage of allowing shallower trenches, yet still enables extra space for the N and P regions 54 and 35 respectively.

Figure 10 is a flow diagram illustrating an alternate embodiment for fabricating a vertical thyristor. One possible disadvantage of the method described above for fabricating vertical thyristors is that the implanted P-type base and N-type base regions (regions 52 and 54 in FIG. The channel punches through with peak concentration and thickness limits. Figure 10 shows an alternative process for achieving a base doping profile that may be more desirable while maintaining a planar silicon surface.

The process begins at step 60 - buried layer N-type implant - as described with respect to FIG. 3 . Then in step 61 , as shown in FIG. 4 , epitaxial silicon is grown across the upper surface to a desired thickness (eg, 80nm-130nm). Next in step 62, the peripheral area of the integrated circuit is masked with photoresist or other material. Then in step 65, the P-type base region (region 35 in FIG. 5) is implanted with suitable dopants. The mask material is then removed from the wafer (step 66), and another epitaxial layer of desired thickness (eg, 120nm-200nm) is then grown across the upper surface of the wafer and doped N-type to form an N-type base area. Finally, the alternate process returns to the formation of trench isolation regions as described above in FIGS. 5-8.

3. Operation of the memory cell array

Figure 1 IA shows a portion of a larger array of memory cells using the thyristors described above. This figure will allow to explain the method of operating a memory array of arbitrary size to read, write, refresh and otherwise manipulate the memory array. Although a 3x3 array is shown, it should be noted that the invention is not limited to any particular number of anode and cathode access lines or memory cells. In this exemplary memory array, individual memory cells 72 are each connected to an anode line AL and a cathode line KL. For example, memory cell 72kn is connected to anode line ALk and cathode line KLn.

In FIG. 11A, and in subsequent figures, the "selected" memory cell for memory array operation is center cell 72jm. The purpose of the operation described with respect to FIG. 11A is to write one bit of data (logic "0") to a selected cell without interfering with the contents of other memory cells. For illustrative purposes, sample data stored in other cells of the array is shown for each cell in the figure. For example, cell 72im is "on" storing a "0" and cell 72kn is "off" storing a "1".

Each of the anode and cathode lines in Figure 11 shows the voltage applied to that line to effect the desired operation - write logic state "0" (thyristor "on") to cell 72jm. It should be noted that the voltage ranges described here are for illustrative purposes only, as the exact voltages used in a particular implementation depend on the actual geometric design and also on the exact doping concentration used to meet the target product specification. Also, each voltage level can be shifted up or down as long as the voltage difference between the anode and cathode wires remains the same.

To write "0", the unselected anode lines ALi and ALk are held at a potential of approximately 1.8-2.1 volts, while the selected anode line ALj is raised to 2.4-3 volts. The unselected cathode lines KL1 and KLn are held at 1.2-1.5 volts, while the selected cathode line KLm is pulled down to ground potential. The effect of these potentials is to apply a potential of 2.4-3 volts across the anode and cathode of the selected thyristor 72jm, which is sufficient to turn on the thyristor 72jm, representing the "0" state. All cells at unselected AL and unselected KL have a potential of about 0.6 volts between their anode and cathode, which is designed as a standby or hold voltage so that the data stored by those thyristors does not change. For a cell at selected AL/unselected KL or selected KL/unselected AL, a potential of 1.2V-2.1V is seen between its anode and cathode, the upper limit of which is determined by the "0" state The trigger voltage to the "1" state is determined.

One possible disadvantage of the write "0" biasing scheme of Fig. 11A is the dark leakage from the "0" cell (72im and 72jl) on the selected ALj or KLm due to the high voltage difference between its anode and cathode at the standby voltage. In yet another embodiment, FIG. 11B shows an alternative write "0" operation using a half selection scheme. In this alternative, all unselected ALs and KLs are biased at half the selected anode voltage level. As a result, cells at unselected AL and unselected KL are biased at 0 volts between their respective anodes and cathodes.

FIG. 12 is a circuit diagram of an exemplary memory cell array using the same symbols as FIGS. 11A and 11B to illustrate the potentials used to write a logic "1" to a selected memory cell 72jm. The potentials on the respective anode and cathode lines to write a "1" on thyristor 72jm are shown. The unselected cathodic lines KL1 and KLn are kept at ground potential, while the unselected anode lines are kept at a potential of 0.5-0.7 volts. In a first embodiment, the selected cathodic wire is raised to 1.8-2.0 volts and the selected anode wire is pulled to ground potential. Alternatively, to facilitate decoder and driver design, the potentials at AL and KL can be level shifted. For example, the bias voltage on selected ALj and unselected KL can be increased from 0V to 0.6V, and the bias voltage on selected KLm and unselected AL can also be increased by 0.6V.

13A is a circuit diagram of a memory cell array using the same notation as in FIG. 12 to illustrate the potentials on the anode and cathode lines used to read the logic state of the memory cells. In this case, the unselected anode lines ALi and ALk are kept at a potential of 0.5-0.7 volts, while all cathode lines (both selected and unselected) are grounded. Selected anode lines are boosted to 1.0-1.4 volts.

If the selected thyristor 72jm was previously programmed to be "on", i.e. "0" logic state, then an applied potential between its anode and cathode will turn on the thyristor and pull the cathode line KLm to a relatively low voltage. high potential. A known sense amplifier coupled to the cathode line KLm detects the increase in potential. The increase in potential is interpreted as indicating that the thyristor is in a "0" logic state. On the other hand, if the selected thyristor 72jm was previously programmed to be "off", ie, a "1" logic state, then the potential applied across its anode and cathode will not be sufficient to turn it on. In this case, the sense amplifier will not detect any increase in the potential of the cathode line KLm. A lack of change in the potential of the cathode line is interpreted as indicating that the thyristor is in a "1" logic state. Alternatively, the logic state of selected memory cells can also be sensed from the anode line, since the same current flows into the anode and out of the cathode.

Figure 13B illustrates another embodiment for reading logic states stored in memory cells. In this method, the entire column is read in one cycle. All unselected cathodic lines (KL) are biased at 0.5-0.7V or their inactive level, and selected anode lines are precharged to a predetermined read voltage level above the inactive voltage. An exemplary range is 1-1.4V, which drives enough cell current through a cell storing "0" data. A sense amplifier coupled to the selected AL detects any potential drop for a "0" logic state. Conversely, a logic state of "1" is detected if the cells on the selected anode line were previously programmed to be "OFF". Therefore, there is no potential drop due to the non-conducting elements. If it is desired to read only a limited number of cells in the column, the unselected ALs are biased at 0.5-0.7V, thereby reducing leakage.

Individual thyristors in the array will gradually lose their stored data over time due to leakage currents. Although this leakage is significantly less than what occurs in conventional one-transistor-one-capacitor DRAM memory cells, to overcome the leakage current, the array can be placed in an inactive state, thereby retaining the stored data. Figure 14 shows the potentials applied to the anode and cathode lines to maintain data stored in an array of thyristor memory cells. In this state, all anode wires are held at 0.5-0.7 volts and all cathode wires are grounded. Under this condition, the "off" thyristor is unaffected, while the "on" thyristor is continuously charged to the "on" state. Because this inactive state continuously consumes power, there is a tradeoff between keeping the thyristors inactive and allowing them to discharge and periodically refresh the array. In our preferred implementation, the entire array is refreshed 1 to 10 times per second. This is much lower than the refresh frequency required by conventional FET based DRAMs - a particular advantage of the present invention.

15A and 15B illustrate another embodiment of a thyristor memory cell of the present invention. In this embodiment, sidewall NMOS gates 80 are added to the deep trenches of the structure. The remaining areas of the structure are the same as described above with respect to Figures 4-8. The benefit of adding gate 80 is to increase write speed and reduce write voltage. Because adding gates increases process complexity, the use of gates depends on the particular application for which the memory array is intended.

Gate 80 may be formed in the deep trench by first performing a deep silicon etch as described above with respect to FIG. 5 . The sidewalls of the trenches are then oxidized, thereby forming a gate oxide, which isolates the gate electrode from doped regions 32 , 59 and 57 . The trenches are then partially filled with silicon dioxide, for example by a chemical vapor deposition process. A conformally doped polysilicon layer is then deposited across the structure. After the anisotropic etch step removes the entire conformal polysilicon layer except that shown in Figure 15A, another trench fill operation is performed to complete the trench fill. A suitable planarization step is then performed, for example using chemical mechanical polishing or other techniques. Later in the process, electrical connections are made to couple the gate 80 to control the gate line (GL).

FIG. 16 is a circuit diagram showing an array of thyristor memory cells 72 with gates 80 added as described above. The gate 80 short-circuits the NPN transistor 82 when turned on by the gate line GL, and connects the base of the PNP transistor 83 to the cathode line KL. This approach has the advantages mentioned above - lowering the write voltage and allowing faster writing of data.

Figure 17 shows another embodiment of a vertical thyristor cell with two sidewall PMOS gates 86 in a deep trench. These cells are formed in the same manner as the gate 80 described above. A buried gate 86 may be connected at the pickup region and coupled to a gate line (GL). These gates are formed in the same manner as described above. After the deep silicon trench etch step, a trench gate oxide is formed. The trench is then partially filled with silicon dioxide to a depth above the N-cathode/P-base junction. A conformal conductive gate layer, such as doped polysilicon, is then formed. The gate layer is then anisotropically etched to form a sidewall gate completely covering the N-type base. Finally, the trenches are filled with silicon dioxide and then planarized using known techniques.

FIG. 18 is a circuit diagram of a memory array using the PMOS gate 86 of FIG. 17 . The gate 86 short-circuits the PNP transistor 83 when turned on by the gate line GL, and connects the base of the NPN transistor 82 to the anode line AL. This approach has the same advantages as described above for NMOS gates.

One potential problem with using thyristor arrays as memory cells is the high row current required to read the memory cells during access operations. (The word "row" is used here as a synonym for anode and "column" for cathode. Wordlines and bitlines can also be used.) To reduce the need for higher row currents, use what we call rolling wordlines Technology. This method is described in conjunction with FIG. 19 .

Figure 19A shows a row of thyristor memory cells in a memory array. The row consists of N columns of memory cells divided into M groups of cells. A set of 4 units is shown at the left end of the row. Using 4 cells for a group is just an example; in a real integrated circuit there will be far more than 4 cells in a group. To access cells, eg, to read data from or write data to them, a voltage VSelected is applied to the column lines of all members of the set. All other column lines receive potential VHold, where VHold is higher than VSelected. As a result, the selected group will have the current:

I group selected = M*I Selected, where I Selected is the current for one cell.

The remaining N/M-1 groups of cells in the row will have the current:

I group hold = (N/M-l)*M*I hold, where I hold is the current for one cell.

When using a memory array, the procedure is to apply the selected potential for the desired operation to the first group while biasing all remaining groups to "hold". Once the desired operation on the first set is complete, the bias on the first set is changed to "hold" and the bias on the next set to the selected potential, such as shown in Figure 19B. By repeating these steps of holding all groups of cells on a word line at a "hold" potential except the selected group, and repeating this operation group by group, the row current is reduced. We call this technique "scrolling" the wordlines.

For memory cells with highly non-linear current and voltage relationships, the holding current for the cell can be orders of magnitude lower than the read current for the selected cell. For example, assume a row has 128 columns divided into 8 groups of 16 cells each. In a typical implementation, the selected current will be approximately 10 μA, while the holding current will be approximately 10 pA, a difference of six orders of magnitude. therefore:

In case of no scrolling: I row = 128*l0uA = 1.28mA

In case of scrolling: I row=16*10uA+(128-16)*10pΑ=160uA

Thus, scrolling the word line in the manner described above provides an 88% reduction in word line current, and 8 scrolling accesses to access a complete row.

Since each thyristor cell that is "on" in the memory array will consume some current, the current consumption of the memory array and the number of such "on" cells depends on the particular data being stored in the array. This has the undesired effect of tying power consumption to the actual data stored in memory. This standby current can be reduced using a data encoding that aims to keep approximately 50% of the cells at logic "1".

For example, consider an 8-bit word with 2 extra parity bits.

In the following example, the check digit is the first two digits preceding the stored word of data and is italicized.

Example 1: All are ones: 1111-1111 becomes 10-0000-1111, so 8 ones become 5 ones.

Example 2: 50% + 1 one: 1010_1011 becomes 01_1010_0100, so 5 ones become 4 ones.

Example 3: 50% to ones: 1010_1010 becomes 00_1010_1010, so 4 ones become 4 ones.

Example 4: 50% - 1 one: 0010_1010 becomes 00_0100_1010, thus 3 ones becomes 3 ones.

Example 5: All zeros: 0000_0000 becomes 10_1111_0000, so 0 ones become 5 ones.

Example 6: 5 ones: 0011_1011 becomes 11_1100_0100, so 5 ones become 3 ones.

The above data encoding techniques, or other similar methods, are useful where the array standby current is to be maintained at a relatively constant level, and are used for current source controlled standby operation. Conventional logic circuitry can be used to detect the number and position of ones, perform the desired inversion (or not) and add a check bit to the stored data.

In an embodiment associated with FIG. 14, the data stored in the thyristor memory array is held inactive by supplying a hold voltage or current so that no refresh is required. Under these inactive conditions, all memory cells holding "0" data conduct a very low but limited current. Due to the exponential relationship between holding current and holding voltage, it is advantageous to use a current source to keep the cell active when not in use. A method is described in our earlier patent applications, e.g., U.S. Patent Application 14/590834, entitled "Cross-Coupled Thyristor SRAM Circuits and Methods of Operation," filed January 6, 2015, which is incorporated by reference The patent application is incorporated herein. There we describe techniques for maintaining data retention at low standby currents using constant current sources to bias the array to an optimal retention voltage. Although this approach is discussed in connection with SRAM memory, it can also be used for other thyristor-based volatile memories, such as those described herein.

In the biasing scheme described above, all memory cells holding "0" data conduct a very low but limited current in order to maintain array data without refreshing. An alternative is to regulate the supplied current to a lower value, not sufficient to maintain data integrity indefinitely, but sufficient to maintain data integrity for a minimum "hold" period (eg 1 ms). This approach allows for a significant reduction in standby current. However, to maintain data integrity indefinitely, a background refresh operation is performed on a sector-by-sector basis where the holding current set for a sector is increased to a higher value for a short period of time to re-establish the cell level to better value, but then reduce back to normal standby current. This allows all cells in a sector to be refreshed simultaneously, rather than row by row as is currently done with conventional DRAM. Also, flushing does not interfere with normal read/write operations, making flush operations invisible to the outside. This method is illustrated in FIG. 20 .

The figure shows how one refresh pulse can refresh an entire sector. A refresh pulse applied to line 90 while CMOS switch 92 is on will refresh the sector of memory cells 72 . This example shows current controlled inactivation/refresh, however, the same approach can be applied to voltage controlled inactivation/refresh.

Figure 21 is a circuit diagram illustrating one technique for reading data from a thyristor array. Sense amplifier 95 has one input connected to a column of memory cells 72 of the memory array. The other input of the sense amplifier 95 is connected to a column of dummy memory cells 94 . Memory cells 72 and dummy cells 94 have column lines precharged to 0 volts. During a read operation, the state of the programmed memory cell 72 will shift the potential of the column line up if the cell is a "0" or near 0V if the cell is a "1". The column lines of the dummy memory cells are shifted up by the current source at a rate that is 1/2 the rate at which the sense amplifier 95 generates differential data for the column in the selected array. If the selected cell is "0", the selected column will be raised above the dummy column. If the selected cell is "1", the dummy column will be raised above the selected column. The sense amplifier output can then be interpreted as a "1" or "0" indicating the stored data.

This description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form described, and many modifications and variations are possible in light of the above teaching. The embodiment was chosen and described in order to best explain the principles of the invention and its practical application. This description will enable those skilled in the art to best utilize and practice the invention in various embodiments with various modifications adapted to a particular use. The scope of the invention is defined by the following claims.

Claims (19)

1. a volatile memory, including:

More than first line；

More than second alignment；And

The array of vertical thyristor, described vertical thyristor has and is coupled to described line and described alignment wherein One of anode and there is the negative electrode of the another one being coupled in described line and described alignment.

Volatile memory the most according to claim 1, wherein, each vertical thyristor includes:

The substrate of the first conduction type；

The buried layer of the films of opposite conductivity extended in a first direction, its negative electrode that described thyristor is provided and first row Line；

The ground floor of the first conduction type being arranged on described buried layer, it provides the first conductive-type of described thyristor Type base stage；

The second layer of setting films of opposite conductivity on the first layer, it provides the opposite conductivity class of described thyristor Type base stage；

The upper strata of the first conduction type, it provides the anode of described thyristor；And

Conductive layer, it is coupled to the described anode of described thyristor and in the second direction orthogonal with described first direction Extend, to provide the first line.

Volatile memory the most according to claim 2, also includes:

The deep region being made up of insulant, its extend through in said first direction described buried layer arrive described substrate, So that the row of thyristor are separated from each other；And

The shallow region being made up of insulant, it extends to described buried layer to be separated from each other by thyristor row.

Volatile memory the most according to claim 3, wherein:

Described substrate includes silicon；

Each in described ground floor, the described second layer and described upper strata includes the part of silicon epitaxial layers；And

Each in described deep region and described shallow region includes silicon dioxide.

Volatile memory the most according to claim 4, wherein:

Described first conduction type is P；And

Described films of opposite conductivity is N.

Volatile memory the most according to claim 1, also includes the nmos pass transistor being coupled to described thyristor.

Volatile memory the most according to claim 6, wherein:

Each thyristor includes the PNP transistor with emitter stage, base stage and colelctor electrode and has emitter stage, base stage NPN transistor with colelctor electrode；

The emitter stage of described PNP is coupled to described line, and the base stage of described PNP is coupled to the colelctor electrode of described NPN, described PNP Colelctor electrode be coupled to the base stage of described NPN, and the colelctor electrode of described NPN is coupled to described alignment；

Described nmos pass transistor has an electrode by the colelctor electrode offer of described NPN, by the emitter stage offer of described NPN Another electrode and grid, described grid is coupled to when described grid is switched on be connected to the colelctor electrode of described NPN The emitter stage of described NPN；And

Memory array includes the gate line being coupled to the described grid of multiple nmos pass transistor grid.

Volatile memory the most according to claim 7, wherein, described gate line is parallel to described alignment and extends.

Volatile memory the most according to claim 1, also includes the PMOS transistor being coupled to described thyristor.

Volatile memory the most according to claim 9, wherein:

Each thyristor includes the PNP transistor with emitter stage, base stage and colelctor electrode and has emitter stage, base stage NPN transistor with colelctor electrode；

The emitter stage of described PNP is coupled to described line, and the base stage of described PNP is coupled to the colelctor electrode of described NPN, described PNP Colelctor electrode be coupled to the base stage of described NPN, and the colelctor electrode of described NPN is coupled to described alignment；

Described PMOS transistor has an electrode by the colelctor electrode offer of described PNP, by the emitter stage offer of described PNP Another electrode and grid, described grid is coupled to when described grid is switched on be connected to the colelctor electrode of described PNP The emitter stage of described PNP；And

Memory array includes the gate line being coupled to the described grid of multiple PMOS transistor grid.

11. volatile memory according to claim 7, wherein, described gate line is parallel to described alignment and extends.

12. 1 kinds of methods manufacturing volatile memory array, described volatile memory array has line, alignment and vertical The array of thyristor, described vertical thyristor has the sun of one of them being coupled to described line and described alignment Pole, and there is the negative electrode of the another one being coupled in described line and described alignment, described method includes:

The adulterant of films of opposite conductivity is introduced in the Semiconductor substrate of the first conduction type, thus to provide buried layer, institute State buried layer and provide negative electrode for each in described vertical thyristor；

Described buried layer is formed the epitaxial layer of the first conduction type；

Remove all of described epitaxial layer and described buried layer, with from the first party upwardly extending in described memory array More than one parallel zone exposes the part of described substrate, to be consequently formed more than first deep trench；

Insulant is utilized to fill described more than first deep trench；

Remove all of described epitaxial layer, with from upwardly extending more than second parallel zone of second party in described memory array Territory exposes the part of described buried layer, to be consequently formed more than second shallow trench；

Insulant is utilized to fill described more than second shallow trench；

The adulterant of films of opposite conductivity is introduced, with the films of opposite conductivity district above being formed in the top of described epitaxial layer Territory, the opposite conductivity type regions of described top is separated with described buried layer by the bottom of described epitaxial layer；And

Introduce the adulterant of the first conduction type to the top of the opposite conductivity type regions of described top, with formed described vertically The anode of each in thyristor.

13. methods according to claim 11, also include the step providing the electrical connection leading to described anode.

14. methods according to claim 12, wherein, it is provided that the step of electrical connection includes:

Refractory metal is introduced in described anode；And

Described anode is annealed, to be consequently formed metal silicide layer.

15. methods according to claim 11, also include:

Before the step of the adulterant introducing the first conduction type at the top of the opposite conductivity type regions above described, The step of another epitaxial layer is formed on the upper surface of described epitaxial layer；And

There is provided the electrical connection leading to another epitaxial layer described after a while, to provide the company of the described anode leading to described thyristor Connect.

16. 1 kinds of methods manufacturing volatile memory array, described volatile memory array has line, alignment and vertical The array of thyristor, described vertical thyristor has the sun of one of them being coupled to described line and described alignment Pole, and there is the negative electrode of the another one being coupled in described line and described alignment, described method includes:

The adulterant of films of opposite conductivity is introduced in the Semiconductor substrate of the first conduction type, thus to provide buried layer, institute State buried layer and provide negative electrode for each in described vertical thyristor；

Described buried layer is formed the first epitaxial layer of the first conduction type；

Described first epitaxial layer is formed the second epitaxial layer of films of opposite conductivity；

Remove all of described first epitaxial layer and described second epitaxial layer and described buried layer, with from described memory array Upwardly extending more than first parallel zone of first party of row exposes the part of described substrate, deep to be consequently formed more than first Groove；

Insulant is utilized to fill described more than first deep trench；

Remove all of described first epitaxial layer and described second epitaxial layer, with in the second direction in described memory array More than second parallel zone extended exposes the part of described buried layer, to be consequently formed more than second shallow trench；

Insulant is utilized to fill described more than second shallow trench；And

The adulterant of the first conduction type is introduced, to be formed in described vertical thyristor to the top of described second epitaxial layer The anode of each.

17. methods according to claim 15, also include the step providing the electrical connection leading to described anode.

18. methods according to claim 16, wherein, it is provided that the step of electrical connection includes:

Refractory metal is introduced to described anode；And

Described anode is annealed, to be consequently formed metal silicide layer.

19. methods according to claim 15, also include:

Before the step of the adulterant introducing the first conduction type at the top of opposite conductivity type regions upward, described The step of another epitaxial layer is formed on the upper surface of the second epitaxial layer；And

There is provided the electrical connection leading to another epitaxial layer described after a while, to provide the company of the described anode leading to described thyristor Connect.