CN107358975A - Power reduction in thyristor random access memory - Google Patents

Power reduction in thyristor random access memory Download PDF

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CN107358975A
CN107358975A CN 201710454983 CN201710454983A CN107358975A CN 107358975 A CN107358975 A CN 107358975A CN 201710454983 CN201710454983 CN 201710454983 CN 201710454983 A CN201710454983 A CN 201710454983A CN 107358975 A CN107358975 A CN 107358975A
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thyristor
array
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memory
data
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H·栾
B·贝特曼
V·阿克赛尔拉德
C·程
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克劳帕斯科技有限公司
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    • H01L27/1023Bipolar dynamic random access memory structures
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    • H01L27/102Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
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    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66363Thyristors
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/87Thyristor diodes, e.g. Shockley diodes, break-over diodes
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    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406Management or control of the refreshing or charge-regeneration cycles

Abstract

The invention relates to power reduction in thyristor random access memory and discloses a volatile memory array using vertical thyristors is disclosed together with methods of reducing power consumption in such arrays.

Description

闸流晶体管随机存取存储器中的功率减小 Thyristor power of the random access memory is reduced

[0001] 本申请是申请日为2015年9月25日、发明名称为“闸流晶体管随机存取存储器中的功率减小”的专利申请201580010700.1的分案申请。 [0001] This application is filed September 25, 2015, entitled divisional application of patent application 201580010700.1 "thyristor of the random access memory power reduction" in.

[0002] 相关申请的交叉引用 CROSS [0002] REFERENCE TO RELATED APPLICATIONS

[0003] 本专利申请涉及同一日期提交的题为“Thyristor VolatiIe Random AccessMemory and Methods of Manufacture”的美国专利申请No. 14/841140、同一日期提交的题为“Methods of Reading and Writing Data in a Thyristor Random Access Memory”的美国专利申请No · 14/841521、同一日期提交的题为“Methods of Retaining andRefreshing Data in a Thyristor Random Access Memory” 的美国专利申请No · 14/841578;所有这些申请都要求享有于2015年6月29日提交的题为“High-Density VolatileRAMs ,Method of Operation and Manufacture Thereof” 的美国临时专利申请No .62/186336的优先权,并且是2015年I月6日提交的题为“Cross-Coupled Thyristor SRAMCircuits and Methods of Operation”的美国申请No. 14/590834的部分延续案,其要求享有2014年9月25日提交的美国临时专利申请No.62/055582的优先权;出于所有目的通过引用的方式将所有申请并入本文中。 [0003] The present patent application relates to the same date herewith, entitled "Thyristor VolatiIe Random AccessMemory and Methods of Manufacture" U.S. Patent Application No. 14/841140, entitled "filed on the same date Methods of Reading and Writing Data in a Thyristor Random Access Memory "US Patent application No · 14/841521, filed on the same date, entitled" Methods of Retaining andRefreshing Data in a Thyristor Random Access Memory "US Patent application No · 14/841578; All of these applications require the benefit of 2015 on June 29, entitled filed "High-Density VolatileRAMs, Method of Operation and Manufacture Thereof" US provisional Patent application No priority .62 / 186,336, and is entitled May 6, 2015, I filed "Cross -Coupled Thyristor SRAMCircuits and Methods of Operation "continuation in part of US application No. 14/590834 case, which claims the benefit of US provisional Patent September 25, 2014 filed No.62 / 055582; and for all purposes by reference in all applications are incorporated herein by reference.

背景技术 Background technique

[0004] 本发明涉及集成电路器件,并且具体而言,涉及通常被称为动态随机存取存储器(DRAM)的易失性随机存取存储器。 [0004] The present invention relates to integrated circuit devices, and in particular, relates to a volatile commonly referred to as a dynamic random access memory (DRAM) is a random access memory.

[0005] DRAM是一种类型的随机存取存储器集成电路,在最常用的商业实施方式中,其在耦合到集成电路内的晶体管的独立电容器中存储数据的每个位。 [0005] DRAM is a type of random access memory integrated circuits, the most commonly used in commercial embodiments, each data bit is stored in a separate capacitor is coupled to the transistor in the integrated circuit. 电容器可以被充电或放电。 Capacitors may be charged or discharged. 充电或放电的状态被解释为位的值,即“〇”和“1”。 Charging or discharging state is interpreted as a bit value, i.e., "square" and "a." 在过去30年间,一个晶体管一个电容器的单元已经是DRAM器件中使用的最商用的存储器单元。 Over the past 30 years, one transistor one capacitor unit has the most commercial DRAM memory cell used in the device. 光刻缩放和增大工艺复杂性已经实现了大约每三年将DRAM中的存储器的位数翻四倍,然而,个体存储器单元现在非常小,维持每个单元的电容并减小电荷泄漏是阻碍尺寸进一步减小的主要问题。 Photolithography scaling and increased complexity of the process has achieved approximately every three years the number of bits in DRAM memory quadruple, however, an individual memory cell is now very small, the capacitance of each unit to maintain the reduced charge leakage and hindering the main problem is further reduced in size.

[0006] 响应于这些挑战和其它问题,已经提出了替代的DRAM存储器单元架构。 [0006] In response to these challenges and other problems, there has been proposed an alternative architecture of the DRAM memory cell. 一种这样的方法被称为浮体DRAM (FBDRAM) JBDRAM是构建于绝缘体上硅(SOI)上的单个MOSFET(Okhonin,Int .SOI Conf ·,2001)或构建于具有掩埋N植入物的三阱中(Ranica,VLSITeChn〇l〇gy,2004)。 One such method is called a floating body DRAM (FBDRAM) JBDRAM MOSFET is constructed on a single silicon (SOI) on-insulator (Okhonin, Int .SOI Conf ·, 2001) or construct having three buried N-well implant in (Ranica, VLSITeChn〇l〇gy, 2004). 晶体管的主体形成了抵靠绝缘衬底的电容器。 A transistor formed body against the capacitor insulating substrate. 该技术尚未解决其数据保持问题,尤其是在缩小的尺寸上。 The technology is not yet solve the problem of maintaining their data, especially on a reduced size.

[0007] 新DRAM架构的另一种方法基于PNPN闸流晶体管的负差分电阻行为。 [0007] Another new method of DRAM architecture based on a negative differential resistance behavior PNPN thyristor. 在这些设计中,使用了有源或无源栅极。 In these designs, the use of active or passive gate. 例如,美国专利6462359中描述的薄电容耦合闸流晶体管使用了SOI衬底上的横向PNPN闸流晶体管,其中耦合栅极用于提高开关速度。 For example, a thin capacitive coupling thyristor described in U.S. Patent 6,462,359 using a PNPN thyristor laterally over the SOI substrate, wherein the gate is coupled for increasing the switching speed. 令人遗憾的是,该设计的横向外观连同其对栅极的需求,导致存储器单元显著大于常规的一个晶体管一个电容器的DRAM单元结构。 Regrettably, this design with its demand for the appearance of transverse gate, resulting in significantly larger than the memory cell structure of a conventional DRAM cell of one transistor one capacitor.

[0008] Liang在美国专利9013918中描述了PNPN闸流晶体管单元,其构造于硅衬底顶部并工作于正向和反向击穿区,以向单元中写入数据。 [0008] Liang described in U.S. Patent No. 9,013,918 in the PNPN thyristor unit, configured on top of a silicon substrate and operates in forward and reverse breakdown region, in order to write data to the unit. 令人遗憾的是,在标准CMOS工艺的后端使用外延或CVD半导体层增加了热循环和蚀刻步骤,这能够降低较早形成于同一衬底上的其它器件的性能和产率。 Unfortunately, the use of CVD epitaxial semiconductor layer or increased etching step thermal cycling and the rear end of the standard CMOS process, which can reduce the yield and performance of other devices in the earlier formed on the same substrate. 此外,工作于击穿机制中的PNPN器件在工艺控制和功耗方面提出了挑战。 In addition, work breakdown mechanisms in PNPN devices present challenges in process control and power.

[0009] 需要比常规的一个晶体管一个电容器小的DRAM存储器单元,其容易在20nm设计规则以下缩放,与标准的体硅处理兼容,并消耗更少的静态和动态功率。 [0009] require less than a conventional one transistor one capacitor DRAM memory cell, which is easy to design rules or less in the 20nm scale, the process is compatible with standard bulk silicon, and consume less static and dynamic power.

发明内容 SUMMARY

[0010] 本发明提供了一种适于动态随机存取存储器的实施方式的易失性存储器阵列,其中垂直PNPN闸流晶体管形成在体硅衬底中并通过一个方向上的绝缘材料的浅沟槽和垂直方向上的绝缘材料的较深沟槽而彼此隔离。 [0010] The present invention provides a volatile memory array suitable for embodiment of a dynamic random access memory, wherein the vertical PNPN thyristor formed in a bulk silicon substrate through an insulating material in the direction of a shallow trench deep trench insulating material on the groove and isolated from each other in the vertical direction. 存储器单元阵列被布置成交叉点网格并由金属导体和掩埋重掺杂层来互连。 The memory cell array is arranged in intersections of the grid conductors by a metal layer and a heavily doped buried interconnected.

[0011] 在一个实施例中,存储器阵列包括行线和列线,并且每个闸流晶体管具有连接到行线之一的阳极和耦合到列线的阴极。 [0011] In one embodiment, the memory array comprising a row and column lines, and each having a thyristor connected to one row line of the anode and the cathode coupled to column lines. 衬底优选为P导电类型,具有在第一方向上延伸的N导电类型掩埋层,以提供列线和闸流晶体管的耦合到该列线的阴极。 Preferably the substrate is a P conductivity type having an N conductivity type buried layer extending in a first direction, column lines and to provide a coupling to the cathode of the thyristor of the column lines. 掩埋层上的交替的P导电类型和N导电类型层提供了闸流晶体管的基极,上方P导电类型层提供了闸流晶体管的阳极。 Alternating N and P conductivity type buried conductive type layer on the base layer provides a thyristor electrode, over the P type conductivity layer provides an anode of the thyristor. 在与第一方向正交的第二方向上延伸的耦合到闸流晶体管的阳极的导电层提供了行线。 Coupling extending in a second direction orthogonal to the first direction to the conductive layer of the thyristor to the anode of the transistor provides the row lines. 如果希望的话,在绝缘材料中形成栅极,以提供NMOS和PMOS晶体管,用于改善开关速度。 If desired, forming a gate insulating material to provide the NMOS and PMOS transistors, for improving the switching speed.

[0012] —种制造阵列的方法包括向P导电类型半导体衬底中引入N导电类型掺杂剂以提供掩埋层的步骤,以为垂直闸流晶体管形成列线和阴极。 [0012] - A method of fabricating an array comprising introducing N conductivity type dopant into the P-conductive type semiconductor substrate to provide a buried layer of the step, that the vertical column lines form a thyristor and the cathode. 然后在掩埋层上形成P导电类型外延层。 Then forming a P conductive type epitaxial layer on the buried layer. 然后蚀刻去除了所有的外延层和掩埋层以暴露衬底的部分,以形成平行的深沟槽,然后利用诸如二氧化硅的绝缘材料填充深沟槽。 It is then removed by etching all of the epitaxial layer and the buried layer to expose portions of the substrate to form deep trenches in parallel, and then an insulating material such as silicon dioxide filled deep trench. 然后再次蚀刻外延层以形成垂直于深沟槽的较浅沟槽。 Epitaxial layer is then etched again to form a shallow trench perpendicular to the deep trench. 在利用绝缘材料填充浅沟槽之后,对闸流晶体管的基极和阳极掺杂,并且形成期望的电接触部和连接器。 After filling the shallow trench with an insulating material, of the thyristor and the anode of the base doping, and forming the desired electrical contact portion and the connector.

[0013] —种操作存储器阵列以将选定的闸流晶体管编程为“导通”的方法包括如下步骤:向与选定闸流晶体管连接的行线施加正电势,并向与选定闸流晶体管连接的列线施加较低电势,其中正电势与较低电势之间的差大于导通闸流晶体管所需的电势差。 [0013] - modes of operation of the memory array to a selected thyristor is programmed "on" the method comprising the steps of: applying a positive potential to the selected row line is connected to the thyristor, the gate and the selected stream column lines connected transistors is applied to the lower potential, wherein the difference between the positive potential and the lower potential than the turn on thyristor desired difference in potential of the transistor. 所有未选定的线被施加的电势不足以改变任何其它闸流晶体管的状态。 All but the potential applied to the selected line is not sufficient to change the state of any other thyristor. 为了关断选定的闸流晶体管,向行线施加低电势,并向列线施加足以将其关断的正电势。 In order to turn-off thyristor selected, applying a low potential to the row line, column line and applying sufficient positive potential it off. 所有未选定的线被施加的电势不足以改变任何其它闸流晶体管的状态。 All but the potential applied to the selected line is not sufficient to change the state of any other thyristor.

[0014] 在向行线施加正电势并向列线施加较低电势的情况下读取选定的闸流晶体管。 [0014] The selected read thyristor in the case of applying a positive potential is applied to the row lines and column lines of lower potential. 正电势与较低电势之间的差在选定的闸流晶体管被编程为导通的情况下足以将列线拉到更高电势,但在选定的闸流晶体管被编程为关断的情况下不足以使闸流晶体管将列线拉到更高电势。 Column line sufficient to pull a case where a higher potential difference between the positive potential and the lower potential at a selected thyristor is turned on is programmed, it is programmed to be off in the case where the selected thyristors insufficient to cause the thyristor column line is pulled higher potential. 施加于未选定行和列线的电势不足以改变其数据。 Potential applied to the unselected row and column lines is insufficient to change its data. 将行线和列线上的电势维持在足以使导通的闸流晶体管继续导通,但不足以将关断的闸流晶体管导通,这保持了阵列中存储的数据。 The potential of the row line and column line is maintained at a sufficient conduction of the thyristor continues to conduct, but not enough to turn-off thyristor is turned on, which keeps the data stored in the array.

[0015] 还提供了一种用于减小要被存取以进行操作的行线中的电流的技术。 [0015] It also provides a technique for reducing the current row lines for operation in to be accessed. 耦合到行线的存储器单元被分成组,并且用于在存储器单元上执行操作的列线是通过每次仅向一组施加该操作所必需的电势来实施的。 Row lines coupled to the memory cells are divided into groups, and for performing the operations on the memory cell column lines by each time applying a potential necessary for the operation of the set only to the embodiment. 所有其它列线维持在较低电势。 All other column lines maintained at a lower potential. 然后执行操作,并选择下一组。 Operation is then performed, and selects the next group.

[0016] —种用于刷新存储器阵列的方法由如下操作构成:将阵列分成扇区,并且通过例如提供刷新线,以通过仅将扇区中要刷新的那些行线可切换地连接到刷新线来向扇区施加电流或电压脉冲,从而逐个扇区地对其刷新。 [0016] - A method for kind of the flash memory array is composed as follows: the array into sectors, and by example, the refresh line to be connected to the refresh line by line only those rows would be refreshed sector switchably current or voltage pulse is applied to the sector so that its refreshed every sector.

[0017] 因为导通的闸流晶体管会耗电,所以可以通过使用校验位更密切地平衡导通和关断的闸流晶体管存储器单元的数量来控制阵列中的功耗。 [0017] Because the thyristor is turned on will power, it is possible to balance the number of turn-on and turn-off thyristor of the memory cell by using the parity bits to more closely control the power consumption of the array. 例如,两个校验位能够为存储的字定义四种状态,它们代表不改变存储的字、反转存储的字的前四位、反转存储的字的后四位、以及反转存储的字的所有位。 For example, two parity bits can be defined as a word stored in four states that represent the stored word do not change, before the word stored in four is inverted, after inverted four words stored, and the stored inverted All bit words. 该方法允许存储的字平均具有大约相同数量的导通和关断闸流晶体管。 This method allows the storage of words having an average of about the same amount of turn-on and turn-off thyristors.

[0018] 在考虑以下具体实施方式和附图时,本发明的其它目的、特征和优点将变得显而易见,在所有附图中,相似附图标记表示相似特征。 [0018] In considering the following detailed description and the accompanying drawings, other objects, features and advantages of the present invention will become apparent from the drawings, like reference numerals denote like features.

附图说明 BRIEF DESCRIPTION

[0019] 图IA是单个闸流晶体管存储器单元的电路图。 [0019] FIG IA is a circuit diagram of a single thyristor of the memory cell.

[0020] 图IB是本文图中使用的等效电路图。 [0020] FIG. IB is an equivalent circuit diagram of FIG used herein.

[0021] 图2A是2 X 2存储器单元阵列的电路图。 [0021] FIG. 2A is a circuit diagram of a 2 X 2 array of memory cells.

[0022] 图2B是显示在集成电路中实施的2 X 2存储器单元阵列的拓扑结构的布局图。 [0022] FIG. 2B is a 2 X 2 layout view of the topology of the memory cell array in an integrated circuit embodiment of the display.

[0023] 图3A-9A是示出用于制造图1的存储器单元的过程的截面图,显示了沿来自图2B的线A〜A'的截面。 [0023] FIGS. 3A-9A is a sectional view showing a process for manufacturing the memory cell of FIG. 1, along the lines shown A~A 'cross-section from FIG. 2B.

[0024] 图3B-9B是示出用于制造图1的存储器单元的过程的截面图,显示了沿来自图2B的线B〜B'的截面。 [0024] FIGS. 3B-9B are sectional views illustrating a process for manufacturing the memory cell of FIG. 1, along the lines shown B~B 'cross-section from FIG. 2B.

[0025] 图10是示出图3-9的过程的替代过程的流程图。 [0025] FIG. 10 is a flowchart showing an alternative process of Process 3-9 of FIG.

[0026] 图IlA和IlB是示出在向选定的存储器单元中写入“0”时施加于存储器单元阵列的电势的示图。 [0026] FIG IlA and IlB are diagrams illustrating electrical potential applied to the memory cell array when writing "0" to the selected memory cell.

[0027] 图12是示出在向选定的存储器单元中写入“Γ时施加于存储器单元阵列的电势的示图。 [0027] FIG. 12 is a diagram illustrating the write potential "Γ when applied to the memory cell array in the selected memory cell shown in FIG.

[0028] 图13A和13B是示出在读取选定的存储器单元时施加于存储器单元阵列的电势的示图。 [0028] FIGS. 13A and 13B are diagrams showing the potential applied to the memory cell array in reading selected memory cell shown in FIG.

[0029] 图14是示出为保持存储器单元中存储的数据而施加于存储器单元阵列的电势的示图。 [0029] FIG. 14 is a diagram illustrating a memory cell to hold data stored in the electrical potential applied to the memory cell array.

[0030] 图15A-15B示出了闸流晶体管存储器单元,在与闸流晶体管相邻的沟槽中具有NMOS侧壁栅极;图15A显示单元的横向截面图,并且图15B显示单元的纵向截面图。 [0030] Figures 15A-15B illustrate thyristor memory cell having a gate and a sidewall NMOS thyristor adjacent trenches; transverse cross-sectional view of the display unit 15A, and 15B shows the longitudinal section of FIG. Sectional view.

[0031] 图16是示出使用图15A-B所示的栅极的单元阵列的电路图。 [0031] FIG. 16 is a circuit diagram illustrating a cell array using the gate shown in FIGS. 15A-B.

[0032] 图17A-17B示出了闸流晶体管存储器单元,在与闸流晶体管相邻的沟槽中具有PMOS侧壁栅极;图17A显示单元的横向截面图,并且图17B显示单元的纵向截面图。 [0032] Figures 17A-17B illustrate thyristor memory cell having a gate and PMOS sidewall thyristor adjacent trenches; transverse sectional view of the display unit of FIG. 17A, and 17B shows a longitudinal section of FIG. Sectional view.

[0033] 图18是示出使用图17 AB所示的栅极的单元阵列的电路图。 [0033] FIG. 18 is a circuit diagram showing a cell array using the gate shown in FIG. 17 AB.

[0034] 图19A-19B示出了滚动字线存取以减少行电流的方法;图19A显示该方法的一个步骤,其中选择第一组用于存取,并且图19B显示下一步骤,其中选择第二组用于存取。 [0034] Figures 19A-19B illustrate the word line accessed to the rolling method of reducing line current; FIG. 19A shows a step in the method, wherein selecting a first set for accessing, and FIG. 19B shows the next step, wherein selecting a second set for access.

[0035] 图20是示出刷新存储器法扇区中存储的数据的方法的电路图。 [0035] FIG. 20 is a circuit diagram illustrating a method of sectors of data stored in the flash memory in the method.

[0036] 图21是示出使用虚设位线来感测存储器单元的方法的电路图。 [0036] FIG. 21 is a circuit diagram illustrating the use of a dummy bit line sensing method of a memory cell.

具体实施方式 detailed description

[0037] 1、个体存储器单元 [0037] 1, the individual memory cells

[0038] 本发明提供了一种基于闸流晶体管的存储器单元、制造单元的方法,以及操作这种单元的阵列的方法。 [0038] The present invention provides a memory cell based on a thyristor, a method of manufacturing the unit, and a method of operation of an array of such units. 存储器单元在用于动态随机存取存储器(DRAM)集成电路以及嵌入了DRAM存储器的电路中时特别有用。 Particularly useful when the memory cell circuit for a dynamic random access memory (DRAM) integrated circuit, and is embedded in DRAM memory. 图IA是耦合在阳极存取线(AL)与阴极存取线(KL)之间的闸流晶体管的电路图。 FIG IA is a circuit diagram of the thyristor is coupled between the anode access line (AL) and the cathode access lines (KL). 闸流晶体管由两个交叉親合的双极晶体管10和12构成。 Thyristor formed by two intersecting affinity bipolar transistors 10 and 12. PNP晶体管10的发射极耦合到阳极存取线,而NPN晶体管12的发射极耦合到阴极存取线。 Emitter of the PNP transistor 10 is coupled to the anode electrode access line, while the emitter of the NPN transistor 12 is coupled to the cathode electrode access line. 如所示,两个晶体管的集电极和基极耦合在一起。 As shown, two transistors collector and base coupled together. 图IB是显示使用常规符号的闸流晶体管15的等效电路图。 FIG IB is a thyristor equivalent circuit 15 using conventional symbols. 在以下后续的图中使用该符号。 The symbols used in the subsequent figures.

[0039] 图2A示出了耦合成网格图案以形成存储器阵列的四个闸流晶体管15a、15b、15c和15d的阵列。 [0039] FIG 2A illustrates 15a, 15b, 15c, and an array of four thyristors coupled in a grid pattern to form a memory array 15d. 闸流晶体管15a和15b连接到同一行线AL 1,但连接到不同的列线KL 1和KL 2。 Thyristors 15a and 15b are connected to the same row line AL 1, but connected to different column lines KL 1 and KL 2. 类似地,闸流晶体管15c和15d连接到同一行线AL2,但连接到不同的列线KLl和KL2。 Similarly, the thyristor 15c and 15d connected to the same row line AL2, but connected to different column lines KLl and KL2.

[0040] 图2B是示出图2A中示为集成电路的电路的布局的布局图。 [0040] FIG. 2B is a diagram showing a layout shown in FIG. 2A is a circuit layout of an integrated circuit. 四个闸流晶体管为垂直闸流晶体管,在布局的角部具有阳极20。 Four vertical thyristor thyristor having an anode 20 at the corners of the layout. 深二氧化硅沟槽22将左侧的闸流晶体管与右侧那些隔离开,而浅沟槽21将上方闸流晶体管与下方那些隔离开。 Silica deep trench 22 and the left right thyristor those isolated from the shallow trench 21 and the upper and the lower transistor thyristor those isolated. 下面更详细地显示这些沟槽。 These trenches are shown below in more detail. 导电线24提供用于存储器阵列的行线,并且耦合到闸流晶体管的阳极。 Conductive lines 24 provided for the row lines of the memory array, and coupled to the anode of the thyristor. 类似的行线(未示出)延伸跨越行线24上方的行中的闸流晶体管的阳极。 The anode of thyristor transistor lines like line (not shown) extending across the top of the row lines 24. 该图还显示在以下后续的图中使用的截面A〜A '和B〜B '的位置。 The figure also shows a cross-sectional position A~A used in the following subsequent figures 'and B~B' of.

[0041] 2、制造过程 [0041] 2, the manufacturing process

[0042] 图3A和3B是用于描述用于制造图2B的顶视图中所示的结构的过程的开始的图示。 [0042] Figures 3A and 3B are diagrams for describing a process for illustrating the start of manufacturing a top view of the structure shown in FIG. 2B. 在该过程的第一步中,利用例如砷的N导电类型掺杂剂将P导电类型硅衬底30的选定区域掺杂到从IX 1〇19到5X102()的范围的浓度。 In the first step of the process, using, for example N conductivity type doped with arsenic dopants selected areas of the P conductive type silicon substrate 30 is to IX concentration ranges from 1〇19 to 5X102 () a. 半导体衬底层30可以包括单晶半导体材料,例如硅或硅锗合金。 The semiconductor substrate layer 30 may comprise a single crystal semiconductor material such as silicon or silicon-germanium alloy. 通过公知的半导体制造技术(例如,离子注入)引入N导电类型掺杂剂32,其如所示的延伸到衬底30中达200nm〜500nm的深度。 Introducing N conductivity type dopant 32 by a known semiconductor manufacturing techniques (e.g., ion implantation), extending to a depth as shown in 200nm~500nm of substrate 30. 因为整个单元阵列区域对该掩埋N型掺杂是开放的,所以在图3A和3B的两幅截面图之间没有差异。 Because the entire cell array region is doped N-type buried in the open, there is no difference between the two cross-sectional view of FIG. 3A and 3B.

[0043] 接下来,如图4A和4B所示,还使用公知的半导体制造工艺技术在下方结构的顶部形成厚度介于大约300nm与500nm之间的外延娃层35。 [0043] Next, as shown in Figures 4A and 4B, also known semiconductor manufacturing technology baby epitaxial layer having a thickness of between about 300nm and between 500nm 35 at the top of the structure below. 外延层35可以是本征的,或原位掺杂成P导电类型。 Epitaxial layer 35 may be intrinsic or in situ doped to P conductivity type.

[0044] 图5A和5B示出了该过程的下一个步骤。 [0044] Figures 5A and 5B illustrate the next step of the process. 首先,跨半导体结构的上表面生长或沉积薄二氧化硅(焊盘)层36。 First, across the upper surface of the semiconductor structure is grown or deposited thin silicon dioxide (pad) layer 36. 在层36的顶部,使用公知的工艺技术形成氮化硅层38。 In the top layer 36, a known technology is formed a silicon nitride layer 38. 使用掩模(未示出),穿过氮化硅层38和焊盘氧化物层36蚀刻开口以暴露外延层35的上表面,上表面处要形成深沟槽39。 Using a mask (not shown), through the silicon nitride layer 38 and pad oxide layer 36 is etched to expose the opening 35 of the upper surface of the epitaxial layer, the surface of the deep trench 39 to be formed. 在去除或不去除光致抗蚀剂的情况下使用图案化焊盘作为硬掩模,然后执行反应离子蚀刻(RIE)步骤,以蚀刻延伸通过存储器单元区域的深沟槽39,例如如图2B的顶视图所示。 Used in the case of removing or without removing the photoresist is patterned pad as a hard mask, and then performing a reactive ion etching (RIE) step, to etch 39 extends through the deep trench memory cell region, for example, FIG. 2B shown in top view. 这些深沟槽穿过上方的层向下延伸到衬底30。 Which extend down into the substrate 30 through the layer over the deep trench. 注意,深沟槽彼此平行,并且因而未出现在图5B中所示的截面中。 Note that, the deep trench parallel to each other, and thus does not appear in the cross section shown in FIG. 5B.

[0045] 如图6A接下来所示,用诸如二氧化硅42的绝缘材料填充深沟槽39。 [0045] Next as shown in FIG. 6A, the deep trench 39 is filled with an insulating material 42 such as silicon dioxide. 这是通过首先在沟槽的侧壁和底部的暴露的硅表面上生长薄衬垫氧化物来实现的。 This is accomplished by first growing a thin liner oxide on the exposed trench sidewalls and the bottom silicon surface. 然后,例如,使用高密度等离子体(HDP)增强化学气相沉积(CVD),用二氧化硅将沟槽填充到适当厚度,通常在结构的上表面上方延伸。 Then, for example, using a high density plasma (HDP) enhanced chemical vapor deposition (CVD), filling the trenches with silicon dioxide to a suitable thickness, generally extends above the upper surface of the structure. 接下来,使用利用高选择性研磨液的公知化学机械抛光(CMP)对表面进行平面化,并去除向下到达焊盘氮化物的过多的沟槽氧化物。 Next, using a known chemical mechanical polishing is highly selective polishing slurry (CMP) to planarize the surface, and removing the excess trench oxide down to the pad nitride. 然后,如图6B所示,执行另一掩模步骤并且蚀刻较浅沟槽40。 Then, as shown in FIG. 6B, and the step of performing another mask 40 is etched shallower trenches. 需注意,较浅沟槽的深度延伸至N导电类型外延层32,而不向下延伸至P型衬底。 It should be noted, shallow trench extends to the N conductive type epitaxial layer 32, without extending down to P-type substrate.

[0046] 接下来,如图7B所示,通过与上文所述相同的方式,使较浅沟槽氧化,然后用二氧化硅45填充沟槽。 [0046] Next, as shown in FIG. 7B, by the same manner as above, so shallow trench oxide and then filling the trench 45 with silicon dioxide. 在用二氧化硅填充沟槽并通过CMP使沟槽平面化之后,再次使用常规的湿法或干法蚀刻来蚀刻掉二氧化硅和氮化硅的上层。 After filling the trenches with silicon dioxide and planarized by CMP groove, again using a conventional wet or dry etch to etch away the upper layer of silicon dioxide and silicon nitride.

[0047] 图8A和8B示出了过程的后续步骤。 [0047] Figures 8A and 8B illustrate the subsequent steps of the process. 使用离子注入步骤将P导电类型52和N导电类型54杂质引入半导体的上表面中,创建PNPN闸流晶体管结构。 An ion implantation step 52 and the P conductivity type N conductivity type impurity is introduced on the surface of the semiconductor 54, the PNPN thyristor structure created. N导电类型杂质优选为砷,而P导电类型杂质优选为硼,例如二氟化硼。 Preferably N conductive type impurity is arsenic, preferably the P conductive type impurity is boron, boron difluoride, for example. 在形成区域52之后,诸如钛、钴或镍等难熔金属被沉积到上表面上。 After forming region 52, such as a titanium, cobalt or nickel refractory metal is deposited on the upper surface. 然后执行快速热退火(RTP)以在诸如区域50等半导体区域中创建导电金属硅化物,以提供与闸流晶体管的阳极50的欧姆接触。 Then rapid thermal annealing (RTP) to create a conductive metal silicide in a semiconductor region such as region 50 or the like, to provide an ohmic contact with the anode 50 of the thyristor. 然后通过湿法蚀刻去除未反应的金属。 Unreacted metal is then removed by wet etching. 掩埋N型区域32提供阴极连接。 The buried N-type region 32 connected to provide a cathode.

[0048] 图8B中还示出了提供将一行的闸流晶体管的阳极连接在一起的行线的导电线58。 [0048] FIG. 8B also shows a row line provides a line connecting together the anode of thyristor 58 conductive lines. 使用公知的半导体制造技术形成可以是金属、金属硅化物或掺杂多晶硅的这些导体。 Using well-known semiconductor manufacturing techniques may be formed a metal, a metal silicide or doped polysilicon conductors. 为了简单起见,仅在图8B中示出了行线导体,并且在本文后续附图中未示出行线导体。 For simplicity, only shown in FIG. 8B row conductors, and herein not illustrated in the subsequent traveling line conductors.

[0049] 图9A和9B示出了用于阳极结构56的替代的实施例。 [0049] FIGS. 9A and 9B illustrate an alternative embodiment of an anode structure 56. 如所示,可以使用提高的源极/漏极技术,通过在结构的上表面上选择性外延生长硅来形成阳极。 As shown, may be used to improve the source / drain technique, formed by an anode structure on the upper surface of the selective epitaxial growth of silicon. 可以原位或使用掩模和注入步骤对P型区域52进行掺杂。 Or may be in situ implantation step using a mask and P-type region 52 is doped. 根据前述实施例,可以使用难熔金属和退火步骤形成阳极电极。 According to the foregoing embodiment, the refractory metal may be used to form an anode electrode and annealing steps. 提高的源极/漏极技术提供了允许较浅沟槽的优点,不过仍然能够实现分别用于N和P区域54和35的额外空间。 Elevated source / drain technique provides the advantage of allowing a shallow trench, but can still be achieved for respectively the N and P regions 54 and 35 of the additional space.

[0050] 图10是示出用于制造垂直闸流晶体管的替代实施例的流程图。 [0050] FIG. 10 is a flowchart showing an alternative for fabricating a vertical thyristor embodiment. 上文所述用于制造垂直闸流晶体管的方法的一个可能缺点在于,注入的P型基极和N型基极区域(图8中的区域52和54)可能由于较高能量注入离子散射和沟道穿通而具有峰值浓度和厚度极限。 The above method for fabricating a vertical thyristor One possible disadvantage is that the implanted P-type base and the N-type base region (region 52 in FIG. 8 and 54) may be due to the high energy ion implantation and diffusion through a channel having a peak concentration and the thickness limit. 图10示出了用于实现可能更符合期望的基极掺杂分布曲线,同时维持平面硅表面的替代过程。 Figure 10 shows a group may be better suited for achieving a desired doping profile, while maintaining the surface of the planar silicon substitution process.

[0051] 过程开始于步骤60—一掩埋层N型注入一一如关于图3所述。 [0051] The process begins at step 60 a N type buried layer as described with respect to FIG. 3 eleven. 然后在步骤61中,如图4所示,跨上表面生长期望厚度(例如80nm-130nm)的外延硅。 Then in step 61, FIG. 4, step onto the surface of the epitaxially grown silicon a desired thickness (e.g., 80nm-130nm) of. 接下来在步骤62中,利用光致抗蚀剂或其它材料对集成电路的周边区域进行掩蔽。 Next, at step 62, the integrated circuit of the peripheral region is masked using a photoresist or other material. 然后在步骤65中,用适当的掺杂剂注入P型基极区域(图5中的区域35)。 Then, in step 65, the implanted P-type base region (region 35 in FIG. 5) with a suitable dopant. 然后从晶片去除掩模材料(步骤66),并且然后跨晶片的上表面生长期望厚度(例如120nm-200nm)的另一个外延层,并将该外延层掺杂为N型以形成N型基极区域。 The mask material is then removed (step 66) from the wafer, the wafer and then across the upper surface of the epitaxial layer thickness growth of the other (e.g. 120nm-200nm) is desired, and doping the N-type epitaxial layer to form an N-type base area. 最后,替代过程返回到如以上图5-8中所述的沟槽隔离区域的形成。 Finally, the process returns to substitute a trench isolation region formed as described above in Figures 5-8.

[0052] 3、存储器单元阵列的操作 [0052] 3, the operation of the memory cell array

[0053] 图IlA示出了使用上文描述的闸流晶体管的存储器单元的较大阵列的一部分。 [0053] FIG IlA shows a portion of a larger array of memory cells using a thyristor described above. 该图将允许解释操作任意尺寸的存储器阵列以读取、写入、刷新和通过其它方式操作存储阵列的方法。 The figure explaining the operation of the memory array allows any size to read, write, and refresh operation of the memory array of methods by other means. 尽管示出了3X3阵列,但应当注意,本发明不限于任何特定数量的阳极和阴极存取线或存储器单元。 Although a 3X3 array, it should be noted that the present invention is not limited to any particular number of access lines or the anode and cathode of memory cells. 在该示例性存储器阵列中,个体存储器单元72均被连接到阳极线AL和阴极线KL。 In the exemplary memory array, individual memory cells 72 are connected to the anode line AL and the cathode line KL. 例如,存储器单元72kn连接到阳极线ALk和阴极线KLn。 For example, the memory cells connected to 72kn cathode line and anode line ALk KLn.

[0054] 在图IIA中以及在后续各图中,用于存储器阵列操作的“选定的”存储器单元是中心单元72加。 [0054] In FIG IIA as well as in subsequent figures, the operation of a memory array "selected" memory cell 72 is added to the central unit. 关于图IlA描述的操作的目的是向选定的单元写入一位的数据(逻辑“0”)而不妨碍其它存储器单元的内容。 Purpose The operations described in FIG IlA is writing a data (logic "0") to the selected cell without interfering with the contents of other memory cells. 出于例示的目的,在图中针对每个单元示出了在阵列的其它单元中存储的样本数据。 For purposes of illustration, in the figure for each cell it shows that the sample data stored in the other cell array. 例如,单元72im为存储“0”的“导通”,而单元72kn为存储“Γ的“关断”。 For example, the storage unit 72im is "0" and "on", and the storage unit 72kn "Gamma]" off. "

[0055] 图11中的每个阳极线和阴极线显示了施加于该线以实施期望的操作一一向单元72jm写入逻辑状态“0”(闸流晶体管“导通”)的电压。 Each anode and cathode lines in [0055] FIG. 11 shows the operation applied to the line to implement a desired logic state has been written 72jm cell voltage "0" (thyristor "on") of the. 应当注意,这里描述的电压范围仅仅出于例示的目的,因为特定实施方式中使用的精确电压取决于实际的几何设计,并且还取决于用于满足目标产品规格的精确掺杂浓度。 It should be noted that the voltage range described herein for purposes of illustration only, since the exact voltage of a particular embodiment depends on the actual geometry used in the design, and also depending on the exact doping concentration of the target to meet product specifications. 此外,只要阳极线与阴极线之间的电压差保持相同,就可以向上或向下移动每个电压电平。 Further, as long as the line voltage between the anode and the cathode line difference remains the same, you can move up or down each voltage level.

[0056] 为了写入“0”,将未选定的阳极线ALi和ALk保持在大约1.8-2.1伏的电势,而将选定的阳极线ALj提高到2.4-3伏。 [0056] In order to write "0", the anode lines unselected ALk ALi and maintained at the potential of about 1.8 to 2.1 volts, while the selected anode line ALj raised to 2.4-3 volts. 将未选定的阴极线KLl和KLn保持在1.2-1.5伏,而将选定的阴极线KLm下拉到地电势。 Unselected cathode line KLl KLn and held at 1.2-1.5 volts, and the selected cathode line KLm down to ground potential. 这些电势的效果是跨选定的闸流晶体管72jm的阳极和阴极施加2.4-3伏的电势,该电势足以将闸流晶体管72 jm导通,代表“0”状态。 Effect of these potentials is 2.4-3 volt potential is applied across the thyristor selected 72jm the anode and cathode, which potential is sufficient to thyristor 72 jm turned on, representing a "0" state. 未选定的AL和未选定的KL处的所有单元在其阳极与阴极之间具有大约0.6伏的电势,其被设计为待用或保持电压,使得那些闸流晶体管存储的数据不变。 AL unselected and all unselected cells at the KL has a potential of approximately 0.6 volts between a cathode and an anode, which is designed to stand or holding voltage, so that the data stored in the same thyristor. 对于选定的AL/未选定的KL或选定的KL/未选定的AL处的单元,在其阳极与阴极之间看到1.2V-2. IV的电势,其上限由“0”状态到“Γ状态的触发电压确定。 AL for the selected / non-selected or selected KL KL / AL at the unit is not selected, see 1.2V-2. IV potential between an anode and a cathode, the upper limit thereof is "0" state to the "state of the trigger voltage Γ OK.

[0057] 图IlA的写入“0”偏压方案的一个可能缺点是来自选定的ALj或KLm上的“0”单元(72im和72jl)的暗中泄漏,因为在其阳极和阴极之间的电压差高于待用电压。 [0057] FIG IlA write "0" biasing scheme of a possible disadvantage of leakage from the secretly selected ALj or "0" cell (72im and 72jl) on KLm, since between the anode and cathode a voltage difference higher than the standby voltage. 在又一实施例中,图IlB显示了采用半选择方案的替代的写入“0”操作。 In yet another embodiment, shown in FIG IlB semi options alternative write "0" operation. 在该替代方法中,所有未选定的AL和KL都被偏压在选定的阳极电压电平的一半处。 In this alternative method, all of the unselected AL and KL are biased at half the selected anode voltage level. 结果,未选定的AL和未选定的KL处的单元在其各自的阳极和阴极之间被偏压在0伏。 As a result, the AL and the unselected cell at the unselected KL is biased at zero volts between their respective anode and cathode.

[0058] 图12是与图IlA和IlB使用相同符号的示例性存储器单元阵列的电路图,以示出用于向选定的存储器单元72jm写入逻辑“Γ的电势。显示了用以在闸流晶体管72jm上写入“Γ的各个阳极和阴极线上的电势。 [0058] FIG. 12 is a circuit diagram of an exemplary memory cell array using the same reference numerals in FIG. IlA and IlB, to show the operation for writing logic "Γ potentials to selected memory cell 72jm. Shows a flow gate for write "potential Γ respective anode and cathode lines. 72jm transistors 将未选定的阴极线KLl和KLn保持在地电势,而将未选定的阳极线保持在〇. 5-0.7伏的电势。 Unselected cathode line KLl KLn and kept at ground potential, and unselected lines maintained at the potential of the anode billion. 5-0.7 volts. 在第一实施例中,选定的阴极线被提高至1.8-2.0伏,选定的阳极线被拉至地电势。 In the first embodiment, the selected line cathode is increased to 1.8 to 2.0 volts, the selected anode lines pulled to ground potential. 替代地,为了有利于解码器和驱动器设计,可以对AL和KL处的电势进行电平移位。 Alternatively, to facilitate decoder and driver design, a level shifter may be the potential of the AL and KL at. 例如,可以将选定的ALj和未选定的KL上的偏压从OV提高到0.6V,并且也将选定的KLm和未选定的AL上的偏压增大0.6V。 For example, the bias on the selected and unselected ALj KL can be increased from OV to 0.6V, and also the selected and unselected bias KLm on AL increased 0.6V.

[0059] 图13A是与图12使用相同符号的存储器单元阵列的电路图,以示出用于读取存储器单元的逻辑状态的阳极和阴极线上的电势。 [0059] FIG. 13A is a circuit diagram of the memory cell array using the same reference numerals in FIG. 12, to illustrate the potential for reading a memory cell logic state of the anode and cathode lines. 在该情况下,将未选定的阳极线ALi和ALk保持在0.5-0.7伏的电势,而将所有阴极线(选定的和未选定的二者)接地。 In this case, the anode lines are not selected ALk ALi and maintained at the potential of 0.5-0.7 volts, and all the cathode lines (selected and unselected both) is grounded. 选定的阳极线被提高至1.0-1.4伏。 The selected anode line is increased to 1.0 to 1.4 volts.

[0060] 如果选定的闸流晶体管72jm事先被编程为“导通”,8卩“0”逻辑状态,那么其阳极与阴极之间施加的电势将导通该闸流晶体管,并将阴极线KLm拉到较高电势。 [0060] If the selected thyristor is programmed in advance 72jm "ON", 8 Jie "0" logic state, then the motor is applied between the anode and the cathode which is bound to the conduction of the thyristor, and the cathode line KLm pulled higher potential. 耦合到阴极线KLm的公知的感测放大器检测电势的提高。 Coupled to the cathode line KLm known to improve the sense amplifier detects potential. 电势增大被解释为指示闸流晶体管处于“0”逻辑状态。 Increase potential be construed as indicating thyristor is in the "0" logic state. 另一方面,如果选定的闸流晶体管72jm事先被编程为“关断”,即“Γ逻辑状态,那么其阳极与阴极之间施加的电势将不足以将其导通。在该情况下,感测放大器将不会检测到阴极线KLm的电势有任何提高。阴极线电势没有变化被解释为指示闸流晶体管处于“Γ逻辑状态。 On the other hand, if the selected thyristors 72jm previously been programmed to "off", i.e., "Gamma] logic state, then the motor is applied between the anode and the cathode potential will be insufficient to turn on. In this case, the sense amplifier does not detect the potential of the cathode line KLm any improved cathode line potential change is not be construed as indicating thyristor is "Γ logic state. 替代地,也可以从阳极线感测选定的存储器单元的逻辑状态,因为相同的电流流入阳极并从阴极流出。 Alternatively, it is also possible, since the same current flows from the anode line sense the logic state of the selected memory cell and the cathode effluent.

[0061] 图13B示出了用于读取存储器单元中存储的逻辑状态的另一实施例。 [0061] FIG 13B shows another logical state stored in the memory cell reading embodiments. 在该方法中,在一个周期中读取整列。 In this method, the entire column in a read cycle. 所有未选定的阴极线(KL)被偏压在0.5-0.7V或其待用电平,并且选定的阳极线被预充电至待用电压以上的预定读取电压电平。 All unselected cathode line (KL) is biased to be 0.5-0.7V power level thereof, and the selected anode line is precharged to a predetermined voltage than the standby voltage level reading. 示例性范围为1〜1.4V,其驱动足够的单元电流通过存储“〇”数据的单元。 An exemplary range 1~1.4V, means a sufficient driving current through the memory cell "square" data. 耦合到选定的AL的感测放大器检测用于“0”逻辑状态的任何电势下降。 Any potential is coupled to a selected sense amplifier AL detecting a "0" logic state decreases. 相反,如果选定的阳极线上的单元预先被编程为“关断”,则检测到逻辑状态“1”。 Conversely, if the selected cell anode lines previously programmed to "OFF", then it detects a logic state "1." 因此,由于非导电单元的原因而没有电势下降。 Thus, due to the non-conductive element without the potential drop. 如果希望仅读取该列中的有限数量的单元,那么将未选定的AL偏压在0.5-0.7V,由此减少泄漏。 If you want the column read only a limited number of units, the unselected bias AL 0.5-0.7V, thereby reducing leakage.

[0062] 阵列中的个体闸流晶体管将由于泄漏电流而随着时间逐渐丢失其存储的数据。 [0062] The individual thyristor array will gradually lose its stored data over time due to leakage currents. 尽管该泄漏显著少于常规的一个晶体管一个电容器DRAM存储器单元中发生的泄漏,但为了克服泄漏电流,可以将阵列置于待用状态,从而保持存储的数据。 While leakage is significantly less than the leakage of a conventional DRAM memory cell transistor in a capacitor, but in order to overcome the leakage current, the array may be placed in an inactive state, thereby maintaining the stored data. 图14示出了施加于阳极和阴极线以保持闸流晶体管存储器单元阵列中存储的数据的电势。 FIG 14 illustrates potential applied to the anode and cathode lines thyristor to maintain data stored in the memory cell array of transistors. 在该状态中,所有阳极线保持在0.5-0.7伏,并且所有阴极线都接地。 In this state, all of the anode line is maintained at 0.5-0.7 volts, and all the cathode lines are grounded. 在该条件下,“关断”闸流晶体管不受影响,而“导通”闸流晶体管被连续充电到“导通”状态。 Under this condition, "off" thyristor unaffected, while the "on" the thyristor is continuously charged into the "on" state. 因为该待用状态连续消耗电力,所以在使闸流晶体管维持待用与允许放电并周期性刷新阵列之间存在折中。 Since the standby state power consumption continuously, so that the thyristor is maintained and allowed to be discharged and a standby periodic refresh tradeoff between arrays. 在我们优选的实施方式中,每秒钟将整个阵列刷新1到10次。 In our preferred embodiment, the entire array per second refresh 1-10 times. 这远比基于常规FET的DRAM要求的刷新频率低一一本发明的特别优点。 This requires DRAM refresh rate than on a conventional FET eleven particular advantage of the invention is low.

[0063] 图15A和15B示出了本发明的闸流晶体管存储器单元的另一实施例。 [0063] FIGS. 15A and 15B show a further thyristor of the memory cell according to the present embodiment of the invention. 在该实施例中,向结构的深沟槽增加侧壁NMOS栅极80。 In this embodiment, NMOS gate 80 to increase the sidewalls of the deep trench structure. 结构的其余区域与上文关于图4-8所述的相同。 The remaining areas of the structure above with respect to FIGS. 4-8 above. 增加栅极80的益处是增大写入速度并降低写入电压。 Increase the benefits of the gate 80 is to increase the write speed and reduce the writing voltage. 因为增加栅极增大了工艺复杂性,所以栅极的使用取决于存储器阵列所预期的特定应用。 Since increasing the gate increases the complexity of the process, the use of the gate depends on the particular application of the memory array contemplated.

[0064] 可以通过首先执行如上文关于图5所述的深硅蚀刻来在深沟槽中形成栅极80。 [0064] The deep trench may be formed in the deep silicon etching on the gate 80 in FIG. 5 by first performing above. 然后氧化沟槽的侧壁,由此形成栅极氧化物,其将栅电极与掺杂区域32、59和57隔离开。 Followed by oxidation of the trench sidewall, thereby forming a gate oxide, a gate electrode which doped regions 32,59 and 57 isolated. 然后例如通过化学气相沉积工艺利用二氧化硅对沟槽进行部分填充。 Then partially filling the trench using, for example, silicon dioxide by a chemical vapor deposition process. 然后跨所述结构沉积共形掺杂的多晶硅层。 Across the layer structure is then depositing a conformal polysilicon doped. 在各向异性蚀刻步骤去除了除图15A所示的之外的整个共形多晶硅层之后,执行另一个沟槽填充操作以完成沟槽填充。 In addition to the anisotropic etching step after the entire conformal polysilicon layers other than that shown in FIG. 15A, the trench filling operation to perform another complete trench fill. 然后例如使用化学机械抛光或其它技术来执行适当的平面化步骤。 Then performs appropriate steps such as planarization using chemical mechanical polishing or other techniques. 稍后在该过程中,制作电连接以将栅极80耦合,从而控制栅极线(GL) 〇 Later in the process, making the electrical connector 80 to couple the gate to control gate lines (GL) square

[0065] 图16是显示如上所述增加了栅极80的闸流晶体管存储器单元72的阵列的电路图。 [0065] FIG. 16 is a circuit diagram of the array increases thyristor gate 80 of memory cells 72 described above. 栅极80在被栅极线GL导通时短接NPN晶体管82,将PNP晶体管83的基极连接到阴极线KL。 The gate 80 when the gate line GL is turned on shorting NPN transistor 82, the base of the PNP transistor 83 is connected to the cathode line KL. 该方式具有上述优点一一降低写入电压并允许更快地写入数据。 This embodiment has the advantages described above eleven reduce writing voltage and allows faster writing of data.

[0066] 图17示出了在深沟槽中具有两个侧壁PMOS栅极86的垂直闸流晶体管单元的另一实施例。 [0066] FIG 17 shows another vertical thyristor unit having two side walls of the gate of the PMOS 86 in the deep trench embodiment. 通过和上文描述的栅极80—样的方式形成这些单元。 These units are formed by way of the gate 80 and sample described above. 掩埋栅极86可以连接在拾取区域处并耦合到栅极线(GL)。 Buried gate 86 may be connected at a pickup area and coupled to the gate line (GL). 以和上文描述的一样的方式形成这些栅极。 In the same manner as described above and the gate electrode is formed. 在深硅沟槽蚀刻步骤之后,形成沟槽栅极氧化物。 After the deep silicon trench etching step of forming a trench gate oxide. 然后用二氧化硅将沟槽部分填充到高于N-阴极/P-基极结的深度。 The trench is then partially filled with silica to a depth greater than the cathode N- / P- base junction. 然后形成例如掺杂多晶硅的共形导电栅极层。 Then formed, for example, a conformal conductive layer is doped polysilicon gate. 然后对栅极层进行各向异性蚀刻以形成完全覆盖N型基极的侧壁栅极。 The gate layer is then anisotropically etched to form sidewalls of the gate electrode completely covers the N-type base. 最后,利用二氧化硅填充沟槽,然后使用公知的技术对沟槽进行平面化。 Finally, the silicon dioxide filled trenches, then using well-known techniques to planarize the trench.

[0067] 图18是使用图17的PMOS栅极86的存储器阵列的电路图。 [0067] FIG. 18 is a circuit diagram of a memory array 86 of the PMOS gate 17 of FIG. 栅极86在被栅极线GL导通时短接PNP晶体管83,将NPN晶体管82的基极连接到阳极线AL。 The gate 86 is turned on when the gate line GL is shorted PNP transistor 83, the base of the NPN transistor 82 is connected to the anode line AL. 该方法与上文针对NMOS栅极所描述的具有相同的优点。 The above method has the same advantages as described for the NMOS gate.

[0068] 使用闸流晶体管阵列作为存储器单元的一个潜在问题是在存取操作期间需要较高的行电流来读取存储器单元。 [0068] Using thyristor array as a potential problem during a memory cell access operation is required to read a high row current memory cell. (这里使用“行”一词作为阳极的同义词,使用“列”作为阴极的同义词。也可以使用字线和位线。)为了减少对较高的行电流的需求,使用我们称为滚动字线的技术。 (As used herein, "row" as a synonym for the word anode, using synonyms "column" as the cathode may also use the word lines and bit lines.) In order to reduce the need for high current row, we use the scroll called wordline Technology. 结合图19对该方法进行描述。 19 in conjunction with the method described in FIG.

[0069] 图19A示出了存储器阵列中的闸流晶体管存储器单元的行。 [0069] FIG. 19A shows a thyristor row of memory cells in a memory array. 该行由被分成M组单元的N列存储器单元构成。 The row consists of N columns of memory cells are divided into M cell groups. 在该行的左端示出了一组4个单元。 At the left end of the line shows a group of four cells. 为一组使用4个单元仅仅是示例;在实际集成电路中,一组中将有远超过4个单元。 As a group using four cells are merely exemplary; in practice an integrated circuit, a group will be far more than four units. 为了存取单元,例如,为了从它们读取数据或向它们写入数据,向该组所有成员的列线施加电压VSelected。 To access unit, e.g., in order to read data from or write data to them which a voltage is applied to the set of all members VSelected column lines. 所有其它列线接收电势VHolcU其中VHold高于VSelected。 All other column lines receiving higher than the potential VHolcU wherein VHold VSelected. 结果,选定的组将具有电流: As a result, a current having a selected group:

[0070] I group selected=M*I Selected,其中I Selected是用于一个单元的电流。 [0070] I group selected = M * I Selected, wherein the current is I Selected for a cell.

[0071] 该行中其余的N/M-1组单元将具有电流: [0071] The rest of the row N / M-1 having a current set of cells:

[0072] I group hold= (N/M-1) *M*I hold,其中I Hold是用于一个单元的电流。 [0072] I group hold = (N / M-1) * M * I hold, where the current I Hold for one unit.

[0073] 在使用存储器阵列时,流程是向第一组施加用于期望操作的选定电势,同时将所有其余的组偏压到“hold”。 [0073] In use the memory array, the process operation is selected for a desired potential is applied to the first group, while the bias voltage to all remaining group "hold". 一旦完成了对第一组的期望操作,就将第一组上的偏压变成“hold”,并且将下一组上的偏压变成选定的电势,例如图19B所示。 Once complete the desired operation on the first group, a first set of bias will become "hold", and the next set of bias potential becomes selected, as shown in FIG 19B. 通过重复将字线上的除选定组之外的所有组的单元保持在“hold”电势的这些步骤并逐个组地重复这一操作,减小了行电流。 By repeating these steps for all the cell groups other than the selected word line is maintained in the group "hold" and the potential-by repeating this operation in groups reduces the line current. 我们称这种技术为“滚动”字线。 We call this technology "rolling" character line.

[0074] 对于具有高度非线性的电流和电压关系的存储器单元,用于单元的保持电流可以比选定单元的读取电流低几个数量级。 [0074] For the memory cell has a highly non-linear relationship between current and voltage, the current can be kept low for the read current of the selected cell is several orders of magnitude than the units. 例如,假设一行具有被分成8组的128列,每组具有16个单元。 For example, assume one row having 128 is divided into eight groups each having 16 cells. 在典型的实施方式中,选定电流将大约为1〇μΑ,而保持电流将大约为10pA,相差六个数量级。 In an exemplary embodiment, it will be approximately 1〇μΑ selected current, the current is maintained approximately 10pA, a difference of six orders of magnitude. 因此: therefore:

[0075] 在没有滚动的情况下:I row= 128*10uA= 1 · 28mA [0075] In the absence of scrolling: I row = 128 * 10uA = 1 · 28mA

[0076] 在滚动的情况下:I row= 16*10uA+(128-16) *10p A = 160uA [0076] In the case of rolling: I row = 16 * 10uA + (128-16) * 10p A = 160uA

[0077] 因而,通过上述方式滚动字线提供了字线电流的88%的减小,以及8次滚动存取以存取完整的行。 [0077] Accordingly, the above-described embodiment by providing a word line scroll 88% reduction in the word line current, and eight row access rolling accesses to complete.

[0078] 因为存储器阵列中“导通”的每个闸流晶体管单元将消耗一些电流,所以存储器阵列的电流消耗以及这种“导通”单元的数量取决于正被存储在阵列中的特定数据。 [0078] Since the memory array "on" for each thyristor unit will consume some of the current, the amount of current consumption of the memory array, and this "on" cell depends upon the particular data is being stored in an array . 这具有将功耗关联到存储器中存储的实际数据的不希望的效果。 This has the power stored in the memory associated with the actual data of the undesirable effects. 可以使用目标是将大约50%的单元保持为逻辑“Γ的数据编码来减小该待用电流。 The goal is to use about 50% of the holding means to reduce the standby current is a logic "Γ of data encoding.

[0079] 例如,考虑具有2个额外校验位的8位字。 [0079] For example, consider the two 8-bit words having the extra parity bits. 校验位=00 无变化校验位=01 反转低4位 No change in parity bit parity bit = 00 = 01 reverse low 4

[0080] 校验位=10 反转高4位校验位=11 反转所有位 [0080] The inverted parity bit 10 = High 11 = 4 parity bit inversion of all bits

[0081] 在以下示例中,校验位是数据的所存储的字前面的前两位且是斜体的。 [0081] In the following example, the parity bit in front of the first two words of stored data and italic.

[0082] 示例1:所有都是一:1111-1111变成10-0000-1111,因而8个一变成5个一。 [0082] Example 1: All are a: 1111-1111 into 10-0000-1111, thus becomes a 8 5 a.

[0083] 示例2:50%+1 个一:1010_1011 变成01_1010_0100,因而5个一变成4个一。 [0083] Example 2: 50% + a 1: 1010_1011 into 01_1010_0100, thus becomes a 4 5 a.

[0084] 示例3:50%为一:1010_1010变成00_1010_1010,因而4个一变成4个一。 [0084] Example 3: a 50%: 1010_1010 into 00_1010_1010, thus becomes a 4 a 4.

[0085] 示例4:50%-1 个一:0010_1010变成00_0100_1010,因而3个一变成3个一。 [0085] Example 4: a 50% -1: 0010_1010 into 00_0100_1010 therefore becomes a 3 3 a.

[0086] 示例5:所有都是零:0000_0000变成10_1111_0000,因而0个一变成5个一。 [0086] Example 5: all are zero: 0000_0000 into 10_1111_0000 thus becomes 0 a 5 a.

[0087] 示例6:5个一:0011_1011 变成11_1100_0100,因而5个一变成3个一。 [0087] Example 6: 5 a: 0011_1011 into 11_1100_0100 therefore becomes a 3 5 a.

[0088] 以上数据编码技术或其它类似方法在要将阵列待用电流维持在相对恒定水平的情况下是有用的,并用于电流源控制的待用操作。 In the case [0088] The above data encoding technique or other similar methods To be used in the current array is maintained at a relatively constant level is useful, and for standby operation controlled current source. 常规逻辑电路可以用于检测1的数量和位置,执行期望的反转(或不执行)并向存储的数据增加校验位。 Conventional inversion logic circuit may be used to detect the number and location 1 performs the desired (or not executed) to increase the parity data storage.

[0089] 在与图14相关联的实施例中,通过供应保持电压或电流将闸流晶体管存储器阵列中存储的数据维持在待用,从而不需要刷新。 [0089] In an embodiment associated with FIG. 14, the holding voltage or current supplied by the thyristor data stored in the memory array is maintained in the rest, so that no refreshing. 在这些待用状况下,保持“〇”数据的所有存储器单元传导非常低但有限的电流。 However, a limited current of all the memory cells under these conditions stand, kept "square" data is very low conductivity. 由于保持电流与保持电压之间的指数关系,有利的是使用电流源来在待用时使单元保持活动。 Since the holding and the holding current exponential relationship between the voltage, the current source is advantageous to use the cell to remain active during stand-by. 在我们更早的专利申请,例如,2015年1月6日提交的题为“Cross-Coupled Thyristor SRAM Circuits and Methods of Operation” 的美国专利申请14/590834中描述了一种方法,通过引用将该专利申请并入本文。 In our earlier patent application, for example, entitled January 6, 2015 filed "Cross-Coupled Thyristor SRAM Circuits and Methods of Operation" US patent application 14/590834 describes a method by reference patent application is incorporated herein by reference. 那里我们描述了使用恒流源将阵列偏压到最优保持电压来将数据保持维持在低待用电流的技术。 There we describe the use of a constant current source array to the optimum bias voltage to the data holding art low holding current is maintained in standby. 尽管结合SRAM存储器论述了这种方法,但其也可以用于其它基于闸流晶体管的易失性存储器,例如本文描述的那些。 Although it discussed in conjunction with this method of SRAM memory, but it can also be used on other volatile memory thyristor, for example those described herein.

[0090] 在上述偏压方案中,保持“0”数据的所有存储器单元传导非常低但有限的电流,以便维持阵列数据而无需刷新。 All the memory cells [0090] In the above biasing scheme, keeping the "0" data is very low but finite conductivity current, in order to maintain the data without refreshing the array. 替代方法是将提供的电流调节到更低值,该值不足以无限期地维持数据完整性,但足以在最小“保持”周期(例如Ims)内维持数据完整性。 An alternative is to provide a current adjusted to a lower value that is insufficient to maintain data integrity indefinitely, but sufficient minimum "hold" to maintain data integrity within a period (e.g. Ims). 该方法允许待用电流的显著减小。 The method allows significant reduction of the standby current. 然而,为了无限期地维持数据的完整性,逐个扇区地执行背景刷新操作,其中在短时间内将为扇区设定的保持电流增大到较高值,以将单元电平重新建立到更好的值,但然后减小回到正常待用电流。 However, in order to indefinitely maintain the integrity of the data sector by sector to perform the background refresh operation, wherein in a short time for the sector is set to maintain the current increases to a higher value, in order to re-establish cell level better values, but then decreases back to normal standby current. 这允许同时刷新扇区中的所有单元,而不是像当前利用常规DRAM所做的那样逐行刷新。 This allows the simultaneous refresh all of the cells in the sector, rather than the current use of conventional DRAM refresh done as progressive. 此外,刷新不会干扰正常读取/写入操作,使得刷新操作在外部不可见。 Further, the refresh does not interfere with the normal read / write operation, so the refresh operation is not externally visible. 在图20中示出了该方法。 In FIG 20 illustrates this method.

[0091] 该图示出了一个刷新脉冲能够如何刷新整个扇区。 [0091] This illustrates how a pulse refresh the entire sector can be refreshed. 在CMOS开关92导通时施加到线90的刷新脉冲将刷新存储器单元72的扇区。 When applied to the CMOS switch 92 is turned on to refresh pulse line 90 to refresh the memory cells 72 of the sector. 该示例示出了电流控制的待用/刷新,然而,可以将同一方法应用于电压控制的待用/刷新。 This example shows a current control standby / refresh, however, the same method can be applied to a voltage controlled standby / refresh.

[0092] 图21是示出用于从闸流晶体管阵列读取数据的一种技术的电路图。 [0092] FIG. 21 is a diagram illustrating a technique for reading data from the array circuit diagram of a thyristor. 感测放大器95具有连接到存储器阵列的一列存储器单元72的一个输入。 The sense amplifier 95 having an input connected to a memory array 72 of memory cells. 感测放大器95的另一输入连接到一列虚设存储器单元94。 The other input of the sense amplifier 95 is connected to a dummy memory cell 94. 存储器单元72和虚设单元94具有被预充电到0伏的列线。 Memory cells 72 and dummy cells 94 are precharged with 0 volts to the column lines. 在读取操作期间,如果单元为“〇”,编程的存储器单元72的状态将使列线的电势向上移动,或者如果单元为“1”,将使列线的电势接近0V。 During a read operation, if the cell potential state is "square", programmed memory cell column line 72 will cause the upward movement, or if the unit is "1", the potential of the column lines will be close to 0V. 虚设存储器单元的列线被电流源以选定阵列中的列为感测放大器95产生差分数据的速率的1/2的速率向上移动。 Rate dummy memory cell column lines are selected as a current source to the sense amplifier array 95 to produce difference data rate of 1/2 is moved upward. 如果选定的单元为“0”,则选定的列将提高到虚设列以上。 If the selected cell is "0", the selected column will increase to the dummy column. 如果选定的单元为“1”,则虚设列将提高到选定列以上。 If the selected cell is "1", the dummy columns will increase to the selected column. 然后可以将感测放大器输出解释为指示所存储的数据的“Γ或“〇”。 Then the sense amplifier output can be interpreted as "Gamma] or" square to the stored indication data. "

[0093] 已经出于例示和描述的目的给出了发明的该描述。 [0093] have been described for purposes of illustration and description is given of the invention. 它并非旨在进行穷举或将本发明限制于所描述的精确形式,并且根据以上教导,很多修改和变化都是可能的。 It is not intended to be exhaustive or to the precise form of the present invention be limited to the described and in accordance with the above teachings, many modifications and variations are possible. 选择并描述实施例是为了最好地解释发明的原理及其实际应用。 Example embodiments were chosen and described the principles and its practical application in order to best explain the invention. 该描述将使得本领域的技术人员能够最好地利用并实践各实施例中的发明以及适于特定用途的各种修改。 This description will enable others skilled in the art to best utilize and practice the various embodiments of the invention, various modifications and embodiments suited to the particular use. 本发明的范围由以下权利要求限定。 Scope of the invention defined by the following claims.

Claims (9)

  1. 1. 一种用于在易失性存储器阵列中控制功耗的方法,所述易失性存储器阵列具有阳极线、阴极线和垂直闸流晶体管存储器单元的阵列,所述垂直闸流晶体管存储器单元具有耦合到阳极线的阳极和耦合到阴极线的阴极,所述方法包括向数据的存储字增加校验位,以更密切地平衡导通的闸流晶体管存储器单元和关断的闸流晶体管存储器单元的数量。 1. A method for volatile memory array power consumption control, the volatile memory array having an anode wire, an array of cathode lines and vertical thyristor of the memory cell, the memory cell vertical thyristor line is coupled to the anode of an anode and a cathode coupled to said cathode lines with the method includes increasing the stored parity bit word data to more closely balance the thyristor is turned off and transistor memory cell of the memory thyristor number of cells.
  2. 2. 根据权利要求1所述的方法,其中,向数据的每个存储字增加两个校验位。 The method according to claim 1, wherein two additional parity bits to each data word stored.
  3. 3. 根据权利要求2所述的方法,其中,取决于所述两个校验位来不改变或改变所述存储字。 3. The method according to claim 2, wherein, depending on the two parity bits do not change or alter the memory word.
  4. 4. 根据权利要求3所述的方法,其中,所述两个校验位为所述存储字定义四种状态,所述四种状态包括: 不改变所述存储字; 反转所述存储字的前半段; 反转所述存储字的后半段;以及反转所述存储字的全部。 4. The method according to claim 3, wherein the two bits of the check word is stored is defined four states, the four states comprising: storing said word is not changed; inverting the stored word the first half; inverting the second half of the memory word; and inverting all of the memory word.
  5. 5. —种在存储器单元的交叉点阵列中存储数据的方法,在存储器单元的所述交叉点阵列中,每个存储器单元仅具有一个闸流晶体管,所述闸流晶体管连接在字线与位线之间,所述方法包括: 为所述阵列中存储的数据的每个字提供至少一个校验位; 接收数据字以存储在所述阵列中,所述字具有第一图案的位,位的值表示存储器单元的所述闸流晶体管是导通还是关断; 将所述至少一个检验位和数据字位编码成第二图案的位,所述第二图案的位处在具有受限数量的导通存储器单元的范围内;以及在所述阵列中存储经编码的图案的字和校验位; 由此,控制通过数据阵列的电流的量。 5. - kind of data stored in the cross point array of memory cells in the method, the cross-point array of memory cells, each memory cell has only one thyristor, said thyristor is connected to word lines and bit between lines, the method comprising: providing at least one parity bit for each data word stored in the array; receiving data words stored in the array, the word having a first bit pattern of bits value indicates the thyristor of the memory cell is turned on or off; the at least one data word and check bits into coded bits of the second bit pattern, the second pattern in a bit having a limited number of within the scope of the conductive memory cells; and the word and parity bit patterns stored encoded in the array; Accordingly, the amount of current controlled by the data array.
  6. 6. 根据权利要求5所述的方法,还包括: 从所述阵列检索所述经编码的图案;以及将所述经编码的数据字位和校验位解码回到所述第一图案的位。 6. The method as claimed in claim 5, further comprising: retrieving from the array through the encoding pattern; and a data word and check bits to decode the encoded bit back to the first pattern .
  7. 7. 根据权利要求5所述的方法,其中,编码步骤包括: 将所述至少一个校验位和所述数据字位编码成处在具有最小数量的导通存储器单元的范围内的第二图案的位,由此控制通过所述数据阵列的所述电流的量。 7. The method according to claim 5, wherein the encoding step comprising: the at least one check bit and the data word encoded into bit patterns in the second range has a minimum number of memory cells conducting bits, thereby controlling the amount of current through the data array.
  8. 8. 根据权利要求7所述的方法,其中,编码步骤包括:将所述至少一个校验位和所述数据字位编码成导通存储器单元的数量介于〇与50%之间的第二图案的位。 8. The method according to claim 7, wherein the encoding step comprising: the at least one check bit and the data word bits encoded into the number of memory cells conducting a second interposed between a square of 50% bit pattern.
  9. 9. 根据权利要求5所述的方法,其中,编码步骤包括:将所述至少一个校验位和所述数据字位编码成导通存储器单元的数量在大约50%的范围内的第二图案的位,以将通过所述数据阵列的所述电流的量维持在相对恒定的水平。 9. The method as claimed in claim 5, wherein the encoding step comprising: the at least one check bit and the data word bits encoded into the number of memory cells of the second conductive pattern in the range of about 50% the bits to be maintained at a relatively constant level by an amount of the current of the data array.
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