CN101110428A - Multi-layer insulator silicon material used for MEMS and method thereof - Google Patents

Multi-layer insulator silicon material used for MEMS and method thereof Download PDF

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Publication number
CN101110428A
CN101110428A CNA2007100436805A CN200710043680A CN101110428A CN 101110428 A CN101110428 A CN 101110428A CN A2007100436805 A CNA2007100436805 A CN A2007100436805A CN 200710043680 A CN200710043680 A CN 200710043680A CN 101110428 A CN101110428 A CN 101110428A
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China
Prior art keywords
soi
silicon
mems
buried
material
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CNA2007100436805A
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Chinese (zh)
Inventor
武爱民
陈静
孙佳胤
王曦
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中国科学院上海微系统与信息技术研究所
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Priority to CNA2007100436805A priority Critical patent/CN101110428A/en
Publication of CN101110428A publication Critical patent/CN101110428A/en

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Abstract

The present invention relates to a multilayer SOI material and production method belonging to the field of MEMS, which is characterized in that a multilayer complex substrate made from SOI material (Silicon-On-Insulator) or similar SOI material is adopted. In addition, silicon-silicon bonding or melting bonding, bonding grinding and polishing or intelligent peeling are utilized to obtain the multilayer SOI material provided with a crystalline silicon layer and an embedded insulating layer staggered towards each other. The material conveniently realizes specific production of complex MEMS element and accurately controls some characteristic sizes of elements, thus consummating application of SOI to MEMS. As for micromechanical processing microelectronic elements isolated with grooves, the material is an effective solution to realize single chip integration.

Description

Be used for silicon materials and method on the multilevel insulator of MEMS micromachined

Technical field

The present invention relates to a kind of multilayer SOI (silicon-on-insulator) material and method of the MEMS of being used for micromachined, belong to SOI material field.

Background technology

Because the limitation of body silicon materials self, SOI material have become the strongest candidate of MEMS field silicon materials and one of have substituted.In soi structure, isolated by insulating buried layer between monocrystalline silicon thin film and the monocrystalline substrate, the existence of buried regions embody plurality of advantages in the MEMS process application: as the etch stop layer in the anisotropic etching of silicon, silicon dioxide and silicon nitride can both extraordinary etch stops for KOH and Tetramethylammonium hydroxide (TMAH) corrosive liquid, comparing silicon chip with electrochemistry automatic stop corrosion does not need to be electrically connected, and can produce in batches; Silicon dioxide can be used as sacrifice layer when carrying out surface micromachined; Have silicon dioxide to be used for doing dielectric insulation, therefore this wafer leakage current is low, at high temperature uses to reach 400 ℃.The top layer silicon of SOI has the monocrystalline quality, has excellent mechanical property such as yield strength height, residual stress is little and fatigue resistance is good etc.The micro mechanical system that the SOI disk prepares also is very beneficial for realizing with cmos circuit integrated, and this is the most important developing direction of MEMS, also is the reason that high performance in recent years SOI base MEMS is subjected to increasing concern and research.From the angle of whole system, the technology stability that the SOI material is brought also is that the body silicon materials are incomparable, therefore adopts the MEMS product yields of SOI wafer preparation also can increase significantly than the like product on the body silicon.

However, in many applications, the many advantages in MEMS of SOI still can not obtain embodying and performance completely.Purpose of the present invention is exactly to propose a kind of many buried regions SOI material that the MEMS device is realized that more helps.

Summary of the invention

The object of the present invention is to provide a kind of the present invention to be used for the multilayer SOI material and the method for MEMS micromachined, can the multilayer SOI backing material of MEMS labyrinth and device fabrication will be advantageously used in, on one-piece substrate, fully play conventional monolayers SOI and be used for the various advantages of MEMS, reach the yields that improves the MEMS device, expand the purpose of the range of application of SOI-MEMS.

The multilayer SOI material that is used for the MEMS device involved in the present invention, comprise two-layer, three layers or multilayer insulation medium, monocrystalline silicon by different layers that these dielectrics are kept apart, in the structure of MEMS device, play different effects, and different dielectrics also can play different functions when the device fabrication process is worked with device, as as electric isolation layer, etch stop layer or sacrifice layer, thereby it is more convenient that some specific MEMS structures and device are implemented, and reliability and long-time stability also are improved.Multilayer soi structure involved in the present invention is characterized in that: have the SOI material of three buried structures of the SOI material of the folded mutually double-buried structure that distributes of monocrystalline silicon-insulating buried layer-monocrystalline silicon-insulating buried layer-monocrystalline silicon or monocrystalline silicon-insulating buried layer-monocrystalline silicon-insulating buried layer-monocrystalline silicon-insulating buried layer-monocrystalline silicon and the composite construction of more superimposed layers.Described insulating buried layer comprises the compound buried regions of silicon dioxide, silicon nitride or silicon dioxide and silicon nitride, and all buried regions are the combination of commaterial or various materials in the whole composite material.The silicon dioxide that is used for buried regions comprise adopt SIMOX (annotating oxygen isolates) or thermal oxidation that form with the silicon dioxide growth of CVD method; Silicon nitride is by the preparation of CVD method, and compound buried regions is the combination of the medium of above the whole bag of tricks formation, can recently adjust the residual stress of the stress minimizing sandwich construction of whole wafer by the method for regulating both thickness ratios that make up; The thickness of each buried regions all between 0.2 μ m-10 μ m, when satisfying the MEMS device fabrication as the thickness requirement of dielectric isolation or sacrifice layer.The monocrystalline silicon layer thickness of top layer and mid portion is between 1um-100um, being that device layer is realized all kinds of MEMS structure needs at top layer easily; And also can carry out P type or N type as required in the material preparation process mixes.

Preparation methods proposed by the invention:

SOI material for the double-buried structure shown in (Fig. 1):

1, adopt the SOI disk and the monocrystalline silicon piece of twin polishing, the buried regions oxide layer of all growing on the top layer of SOI or silicon chip surface or above two surfaces, described buried regions oxide layer is silicon dioxide, silicon nitride or both combinations; CVD method grown silicon nitride is adopted on a surface therein as required;

2, through after the semiconductor standard cleaning, adopt Ar plasma bombardment 5~120 seconds to increase surface activity, by silicon-Si direct bonding under the normal temperature vacuum state or fusion bonding, bonding face is the surface of top layer silicon face and the silicon chip somatomedin of SOI, the temperature range of fusion bonding is at 200~500 ℃, pressure limit 1bar-50bar, bonding is after the 900-1100 more than 2 hours ℃ high-temperature annealing process, obtains the double-deck soi structure of desired thickness and roughness then by grinding and chemico-mechanical polishing or smart peeling.

SOI material for three buried structures shown in (Fig. 2):

1, adopt the SOI disk of twin polishing, the top layer of a slice SOI or two interfaces oxide layer of all growing therein, described buried regions oxide layer is silicon dioxide, silicon nitride or both combinations; Adopt CVD method grown silicon nitride in a surface therein according to concrete needs.

2, through after the semiconductor standard processes cleaning, adopt the Ar plasma bombardment to increase surface activity in 5~120 seconds, by Si-Si direct bonding under the normal temperature vacuum state or fusion bonding, the bonding contact-making surface is the top layer silicon face of two SOI.The temperature range of fusion bonding is at 200~500 ℃, and pressure limit 1bar-50bar, bonding be after the 900-1100 more than 2 hours ℃ high-temperature annealing process, then by grinding and three layers of soi structure of chemico-mechanical polishing acquisition desired thickness and roughness.

Silicon dioxide and silicon nitride can obtain combination as etch stop layer or as the effect of sacrifice layer and electric isolation layer in the MEMS course of processing of multilayer SOI material in silicon anisotropic etching and deep reactive ion bundle etching, thereby avoided the limitation of conventional monolayers SOI material in MEMS uses.For example in the application of pressure sensor, the insulating buried layer of individual layer SOI material can be used as pressure drag and reads the electric isolation in the mechanism or obtain level and smooth, thickness stress film accurately as etch stop layer, but both but can not take into account, and multilayer SOI material has then well solved this contradiction.Silicon nitride is used to regulate stress and can brings into play better heat conductivility as the part of insulating buried layer or insulating buried layer.It is integrated that this material can also be used for the monolithic of the IC circuit of trench isolations and MEMS element, and this also is the most important developing direction of MEMS.Core process that preparation method in the present invention is related such as Si-Si bonding and chemico-mechanical polishing all are relatively ripe technology, are to realize easily.

Description of drawings

Fig. 1 is the end view of the SOI material of double-deck buried structure among the present invention,

Fig. 2 is the end view of the SOI material of three buried structures among the present invention,

Fig. 3 is the preparation process of the SOI material of double-buried structure shown in Figure 1, (a) treat the monocrystalline silicon piece and the SOI sheet of bonding, (b) SOI sheet and the silicon chip after the oxidation, (c) bonding and high temperature are reinforced (dotted portion is the foaming position when adopting smart peeling), (d) polish and polish;

Fig. 4 is the preparation process of the SOI material of three buried structures shown in Figure 2, (a) treats the SOI sheet of bonding, (b) the SOI sheet after the oxidation, and (c) bonding and high temperature are reinforced, and (d) polish and polish;

Among the figure: 1 monocrystalline silicon, the composite bed of 2 silicon dioxide, silicon nitride or silicon dioxide and silicon nitride, 3 treat the SOI picture of the twin polishing of bonding

Embodiment

Be used among the present invention the MEMS micromachined double-deck SOI material and the concrete preparation process of three layers of SOI material for example, the description by embodiment will further will help to understand the present invention, but not limit content of the present invention.

Embodiment 1

For double-deck SOI material, shown in Fig. 3 (a), adopt the SOI disk and the monocrystalline silicon piece of twin polishing, in top layer and the silicon chip surface growth oxide layer of SOI, as Fig. 3 (b).After semiconductor RCA standard cleaning, after adopting the Ar plasma bombardment to increase surface activity in 5~120 seconds, by fusion bonding under the vacuum state, bonding face is top layer silicon face and the silicon chip lower surface of SOI, the temperature of fusion bonding is got 500 degree, pressure limit 10bar, bonding after 2 hours 1100 the degree high-temperature annealing process, bonding process is as shown in Fig. 3 (c).Last shown in Fig. 3 (d), by the double-deck soi structure of grinding and chemico-mechanical polishing acquisition desired thickness and roughness.

Embodiment 2

For three layers of SOI material, shown in Fig. 4 (a), adopt the SOI disk of two twin polishings, in the superficial growth oxide layer of SOI, as Fig. 4 (b).After semiconductor RCA standard cleaning, after adopting the Ar plasma bombardment to increase surface activity in 5~120 seconds, by fusion bonding under the vacuum state, bonding face is the top layer silicon face of two SOI, the temperature of fusion bonding is got 500 degree, pressure limit 10bar, bonding after 2 hours 1100 the degree high-temperature annealing process, bonding process is as shown in Fig. 4 (c).Last shown in Fig. 2 or Fig. 4 (d), by three layers of soi structure of grinding and chemico-mechanical polishing acquisition desired thickness and roughness.

Claims (10)

1. multilayer SOI material that is used for the MEMS micromachined, it is characterized in that described SOI material has monocrystalline silicon-insulating buried layer-monocrystalline silicon-insulating buried layer-monocrystalline silicon SOI material of the folded double-buried structure that distributes mutually, or the SOI material of three buried structures of monocrystalline silicon-insulating buried layer-monocrystalline silicon-insulating buried layer-monocrystalline silicon-insulating buried layer-monocrystalline silicon, or the composite construction of more superimposed layers.
2. by the described multilayer SOI material that is used for the MEMS micromachined of claim 1, it is characterized in that described insulating buried layer is the compound of silicon dioxide, silicon nitride or silicon dioxide and silicon nitride.
3. by claim 1 or the 2 described multilayer SOI materials that are used for the MEMS micromachined, it is characterized in that all insulating buried layer materials in the multilayer SOI material are the combination of commaterial or several different buried regions material.
4. by the described multilayer SOI material that is used for the MEMS micromachined of claim 2, it is characterized in that insulating buried layer is the compound tense of silicon dioxide and silicon nitride, the method of the ratio of silicon nitride and silicon dioxide thickness in the adjusting insulating buried layer, the residual stress of minimizing sandwich construction.
5. by claim 1 or the 2 described multilayer SOI materials that are used for the MEMS micromachined, the monocrystalline silicon thickness that it is characterized in that top layer and mid portion is 1 μ m-100 μ m; The thickness of described each insulating buried layer is 0.2 μ m-10 μ m.
6. by the described multilayer SOI material that is used for the MEMS micromachined of claim 3, the thickness that it is characterized in that described each insulating buried layer is 0.2 μ m-10 μ m.
7. prepare the multilayer SOI material of the MEMS of being used for micromachined as claimed in claim 1 or 2, it is characterized in that
(A) processing step of the SOI material of double-buried structure is:
(1) the SOI disk and the monocrystalline silicon piece of employing twin polishing, at top layer or the monocrystalline silicon sheet surface of SOI, perhaps described two superficial growth buried regions oxide layers, described buried regions oxide layer are silicon nitride, silicon dioxide or both combinations;
(2) through after the semiconductor standard cleaning, adopt the Ar plasma bombardment to increase surface activity in 5~120 seconds, silicon-Si direct bonding or fusion bonding under the normal temperature vacuum state, bonding face is the surface of top layer silicon face and the silicon chip somatomedin of SOI, the temperature range of fusion bonding is at 200~500 ℃, pressure limit 1bar-50bar, bonding is after the 900-1100 more than 2 hours ℃ high-temperature annealing process, obtains the double-deck soi structure of desired thickness and roughness at last by grinding and chemico-mechanical polishing or smart peeling.
(B) step of the SOI material of three buried structures is:
(1) adopt the SOI disk of twin polishing, the top layer of a slice SOI or two interface growth buried regions oxide layers therein, described buried regions oxide layer is silicon nitride, silicon dioxide or both combinations;
(2) through after the semiconductor standard processes cleaning, adopt the Ar plasma bombardment to increase surface activity in 5~120 seconds, silicon-Si direct bonding or fusion bonding under the normal temperature vacuum state, bonding contact-making surface are the top layer silicon face of two SOI.The temperature range of fusion bonding is at 200~500 ℃, pressure limit 1bar-50bar, bonding is after the 900-1100 more than 2 hours ℃ high-temperature annealing process passes through the soi structure that grinding and chemico-mechanical polishing obtain three buried structures of desired thickness and roughness then.
8. by the described multilayer SOI preparation methods that is used for the MEMS micromachined of claim 8, it is characterized in that adopting the isolation of notes oxygen, thermal oxidation or the growth of CVD method as the silicon dioxide of buried regions oxide layer; Silica is then grown by the CVD method; Compound buried regions then is the combination of media that described method forms.
9. by the described multilayer SOI preparation methods that is used for the MEMS micromachined of claim 8, it is characterized in that in the SOI material that generates two buried regions or three buried structures, on the SOI of twin polishing disk or monocrystalline silicon piece, adopting CVD method grown silicon nitride.
10. by claim 1 or the 2 described application that are used for the multilayer SOI material of MEMS micromachined, it is characterized in that in pressure sensor it is integrated that an insulating silicon nitride buried regions or an insulating buried layer part are used to the monolithic of the IC circuit regulating stress or be used for trench isolations and MEMS element.
CNA2007100436805A 2007-07-11 2007-07-11 Multi-layer insulator silicon material used for MEMS and method thereof CN101110428A (en)

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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100595928C (en) * 2007-12-28 2010-03-24 上海新傲科技股份有限公司 Semiconductor substrate, preparing technique and application in advanced three-dimensional electronic packaging
CN102097328A (en) * 2010-12-20 2011-06-15 北京自动测试技术研究所 Method for manufacturing high-power field effect transistor
CN102442631A (en) * 2010-10-08 2012-05-09 探微科技股份有限公司 Micro-electromechanical device and composite base material used in one micro-electromechanical device
CN101853864B (en) * 2009-03-31 2012-07-04 台湾积体电路制造股份有限公司 Method of wafer bonding
CN102656110A (en) * 2009-07-03 2012-09-05 法国原子能与替代能委员会 Simplified copper-copper bonding
CN103295878A (en) * 2012-02-27 2013-09-11 中芯国际集成电路制造(上海)有限公司 Manufacturing method of multilayer nanowire structure
CN104925748A (en) * 2014-03-19 2015-09-23 中芯国际集成电路制造(上海)有限公司 Method for strengthening bonding strength between wafers
CN106409649A (en) * 2015-07-30 2017-02-15 沈阳硅基科技有限公司 Multilayer SOI material and preparation method thereof
CN108807229A (en) * 2018-06-08 2018-11-13 武汉新芯集成电路制造有限公司 A kind of monitoring method of bonding machine platform

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100595928C (en) * 2007-12-28 2010-03-24 上海新傲科技股份有限公司 Semiconductor substrate, preparing technique and application in advanced three-dimensional electronic packaging
CN101853864B (en) * 2009-03-31 2012-07-04 台湾积体电路制造股份有限公司 Method of wafer bonding
CN102656110B (en) * 2009-07-03 2015-11-25 法国原子能与替代能委员会 Simplify copper-copper bond
CN102656110A (en) * 2009-07-03 2012-09-05 法国原子能与替代能委员会 Simplified copper-copper bonding
CN102442631A (en) * 2010-10-08 2012-05-09 探微科技股份有限公司 Micro-electromechanical device and composite base material used in one micro-electromechanical device
CN102097328A (en) * 2010-12-20 2011-06-15 北京自动测试技术研究所 Method for manufacturing high-power field effect transistor
CN103295878A (en) * 2012-02-27 2013-09-11 中芯国际集成电路制造(上海)有限公司 Manufacturing method of multilayer nanowire structure
CN103295878B (en) * 2012-02-27 2016-05-25 中芯国际集成电路制造(上海)有限公司 A kind of manufacture method of multi-layer nano line structure
CN104925748A (en) * 2014-03-19 2015-09-23 中芯国际集成电路制造(上海)有限公司 Method for strengthening bonding strength between wafers
CN104925748B (en) * 2014-03-19 2017-06-13 中芯国际集成电路制造(上海)有限公司 A kind of method of bond strength between raising wafer
CN106409649A (en) * 2015-07-30 2017-02-15 沈阳硅基科技有限公司 Multilayer SOI material and preparation method thereof
CN106409649B (en) * 2015-07-30 2019-03-15 沈阳硅基科技有限公司 A kind of multilayer SOI material and preparation method thereof
CN108807229A (en) * 2018-06-08 2018-11-13 武汉新芯集成电路制造有限公司 A kind of monitoring method of bonding machine platform

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