CN101097900A - Conducting wire frame and method for producing same - Google Patents
Conducting wire frame and method for producing same Download PDFInfo
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- CN101097900A CN101097900A CN 200610093539 CN200610093539A CN101097900A CN 101097900 A CN101097900 A CN 101097900A CN 200610093539 CN200610093539 CN 200610093539 CN 200610093539 A CN200610093539 A CN 200610093539A CN 101097900 A CN101097900 A CN 101097900A
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- groove
- metallic plate
- lead frame
- manufacture
- wire holder
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
Abstract
The invention discloses a wire support and a relative production, wherein The invention processes local two faces of a metal board into dense and accurately aligned wire distances, while the local single face is processed into patterned grooves, to be filled with insulation material or the materials with different conductivities, therefore, the metal board is divided into a plurality of conductive areas or special electric areas, with additional support strengthen of metal circuit board. The invention can improve the production limit of prior wire support, with better heat radiation and high variation of pin number.
Description
Technical field
The invention relates to a kind of lead frame manufacturing technology, particularly can have a plurality of conductive regions or special electrical areas and lead frame of metallic plate circuit extra support intensity and preparation method thereof is provided about a kind of.
Background technology
The purpose of Electronic Packaging is mainly the transfer circuit signal, transmits electric energy, heat radiation approach and structural defence and support etc. is provided.In the packaging technology of carrying out semiconductor rear section, lead frame (Lead frame) and semiconductor carrier plate (IC substrate) are the bridges that is connected with external circuit as integrated circuit (IC) chip, to be used for transmitting the chip internal electronic signal to the external system plate.
Yet, along with the chip circuit functional promotion, cause the input and output contact of chip also significantly to increase, the lead frame of carries chips only can utilize four limits to do pin, and enough pins can't be provided; And lead frame can only link to each other and simple circuit; And another kind utilizes the support plate of a printed circuit board (PCB) (PCB) as carries chips, and be aided with its bottom and be the mode that tin ball that array arranges replaces tradition to do pin around with conductive metal frames and be suggested, the benefit of this encapsulation technology is under the same size area, it is many that number of pins can become, and its package dimension dwindles many.Yet under the more and more big result of the consumed power of this potted element, cause the heat dissipation problem of potted element to become the difficult problem that can't overcome.
But along with line design has been simplified in the integration (SOC) of chip functions, the encapsulation of number of C SP size turns to uses lead frame to reach the demand of heat radiation; Also bred simultaneously the demand of line design complexity between between CSP and lead frame, for example the lifting of QFN encapsulating products demand promptly is a tangible example.But the demand of non-symmetrical line transfers to conventional wires frame production method and is not easy up and down, has 1) etch partially (Half etching) circuit and make to be difficult for; 2) cause the circuit distortion during encapsulating (molding) easily; And 3) problem of the excessive glue pollution pin during encapsulating such as is difficult for overcoming at problem.So, the present invention is directed to that above-mentioned problem proposes a kind of new lead frame and manufacture method solves above-mentioned problem.
Summary of the invention
The present invention discloses a kind of lead frame and manufacture method thereof, it is with the local two-sided line pitch that is processed to form closeer and accurate contraposition simultaneously of metallic plate, local single-sided process forms patterned groove on metallic plate, and insert the material of insulating material or different conductivity, make this metallic plate isolated for a plurality of conductive regions or special electrical areas and provide the metallic plate circuit extra support strength.The present invention improves the making of known lead frame restriction, and has excellent in heat dissipation effect and the many advantages of high number of pins variability are arranged.
Main purpose of the present invention, be to provide a kind of manufacture method of lead frame, it is to utilize two-sided while etching or machining to control the mode that moulding runs through or casts deeply, make finer and closely woven line pitch part and accurately contraposition, and cooperate the etched mode of local single face to produce groove, in groove/groove, fill filler then to be supported, finish the circuit of groove another side again, with the problem of effective solution known lead frame making, encapsulation.
Another object of the present invention is to provide a kind of manufacture method of lead frame, and it is to utilize the making of packing material and supporting construction to make the circuit variation, and applicable to various semiconductor packages demands.
Another purpose of the present invention, be to provide a kind of manufacture method of lead frame, it is directly to produce the cylindrical conductor that upper and lower surface is connected, and wherein be packed to packing material at pattern and support, and need not need utilize boring and plated through hole technology as the conducting of printed circuit board (PCB), dwindle the support plate size so can save the trouble of coiling, or bigger utilized area can be provided under same size, pin be not limited to lead frame around, the lead frame of the LGA that can say so (Land grid array).
One embodiment of the invention are for being formed with patterning groove that runs through and the groove design that does not run through on a metallic plate; And be packed to packing material in patterning groove or groove, to form a lead frame with a plurality of conductive regions.
Another embodiment of the present invention is the manufacture method of lead frame, and it provides a metallic plate; Metallic plate is carried out etching, machining control moulding or forging type deeply, to form a plurality of grooves and following/upper groove; Selectivity filling filler in groove and following/upper groove; On the metallic plate upper and lower surface, form a plurality of conductive layers; Subsequently metallic plate is carried out etching, machining and controls moulding or forging type deeply, with form at the metallic plate upper surface a plurality of on/low groove, finish the making of circuit.
The present invention also provides the manufacture method of another kind of lead frame to be: a metallic plate is provided; This metallic plate is carried out etching, machining controls moulding or forging type deeply, with form a plurality of grooves with down/upper groove, and these grooves with down/upper groove in selectivity filling filler; Then again this metallic plate being carried out etching, machining controls moulding or forging type deeply, with form in this metallic upper surface a plurality of grooves with on/low groove, and these grooves with on/select the filling filler or do not clog filler in the low groove; And, finish the making of circuit at a plurality of conductive layers of the upper and lower surface formation of this metallic plate.
Beneficial effect of the present invention is:
One, can utilize the making of filler material and supporting construction to make the circuit variation, and can be widely used in various semiconductor packages demands.
Two, can be pre-formed a plurality of Metal Ball to reduce the scrappage and the cost of encapsulation, improve the reliability of potted element.
Three, because of all with filler it being filled between each pin, thus the excessive glue that is produced can avoid fully using the conventional wires frame to be encapsulated in encapsulating the time to the problem of last tin face (SMT Pad), can reduce encapsulation technology, improve acceptance rate and reduce cost.
Four, can be formed with the lead frame of a storage tank to reduce overall packaging height.
For making the auditor further understanding and understanding more be arranged to architectural feature of the present invention and the effect reached, careful with preferred embodiment, accompanying drawing and cooperate detailed explanation, illustrate as after.
Description of drawings
Figure 1A to Fig. 1 J2 is each step structure cutaway view of one embodiment of the invention.
Fig. 2 A to Fig. 2 C2 is each step structure cutaway view of another embodiment of the present invention.
Fig. 3 is the patterning resist layer pattern schematic diagram of the metallic plate upper surface of Figure 1B.
Fig. 4 is the patterning resist layer pattern schematic diagram of the metallic plate lower surface of Figure 1B.
Fig. 5 A to Fig. 5 F4 is each step structure cutaway view of another embodiment of the present invention.
Fig. 6 is incorporated into the formation step of storage tank for the present invention the schematic diagram of upper groove etching step.
Fig. 7 A and Fig. 7 B form a plurality of Metal Ball, with the embodiment schematic diagram as the interface that externally connects.
Figure number is to as directed:
10 metallic plates, 12 patterning resist layers
14 patterning resist layers, 16 grooves
18 low grooves, 20 fillers
22 patterning resist layers, 24 patterning resist layers
26 upper grooves, 28 fillers
The anti-coating of anti-coating 32 patternings of 30 patternings
The anti-coating of 34 conductive layers, 36 patternings
The anti-coating 42 patterning resist layers of 38 patternings
44 patterning resist layers, 48 chips
50 leads, 52 packing colloids
54 storage tanks, 56 Metal Ball
Embodiment
The present invention is a kind of lead frame and manufacture method thereof, it is to utilize selective etch, control forming technique or forging type, two-sided etching technique collocation filler filling technique deeply and produce a metallic plate lead frame as semiconductor carrier plate, make it simultaneously with excellent in heat dissipation effect and applicable to the semiconductor packages of high number of pins, existing lead frame is made and the problem of encapsulation to overcome.
In this explanation earlier, the present invention utilizes groove, upper groove, low groove and filling technique to form conductive metal frames, therefore can not limit to the present invention with the process point difference that groove, upper groove, low groove form.And below be to be example earlier to form groove and low groove, steps flow chart of the present invention is described.
At first, see also Figure 1A, be formed with a patterning resist layer 12 and a patterning resist layer 14 on the upper and lower surface of a metallic plate 10 respectively, and the pattern of patterning resist layer 12 sees also shown in Figure 3ly, and that the pattern of patterning resist layer 14 sees also is shown in Figure 4.
Be mask with patterning resist layer 12 with patterning resist layer 14 simultaneously again, metallic plate 10 is carried out etching, to form the groove 16 and low groove 18 shown in Figure 1B, this etched mode can adopt the Wet-type etching mode, mainly be because the Wet-type etching solvent after stinging erosion metal support plate 10 and penetrating, easily forms more straight sidewall, and helps to form finer and closely woven circuit pack, and can obtain accurate contraposition, subsequently and remove patterning resist layer 12,14.The formation of groove or low groove also can be through repeatedly selective etch, repeatedly dark control moulding or the mode of casting make.In a word, the formation method of this groove or groove can be selected from repeatedly Wet-type etching, dry-etching, casting or the dark control of process molding mode.
Continue, carry out fill process, filling supporter or filler 20 in above-mentioned groove 16 and low groove 18, and carry out filler 20 planarizations through a grinding steps, filler 20 can not covered to make on the metallic plate 10 circuit or cover the part of conductive layer, so promptly form the fine and closely woven circuit pack and the circuit pack of lower surface, shown in Fig. 1 C.Wherein, the material of filler 20 can be all obstructs such as resin, elargol, copper glue, carbon ink or changes electrical material.And at this metal sheet surface or be positioned at and also can select to form or not form the mask layer of taking precautions against drought above this packing material.
Then, see also shown in Fig. 1 D, respectively form a patterning resist layer 22 and a patterning resist layer 24 on metallic plate 10 upper and lower surfaces, continuing with patterning resist layer 22,24 is that mask carries out etching to metallic plate 10, on metallic plate 10, to form a plurality of upper grooves 26, remove patterning resist layer 22,24 subsequently, form shown in Fig. 1 E, and this etched mode can or be controlled moulding deeply by the selective etch mode and completes.
In above-mentioned a plurality of upper grooves 26, select whether to select to clog supporter or filler 28 subsequently, and behind filling supporter or filler 28, carry out the filler planarization, to form the circuit of upper surface, shown in Fig. 1 F1 or Fig. 1 F2 through a grinding steps.
Continue, respectively form anti-coating 30,32 of a patterning or welding resisting layer on metallic plate 10 upper and lower surfaces, shown in Fig. 1 G1 or Fig. 1 G2.Anti-coating 30,32 of this patterning or welding resisting layer are to define a plurality of positions to outer conducting layer.With anti-coating 30,32 of this patterning or welding resisting layer is mask, form on the upper and lower surface of metallic plate 10 a plurality of in order to the conductivity that increases conductive region to outer conducting layer 34, remove the anti-coating 30,32 of patterning subsequently, or welding resisting layer does not remove the structure of formation shown in Fig. 1 H1 or Fig. 1 H2.Wherein this conductive layer is the various Treatment of Metal Surface that are selected from electro-less plating Sn, electrotinning, electroless deposition of silver, electrosilvering, electronickelling gold, electroless nickel plating porpezite and ENIG or the like.
After the making of finishing lead frame; can carry out the step that chip 48 is installed; be as the chip presumptive area is installed in the present embodiment with metallic plate 10 central authorities; and by lead 50 with chip 48 and as external conductive junction point outer conducting layer 34 is connected; cover the upper surface of metallic plate 10 at last with a packing colloid 52; to envelope this chip 48 and lead 50; this packing colloid 52 is generally epoxy resin (epoxy resin); using provides a mechanical protective effect; avoid being subjected to the external force infringement, form the structure shown in Fig. 1 I1 and Fig. 1 I2.In addition, can be formed with a storage tank 54 earlier to reduce overall packaging height, carry out steps such as chip 48 installations subsequently again, to form the structure shown in Fig. 1 J1 and Fig. 1 J2 in metallic plate 10 central authorities.
And in the aforesaid groove that carries out metallic plate 10 16 and low groove 18, clog the processing step of supporter or filler 20, also can be according to each zone on the metallic plate to electrical demand, selection is packed to or is not packed to supporter or filler 20, see also Fig. 2 A, it is a groove 16 and the part low groove 18 interior embodiment schematic diagrames that do not have filling supporter or filler 20.It forms a plurality of upper grooves 26 as utilizing with aforesaid step subsequently on metallic plate 10, and the upper groove of selecting to insert filling supporter or filler 28 26 is inserted supporter or filler 28, carry out the filler planarization, to form the upper surface circuit shown in Fig. 2 B.Subsequently, form a plurality ofly on the upper and lower surface of metallic plate 10, and carry out chip 48 step with packing colloid 52 is installed, form the structure shown in Fig. 2 C1 or Fig. 2 C2 outer conducting layer 34.
Except the above embodiments, the present invention also enumerates another kind of embodiment, this embodiment be form earlier/upper groove or groove after, after groove or groove filling filler and planarization, form a plurality of conductive layers in the upper and lower surperficial specific region of metallic plate again, subsequently, form again/low groove and circuit.
At this is to lift one to form low groove or groove earlier, and the embodiment that clogs filler, formation conductive layer, upper groove more in regular turn describes.At first please refer to the step shown in aforementioned Figure 1A to Fig. 1 C, so that form the low groove 18 and groove 16 that has been filled with filler, shown in Fig. 5 A.
Continue, see also Fig. 5 B, respectively form the anti-coating 36,38 of a patterning on the upper and lower surface of metallic plate 10, the anti-coating the 36, the 38th of this patterning defines a plurality of positions to outer conducting layer.Continue, with the anti-coating 36,38 of this patterning is mask, form on the upper and lower surface of metallic plate 10 a plurality of in order to the conductivity that increases conductive region to outer conducting layer 34, wherein this conductive layer 34 is the various Treatment of Metal Surface that are selected from electro-less plating Sn, electrotinning, electroless deposition of silver, electrosilvering, electronickelling gold, electroless nickel plating porpezite and ENIG or the like, remove the anti-coating 36,38 of patterning subsequently, shown in Fig. 5 C.
Form a patterning resist layer 42,44 respectively on the upper and lower surface of metallic plate 10, to define the position of upper groove, continue, with patterning resist layer 42,44 and to outer conducting layer 34 is mask, metallic plate 10 is carried out etching, to form the upper groove 26 shown in Fig. 5 D, subsequently, patterning resist layer 42,44 is removed, continue, selectivity is carried out fill process, filling supporter or filler 28 in above-mentioned upper groove 26, to obtain a lead frame in conjunction with the technology and the advantage of known lead frame and printed circuit board (PCB), shown in Fig. 5 E1 or Fig. 5 E2.
Carry out chip 48, lead 50 installings and packing colloid 52 subsequently, to form as Fig. 5 F1, Fig. 5 F2, perhaps carry out storage tank 54 etchings earlier, carry out chip 48, lead 50 installings and packing colloid 52 again, have Fig. 5 F3 of chip 48 storage tanks 54 and the structure shown in Fig. 5 F4 with formation.
In addition, the formation step of storage tank 54 also can be incorporated in the formation step of upper groove 26, its processing step will become on metallic plate 10, lower surface forms a patterning resist layer 42 respectively, 44, to define the position of upper groove 26 and storage tank 54, continue, with patterning resist layer 42,44 be mask to outer conducting layer 34, metallic plate 10 is carried out etching, to form upper groove 26 and storage tank 54 as shown in Figure 6, subsequently, with patterning resist layer 42,44 remove, continue, selectivity is carried out steps such as fill process and chip installation, because of subsequent process steps with previous described identical, no longer give unnecessary details at this.
See also Fig. 7 A and Fig. 7 B, it is an another embodiment of the present invention, these embodiment are in the manufacturing process of this lead frame, as when selecting a plurality of low grooves not fill filler, form a plurality of Metal Ball 56 (metal bump) to replace traditional tin ball (solder ball), interface as external connection, the reliability problem that is produced when reducing different metal interface phase gluing, can increase the reliability of integral member, and plant the technology of tin ball because of minimizing, can reduce overall package technology scrappage and cost.
In sum, the present invention is a kind of lead frame and manufacture method thereof, it is to utilize a pair of facet etch technology to come to form the circuit pack of comparatively dense on metallic plate, and cooperates repeatedly etching, controls the problem that moulding and filler filling technology are made, encapsulated with effective solution known lead frame deeply.
The present invention can summarize following several advantages:
One, can utilize the making of filler material and supporting construction to make the circuit variation, and can be widely used in various semiconductor packages demands.
Two, can be pre-formed a plurality of Metal Ball to reduce the scrappage and the cost of encapsulation, improve the reliability of potted element.
Three, because of all with filler it being filled between each pin, thus the excessive glue that is produced can avoid fully using the conventional wires frame to be encapsulated in encapsulating the time to the problem of last tin face (SMT Pad), can reduce encapsulation technology, improve acceptance rate and reduce cost.
Four, can be formed with the lead frame of a storage tank to reduce overall packaging height.
The above is a preferred embodiment of the present invention only, is not to be used for limiting scope of the invention process, so all equalizations of being done according to the described process of claim of the present invention, feature and spirit change and modify, all should be included in protection scope of the present invention.
Claims (38)
1. lead frame is characterized in that comprising:
One metallic plate is formed with patterning groove that runs through and the groove design that does not run through on it; And
One packing material is filled in the patterning groove or groove of described metallic plate, in order to binding, support this metallic plate is completely cut off to be a plurality of conductive regions.
2. lead frame as claimed in claim 1 is characterized in that, described packing material is an insulating material, and it is described metallic plate to be completely cut off be a plurality of conductive regions.
3. lead frame as claimed in claim 1 is characterized in that, described packing material is a conductive material, and it is to be filled in described metallic plate specific the patterning groove and groove, in order to forming special electrical areas in the zone.
4. lead frame as claimed in claim 2 is characterized in that, on a plurality of conductive regions surface of described metallic plate more through a surface treatment, to form a conductive layer.
5. lead frame as claimed in claim 4 is characterized in that, described conductive layer is the Treatment of Metal Surface that is selected from electro-less plating Sn, electrotinning, electrotinning lead, spray tin lead, electroless deposition of silver, electrosilvering, electronickelling gold, electroless nickel plating porpezite and ENIG.
6. lead frame as claimed in claim 1 is characterized in that, the formation method of described groove or groove is to be selected from repeatedly Wet-type etching, dry-etching, casting or the dark control of process molding mode.
7. lead frame as claimed in claim 1 is characterized in that, described groove or groove are to finish through selective etch mode made repeatedly.
8. lead frame as claimed in claim 1 is characterized in that, described groove or groove are to finish through dark control molding mode made repeatedly.
9. lead frame as claimed in claim 1 is characterized in that described groove or groove are finished through the forging type made.
10. lead frame as claimed in claim 1 is characterized in that, the chip on described metallic plate is installed the precalculated position and also is provided with one or more storage tanks, for one or more chips are installed.
11. lead frame as claimed in claim 1 is characterized in that, also can select to form or do not form an anti-welding mask layer at described metal sheet surface or above being positioned at described packing material.
12. lead frame as claimed in claim 1 is characterized in that, described packing material is all obstructs of resin, elargol, aluminium glue, ceramic material, copper glue, carbon ink or changes electrical material.
13. lead frame as claimed in claim 1 is characterized in that, also forms a plurality of Metal Ball at the lower surface of described metallic plate, externally connects usefulness for semiconductor element.
14. a manufacture of wire holder is characterized in that comprising the following steps:
One metallic plate is provided;
Described metallic plate is processed, to form a plurality of grooves and following/upper groove;
Optionally in described these grooves and following/upper groove, clog filler;
On the upper and lower surface of described metallic plate, form a plurality of conductive layers; And
Described metallic plate is processed, with form at this metallic plate upper surface a plurality of on/low groove, and optionally on these/clog filler in the low groove.
15. manufacture of wire holder as claimed in claim 14 is characterized in that, processing method can be selected from repeatedly Wet-type etching, dry-etching, casting or the dark control of process molding mode.
16. manufacture of wire holder as claimed in claim 14 is characterized in that, described time/upper groove or groove are to finish through selective etch mode made repeatedly.
17. manufacture of wire holder as claimed in claim 14 is characterized in that, described time/upper groove or groove are to finish through dark control molding mode made repeatedly.
18. manufacture of wire holder as claimed in claim 14 is characterized in that, described time/upper groove or groove are finished through the forging type made.
19. manufacture of wire holder as claimed in claim 14, it is characterized in that described conductive layer is the various Treatment of Metal Surface for semiconductor and lead frame do electric connection usefulness that are selected from electro-less plating Sn, electrotinning, electrotinning lead, spray tin lead, electroless deposition of silver, electrosilvering, electronickelling gold, electroless nickel plating porpezite and ENIG.
20. manufacture of wire holder as claimed in claim 14 is characterized in that, described packing material is all obstructs of resin, elargol, aluminium glue, ceramic material, copper glue, carbon ink or changes electrical material.
21. a manufacture of wire holder is characterized in that comprising the following steps:
One metallic plate is provided, this metallic plate is processed, to form a plurality of grooves and following/upper groove;
In described these grooves and following/upper groove, optionally clog filler;
Described metallic plate is processed, with form at this metallic plate upper surface a plurality of on/low groove, and on these/optionally clog filler in the low groove; And
On described metallic plate/lower surface forms a plurality of conductive layers.
22. manufacture of wire holder as claimed in claim 21 is characterized in that, described processing method can be selected from wet/dry-etching, casting or control moulding deeply.
23. manufacture of wire holder as claimed in claim 21 is characterized in that, described time/upper groove or groove are to finish through selective etch mode made repeatedly.
24. manufacture of wire holder as claimed in claim 21 is characterized in that, described time/upper groove or groove are to finish through dark control molding mode made repeatedly.
25. manufacture of wire holder as claimed in claim 21 is characterized in that, described time/upper groove or groove are finished through the forging type made.
26. manufacture of wire holder as claimed in claim 21, it is characterized in that described conductive layer is the various Treatment of Metal Surface for semiconductor and lead frame do electric connection usefulness that are selected from electro-less plating Sn, electrotinning, electrotinning lead, spray tin lead, electroless deposition of silver, electrosilvering, electronickelling gold, electroless nickel plating porpezite and ENIG.
27. manufacture of wire holder as claimed in claim 21 is characterized in that, described packing material is all obstructs of resin, elargol, aluminium glue, ceramic material, copper glue, carbon ink or changes electrical material.
28. a semiconductor encapsulated element is characterized in that comprising:
One metallic plate is formed with a patterning groove that runs through and a upper and lower groove design on it;
One filler, it is filled in the patterning groove or upper and lower groove of described metallic plate, is one or more chip presumptive areas and a plurality of conductive region in order to this metallic plate is completely cut off; And
One or more chips are installed on the chip presumptive area on the described metallic plate, and form electric connection with described conductive region.
29. semiconductor encapsulated element as claimed in claim 28 is characterized in that, on a plurality of conductive regions surface of described metallic plate also through a surface treatment, to form a conductive layer.
30. semiconductor encapsulated element as claimed in claim 28, it is characterized in that described conductive layer is the various Treatment of Metal Surface for semiconductor and semiconductor encapsulated element do electric connection usefulness that are selected from electro-less plating Sn, electrotinning, electrotinning lead, spray tin lead, electroless deposition of silver, electrosilvering, electronickelling gold, electroless nickel plating porpezite and ENIG.
31. semiconductor encapsulated element as claimed in claim 28 is characterized in that, comprises that also a packing colloid coats described chip.
32. semiconductor encapsulated element as claimed in claim 28 is characterized in that, described groove or groove are to finish through selective etch mode made repeatedly.
33. semiconductor encapsulated element as claimed in claim 28 is characterized in that, described groove or groove are to finish through dark control molding mode made repeatedly.
34. semiconductor encapsulated element as claimed in claim 28 is characterized in that, described groove or groove are finished through the forging type made.
35. semiconductor encapsulated element as claimed in claim 28, it is characterized in that described conductive layer is the various Treatment of Metal Surface for semiconductor and lead frame do electric connection usefulness that are selected from electro-less plating Sn, electrotinning, electrotinning lead, spray tin lead, electroless deposition of silver, electrosilvering, electronickelling gold, electroless nickel plating porpezite and ENIG.
36. semiconductor encapsulated element as claimed in claim 28 is characterized in that, described packing material is all obstructs of resin, elargol, aluminium glue, ceramic material, copper glue, carbon ink or changes electrical material.
37. semiconductor encapsulated element as claimed in claim 28 is characterized in that, the chip presumptive area on described metallic plate also is provided with one or more storage tanks, for the one or more chips of ccontaining installation.
38. semiconductor encapsulated element as claimed in claim 28 is characterized in that, also forms one or more Metal Ball at the lower surface of described metallic plate, externally connects usefulness for semiconductor element.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200610093539 CN100505230C (en) | 2006-06-26 | 2006-06-26 | Conducting wire frame and method for producing same |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200610093539 CN100505230C (en) | 2006-06-26 | 2006-06-26 | Conducting wire frame and method for producing same |
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| CN101097900A true CN101097900A (en) | 2008-01-02 |
| CN100505230C CN100505230C (en) | 2009-06-24 |
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| CN 200610093539 Expired - Fee Related CN100505230C (en) | 2006-06-26 | 2006-06-26 | Conducting wire frame and method for producing same |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107393896A (en) * | 2017-08-09 | 2017-11-24 | 林英洪 | Lead frame preparation method |
| CN107845618A (en) * | 2013-08-18 | 2018-03-27 | 乾坤科技股份有限公司 | Electronic system with composite base material |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102263078A (en) * | 2011-06-13 | 2011-11-30 | 西安天胜电子有限公司 | WLCSP (Wafer Level Chip Scale Package) packaging component |
| CN103025068A (en) * | 2011-09-21 | 2013-04-03 | 三星泰科威株式会社 | Method for manuracturing printed circuit board with via and fine pitch circuit and printed circuit board by the same method |
| CN107845618A (en) * | 2013-08-18 | 2018-03-27 | 乾坤科技股份有限公司 | Electronic system with composite base material |
| CN106803487A (en) * | 2015-11-26 | 2017-06-06 | 恒劲科技股份有限公司 | The preparation method of packaging system and its lead frame and lead frame |
| CN106803487B (en) * | 2015-11-26 | 2019-02-15 | 恒劲科技股份有限公司 | The production method of packaging system and its lead frame and lead frame |
| CN106970694A (en) * | 2017-05-11 | 2017-07-21 | 合肥联宝信息技术有限公司 | The preparation method of heat conducting pipe, electronic equipment and heat conducting pipe |
| CN107393896A (en) * | 2017-08-09 | 2017-11-24 | 林英洪 | Lead frame preparation method |
| CN107393896B (en) * | 2017-08-09 | 2019-08-23 | 林英洪 | Lead frame production method |
| CN108122783A (en) * | 2017-12-25 | 2018-06-05 | 谢涛 | A kind of precision unit structure manufacturing method of chip wire rack |
| CN111968920A (en) * | 2020-08-31 | 2020-11-20 | 福建天电光电有限公司 | Lead frame and manufacturing method thereof |
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| CN100505230C (en) | 2009-06-24 |
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