CN101055860A - Lead frame encapsulation structure with the high-density pin array - Google Patents
Lead frame encapsulation structure with the high-density pin array Download PDFInfo
- Publication number
- CN101055860A CN101055860A CN 200610074683 CN200610074683A CN101055860A CN 101055860 A CN101055860 A CN 101055860A CN 200610074683 CN200610074683 CN 200610074683 CN 200610074683 A CN200610074683 A CN 200610074683A CN 101055860 A CN101055860 A CN 101055860A
- Authority
- CN
- China
- Prior art keywords
- those
- chip
- lead frame
- pins
- kenel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
The present invention provides a lead frame base package structure with a high-density arranged pins. The said lead frame base package structure contains a chip, a plurality of first type pins, and a plurality of second type pins, wherein the first and second type pins located at at least one side of the chip, and electrically connected with the chip. The first and second type pins are any two kinds selected from a J-shaped pin, and a L-shaped pin and a I-shaped pin, and the welding end of the first type pins and the welding end of the second type pins are arranged in a dislocation mode, so that the pins can be arranged in a high-density without occurrence short-circuit.
Description
[technical field]
The present invention is about a kind of lead frame encapsulation structure, especially about a kind of dislocation arrangement by the pin welding ends so that pin can be the lead frame encapsulation structure that high density is arranged.
[background technology]
Owing to have the advantage of low manufacturing cost and high reliability, the leaded package structure has been used a very long time in the integrated circuit encapsulation field, especially has suitable market for the low pin count chip.
Please refer to Fig. 1, Fig. 2 and Fig. 3, Fig. 1 is that vertical view, Fig. 2 of existing leaded package structure 10 is the end view of existing leaded package structure 10, and Fig. 3 is the vertical view of existing printed circuit board (PCB) 30.As shown in Figures 1 and 2, existing leaded package structure 10 includes a chip 12, several pins 14 and a crystalline setting area 16, have several joint sheets 18 and each pin 14 to comprise a welding ends 22 and an external welding end 24 in one respectively on its chips 12, joint sheet 18 then is electrically connected to the interior welding ends 22 of pin 14.In addition, a packing colloid 26 coating chips 12 and interior welding ends 22 and curing molding are arranged, suppose that at this this packing colloid 26 is that transparent material is conveniently to inspect the structure of packing colloid 26 inside.As shown in Figure 3, the external welding end 24 of pin 14 is electrically connected to the corresponding link 32 on the printed circuit board (PCB) 30.What especially note is, in the existing leaded package structure 10, be all single-row arrangement between the link 32 corresponding in each between welding ends 22, between each external welding end 24 with each, wherein, one spacing (lead pitch) 24a is arranged between each external welding end 24, and a spacing 32a is arranged between each link 32.
Yet, along with the integrated circuit (IC) products demand of precise treatment constantly, for size and the while that reduces packaging structure do not reduce number of pins, perhaps increasing number of pins and while does not increase the size of packaging structure, just must develop the conducting wire frame structure that high-density pin is arranged.Existing leaded package structure 10 becomes a restriction of precise treatment, just need dwindle spacing 24a between the adjacent leads 14 because desire increases the density of pin 14, and increase the probability that string news (cross-talk) or signal disturb and cause difficulty in the packaging structure manufacturing.In theory, one pin 14 should only be electrically connected to the link 32 of these pin 14 correspondences, but because the mobile or contraposition skew factors such as (misalignment) of expanded by heating, welding material, can cause between electric conducting material conducting pin 14 and the pin 14, therefore produce electrical situation of short circuit, and influence the normal running of product.
In existing leaded package structure 10,, all must increase the density of pin 14 and increase the interior welding ends 22 of pin 14 and the density of external welding end 24 if want to dwindle the size of leaded package or under the situation that does not increase size, increase the number of pin 14.When the density of welding ends 22,24 increased, the spacing 24a between the welding ends 22,24 can dwindle and cause the probability of string news or signal interference to raise.Therefore the present invention proposes the lead frame encapsulation structure that a kind of high-density pin is arranged, to solve the existing existing deficiency of method.
[summary of the invention]
Main purpose of the present invention is to provide a kind of conducting wire frame structure that high-density pin is arranged that has, to solve the difficult problem that prior art can't overcome.
Lead frame encapsulation structure of the present invention includes: a chip; Several first kenel pins are positioned at least one side of this chip, and electrically connect with this chip; And several second kenel pins are positioned at least one side of this chip, and electrically connect with this chip, and wherein those first kenel pins and those second kenel pins are selected from J type pin, L type pin and the I type pin wantonly two kinds.
Because the first kenel pin and the second kenel pin are selected from wantonly two kinds in J type pin, L type pin and the I type pin, make the welding ends of the welding ends of the kenel pin of winning and the second kenel pin can not be positioned at same single on and be the dislocation mode and arrange.Therefore, under the constant situation of adjacent leads distance, distance will increase between welding ends and the welding ends, and at welding ends each other under the constant situation of distance, the adjacent leads distance can be dwindled.Because the raising of pin arrangements density, can dwindle the size of lead frame encapsulation structure or increase the number of the welding ends of lead frame encapsulation structure, make precision improve.
[description of drawings]
Fig. 1 is the vertical view of existing leaded package structure.
Fig. 2 is the end view of existing leaded package structure.
Fig. 3 is the vertical view of existing printed circuit board (PCB).
Fig. 4 is the vertical view of the leaded package structure of the present invention's first preferred embodiment.
Fig. 5 is the end view of the leaded package structure of the present invention's first preferred embodiment.
Fig. 6 is the vertical view of the printed circuit board (PCB) of the present invention's first preferred embodiment.
Fig. 7 is the vertical view of the leaded package structure of the present invention's second preferred embodiment.
Fig. 8 is the end view of the leaded package structure of the present invention's second preferred embodiment.
Fig. 9 is the vertical view of the printed circuit board (PCB) of the present invention's second preferred embodiment.
Figure 10 is the vertical view of the leaded package structure of the present invention's the 3rd preferred embodiment.
Figure 11 is the end view of the leaded package structure of the present invention's the 3rd preferred embodiment.
Figure 12 is the vertical view of the printed circuit board (PCB) of the present invention's the 3rd preferred embodiment.
Figure 13 is the vertical view of the leaded package structure of the present invention's the 4th preferred embodiment.
Figure 14 is the end view of the leaded package structure of the present invention's the 4th preferred embodiment.
Figure 15 is the vertical view of the printed circuit board (PCB) of the present invention's the 4th preferred embodiment.
Figure 16 is the structural representation of routing bond package.
Figure 17 is the structural representation of chip bonding encapsulation.
[embodiment]
Please refer to Fig. 4 to Fig. 6, Fig. 4 is the vertical view of the leaded package structure 40 of the present invention's first preferred embodiment, the 5th figure is the end view of the leaded package structure 40 of the present invention's first preferred embodiment, and Fig. 6 is the vertical view of the printed circuit board (PCB) 50 of the present invention's first preferred embodiment.As Fig. 4 and shown in Figure 5, lead frame encapsulation structure 40 includes a Chip Packaging 42, several J type pins 44 and several L type pins 46, wherein each pin 44 and 46 comprises a welding ends (not shown) and an external welding end 48 in one respectively, wherein between each external welding end 48 of same row a spacing 48a is arranged.As shown in Figure 6, provide a printed circuit board (PCB) 50, wherein having several correspondences on the printed circuit board (PCB) 50 should be in the link 52 of external welding end, and a spacing 52a is arranged between each link 52.Then, printed circuit board (PCB) 50 surfaces beyond link 52 form an anti-welding resistance agent 54 to lower the possibility of short circuit, and link 52 then exposes by anti-welding resistance agent opening (solderresist opening).Then pin 44 and 46 external welding end 48 are electrically connected to the corresponding link 52 on the printed circuit board (PCB) 50.The characteristics of present embodiment are that the link 52 that each external welding end 48 is corresponding with each each other is all the biserial dislocation each other and arranges, and welding ends (not shown) is single-row arrangement each other in each.In addition, singly be not confined to single-row arrangement between the welding ends in each, also can be the biserial dislocation and arrange.
If pin 44 is compared with existing lead frame encapsulation structure 10 shown in Figure 1 with 46 structures, under the identical situation of pin-pitch, the welding ends spacing 48a among this embodiment is bigger than the welding ends spacing 24a of existing structure.In biserial dislocation is arranged, when the spacing 52a of the spacing 48a of same row welding ends or same row link is single-row arrangement the two times wide.On the other hand, if under the identical situation of pin-pitch, lead frame encapsulation structure of the present invention can be installed more link than existing lead frame encapsulation structure.
Please refer to Fig. 7 to Fig. 9, Fig. 7 is the vertical view of the leaded package structure 60 of the present invention's second preferred embodiment, Fig. 8 is the end view of the leaded package structure 60 of the present invention's second preferred embodiment, and Fig. 9 is the vertical view of the printed circuit board (PCB) 70 of the present invention's second preferred embodiment.As shown in Figures 7 and 8, be with the previous embodiment difference, lead frame encapsulation structure 60 includes a Chip Packaging 62, several J type pins 64 and several I type pins 66, and wherein each pin 64 and 66 comprises a welding ends (not shown) and an external welding end 68 in one respectively.As shown in Figure 9, provide a printed circuit board (PCB) 70, wherein have several link 72 and 70 surfaces of the printed circuit board (PCB) beyond link 72 on the printed circuit board (PCB) 70 and form an anti-welding resistance agent 74 corresponding to external welding end 68.Then pin 66 and 64 external welding end 68 are electrically connected to the corresponding link 72 on the printed circuit board (PCB) 70.
Please refer to Figure 10 to Figure 12, Figure 10 is the vertical view of the leaded package structure 80 of the present invention's the 3rd preferred embodiment, Figure 11 is the end view of the leaded package structure 80 of the present invention's the 3rd preferred embodiment, and Figure 12 is the vertical view of the printed circuit board (PCB) 90 of the present invention's the 3rd preferred embodiment.Shown in Figure 10 and 11, be with aforementioned two embodiment differences, lead frame encapsulation structure 80 includes a Chip Packaging 82, several I type pins 84 and several L type pins 86, and wherein each pin 84 and 86 comprises a welding ends (not shown) and an external welding end 88 in one respectively.As shown in figure 12, provide a printed circuit board (PCB) 90, wherein have several link 92 and 90 surfaces of the printed circuit board (PCB) beyond link 92 on the printed circuit board (PCB) 90 and form an anti-welding resistance agent 94 corresponding to external welding end 88.Then pin 86 and 84 external welding end 88 are electrically connected to the corresponding link 92 on the printed circuit board (PCB) 90.
Please refer to Figure 13 to 15, Figure 13 is the vertical view of the leaded package structure 100 of the present invention's the 4th preferred embodiment, Figure 14 is the end view of the leaded package structure 100 of the present invention's the 4th preferred embodiment, and Figure 15 is the vertical view of the printed circuit board (PCB) 120 of the present invention's the 4th preferred embodiment.Shown in Figure 13 and 14, be with aforementioned three embodiment differences, lead frame encapsulation structure 100 includes a Chip Packaging 102, several J type pins 104, several I type pins 106 and several L type pins 108, and wherein each pin 104,106 and 108 comprises a welding ends (not shown) and an external welding end 112 in one respectively.As shown in figure 15, provide a printed circuit board (PCB) 120, wherein have several links 122 on the printed circuit board (PCB) 120, and 120 surfaces of the printed circuit board (PCB) beyond link 122 form an anti-welding resistance agent 124 corresponding to external welding end 112.Then pin 104,106 and 108 external welding end 112 are electrically connected to the corresponding link 122 of answering on the printed circuit board (PCB) 120.The characteristics of present embodiment are, corresponding with each the each other link of answering 122 of each external welding end 112 is all three row dislocation each other and arranges, make between the same row welding ends 112 or the spacing between the link 122 wideer.
The chip of above-mentioned first embodiment to the, four embodiment can adopt routing to engage or chip bonding with the pin juncture.Please refer to Figure 16 and 17, Figure 16 is the structural representation of routing bond package 160, and Figure 17 is the structural representation of chip bonding encapsulation 170.As shown in figure 16, utilize wiring 162 that chip 164 and interior welding ends 166 are electrically connected.As shown in figure 17, utilize tin ball 172 that chip 174 and interior welding ends 176 are electrically connected.
In existing leaded package structure, the density that increases pin will increase the density of the welding ends of pin, and increases the density of link corresponding on the printed circuit board (PCB), and the possibility that makes short circuit or signal disturb raises.Because welding ends of the present invention adopts dislocation to arrange, having under the situation of same pin density with existing lead frame encapsulation structure, the welding ends spacing of the existing method of welding ends gap ratio of the present invention is greater, and therefore can reduce the probability that short circuit or signal disturb.In sum, lead frame encapsulation structure of the present invention can improve the density of welding ends or link and can not have influence on the processing procedure (surface mount technology) of surface mount technology or the running of printed circuit board (PCB).
The above only is preferred embodiment of the present invention, and all equalizations of being done according to claim scope of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (8)
1. a leaded package (lead frame base package) structure comprises a chip; Several first kenel pins that are positioned at least one side of chip and electrically connect with chip; And several second kenel pins that are positioned at least one side of chip and electrically connect with chip; It is characterized in that: those first kenel pins and those second kenel pins are selected from wantonly two kinds in J type pin, L type pin and the I type pin.
2. lead frame encapsulation structure as claimed in claim 1 is characterized in that: the described first kenel pin comprises welding ends in one first respectively, and the described second kenel pin comprises welding ends in one second respectively, in order to electrically connect with chip.
3. as claim 2 a described lead frame encapsulation structure, it is characterized in that: described chip utilizes the routing mode to electrically connect with those first interior welding endss and those second interior welding endss respectively.
4. lead frame encapsulation structure as claimed in claim 2 is characterized in that: crystal type direct and those first interior welding endss and those second interior welding ends electric connections are covered in described chip utilization.
5. lead frame encapsulation structure as claimed in claim 4, it is characterized in that: the distance of those first interior welding endss and chip central authorities, and those in second welding endss different with the distance of chip central authorities, by this those in first welding endss and those second interior welding endss be the dislocation mode and arrange.
6. lead frame encapsulation structure as claimed in claim 1 is characterized in that: those first kenel pins and those second kenel pins are for being staggered.
7. as claim 1 a described lead frame encapsulation structure, it is characterized in that: those first kenel pins include one first external welding end respectively, and those second kenel pins include one second external welding end respectively.
8. lead frame encapsulation structure as claimed in claim 7, it is characterized in that: the distance of those first external welding ends and these chip central authorities, and those second external welding ends are different with the distance of chip central authorities, and those first external welding ends and those second external welding ends are the dislocation mode and arrange by this.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200610074683 CN100521182C (en) | 2006-04-11 | 2006-04-11 | Lead frame encapsulation structure with the high-density pin array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200610074683 CN100521182C (en) | 2006-04-11 | 2006-04-11 | Lead frame encapsulation structure with the high-density pin array |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101055860A true CN101055860A (en) | 2007-10-17 |
| CN100521182C CN100521182C (en) | 2009-07-29 |
Family
ID=38795597
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200610074683 Expired - Fee Related CN100521182C (en) | 2006-04-11 | 2006-04-11 | Lead frame encapsulation structure with the high-density pin array |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100521182C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101964335A (en) * | 2009-07-23 | 2011-02-02 | 日月光半导体制造股份有限公司 | Packaging member and production method thereof |
| CN107631812A (en) * | 2017-07-25 | 2018-01-26 | 首凯汽车零部件（江苏）有限公司 | A kind of high temperature compact substance is into porcelain thermistor temperature sensor |
-
2006
- 2006-04-11 CN CN 200610074683 patent/CN100521182C/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101964335A (en) * | 2009-07-23 | 2011-02-02 | 日月光半导体制造股份有限公司 | Packaging member and production method thereof |
| CN107631812A (en) * | 2017-07-25 | 2018-01-26 | 首凯汽车零部件（江苏）有限公司 | A kind of high temperature compact substance is into porcelain thermistor temperature sensor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100521182C (en) | 2009-07-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11374068B2 (en) | Display panel and display apparatus | |
| US7280372B2 (en) | Stair step printed circuit board structures for high speed signal transmissions | |
| CN2697858Y (en) | Electric connector | |
| KR970702582A (en) | Semiconductor integrated circuit device and its manufacturing method and manufacturing device (SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND METHOD AND APPARATUS FOR MANUFACTURINGIT) | |
| CN1213874A (en) | High density electrical connector assembly | |
| CN1742372A (en) | Integrated circuit assembly | |
| CN1959425A (en) | Semiconductor apparatus testing arrangement and semiconductor apparatus testing method | |
| CN108718481B (en) | Pin structure and binding structure of display panel | |
| CN101044801A (en) | Circuit board assembly with reduced capacitive coupling | |
| CN1967839A (en) | Stacking method and stacked structure for attaching memory components to associated device | |
| CN201174842Y (en) | Electronic device | |
| CN1914962A (en) | Method for increasing a routing density for a circuit board and such a circuit board | |
| CN101055860A (en) | Lead frame encapsulation structure with the high-density pin array | |
| CN1171516C (en) | Printed circuit board structure | |
| CN2896794Y (en) | Circuit-board with differential signal transmission structure | |
| CN101064992A (en) | Printed circuit board and wiring method | |
| CN2854807Y (en) | Integral circuit device | |
| CN1206728C (en) | Chip package and its making process | |
| CN101738806B (en) | Array backboard, probe used for testing array backboard and liquid crystal display panel | |
| CN2538067Y (en) | Crystal covered package base | |
| CN1558270A (en) | Structure for increasing reliability of metal connecting line | |
| CN102487165B (en) | Connector with a locking member | |
| CN1284996C (en) | Outer pin structure | |
| CN101068450A (en) | Circuit board system | |
| CN2594979Y (en) | Integrated circuit chip carrier |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090729 Termination date: 20180411 |