CN108718481B - Pin structure and binding structure of display panel - Google Patents
Pin structure and binding structure of display panel Download PDFInfo
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- CN108718481B CN108718481B CN201810352156.4A CN201810352156A CN108718481B CN 108718481 B CN108718481 B CN 108718481B CN 201810352156 A CN201810352156 A CN 201810352156A CN 108718481 B CN108718481 B CN 108718481B
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09427—Special relation between the location or dimension of a pad or land and the location or dimension of a terminal
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention provides a pin structure and a binding structure of a display panel, wherein the pin structure comprises: the circuit carrier comprises a plurality of groups of pins arranged on the circuit carrier, wherein the plurality of groups of pins are arranged side by side, each group of pin groups comprises a first pin and a second pin, and the first pin and the second pin both comprise a first pin edge and a second pin edge; in each group of pin groups, a first pin edge of a first pin and a first pin edge of a second pin are parallel and are positioned on the same plane, the first pin edge of the first pin and a second pin edge of the second pin are arranged in a vertical opposite manner, and the first pin edge of the second pin and the second pin edge of the first pin are arranged in a vertical opposite manner; the circuit carrier is a flip chip film or a flexible circuit board. The invention can avoid the risk of short circuit between the pin and the adjacent binding terminal when the pin on the chip on film is bound with the binding terminal on the glass substrate, and reduce the requirement of alignment precision between the pin and the binding terminal.
Description
Technical Field
The invention relates to the technical field of display, in particular to a pin structure and a binding structure of a display panel.
Background
With the development of display technology, especially the popularization of handheld display devices such as mobile phones/tablet computers and the like, the demand of users on high resolution of products is higher and higher; the high resolution means that the wiring is denser (Fine-pitch design) under the same size, and the requirement on the precision of the module binding process is higher.
The binding terminals on the glass substrate of the existing display panel are shown in fig. 1, the binding terminals 10 adopt a double-row design, the corresponding pins (pin pins) of the COF circuit are in a single-layer design, and when the pins of the COF and the binding terminals of the glass substrate are bound and bonded, the corresponding structural schematic diagram is shown in fig. 2. The width d1 of the binding terminals 10 on the glass substrate is 12 micrometers, and the distance d3 between two adjacent binding terminals 10 in the same row is 16 micrometers. The width d2 of a single lead 20 on the chip on film is 10 microns, and the distance between the lead 20 and the first row of two adjacent bonding terminals 10 on both sides of the lead 20 is 3 microns.
Therefore, in order to prevent the short circuit of the bonding circuit between the chip on film and the glass substrate, the corresponding bonding alignment precision is required to be within plus or minus 3 microns, and if the alignment precision exceeds 3 microns, the short circuit abnormal risk exists in the bonding circuit between the chip on film and the glass substrate.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides a pin structure and a bonding structure of a display panel, which can avoid reducing the risk of short circuit between a pin and an adjacent bonding terminal and reducing the requirement for alignment accuracy between the pin and the bonding terminal when the pin on a chip on film is bonded with the bonding terminal on a glass substrate.
The invention provides a pin structure, comprising: the circuit carrier comprises a plurality of groups of pins arranged on the circuit carrier, wherein the plurality of groups of pins are arranged side by side, each group of pin groups comprises a first pin and a second pin, and the first pin and the second pin comprise a first pin edge and a second pin edge;
in each group of pin groups, a first pin edge of the first pin and a first pin edge of the second pin are parallel and are positioned on the same plane, the first pin edge of the first pin and a second pin edge of the second pin are arranged in a vertical opposite manner, and the first pin edge of the second pin and the second pin edge of the first pin are arranged in a vertical opposite manner;
wherein the first pin and the second pin in each group of pin groups are not overlapped in a crossing way; the circuit carrier is a flip chip film or a flexible circuit board.
Preferably, in each group of pin groups, the first pin edge of the first pin and the first pin edge of the second pin are both located at the first surface of the circuit carrier, the second pin edge of the first pin and the second pin edge of the second pin are both located at the second surface of the circuit carrier, and the first surface and the second surface of the circuit carrier are two opposite surfaces.
Preferably, the length of the first pin edge of the first pin is greater than the length of the second pin edge of the second pin, and the length of the first pin edge of the second pin is greater than the length of the second pin edge of the first pin;
a first through hole is formed in the circuit carrier at one end of the first pin edge of the first pin, and the first pin edge of the first pin is in conductive connection with the second pin edge of the first pin through the first through hole;
and a second through hole is formed in the circuit carrier at one end of the first pin edge of the second pin, and the first pin edge of the second pin is in conductive connection with the second pin edge of the second pin through the second through hole.
Preferably, the lengths of the first pin edge of the first pin, the second pin edge of the first pin, the first pin edge of the second pin and the second pin edge of the second pin are not less than the length of the pin on the glass substrate; and the length of the first pin edge of the first pin is the same as the length of the first pin edge of the second pin, and the length of the second pin edge of the first pin is the same as the length of the second pin edge of the second pin.
Preferably, the widths of the first pin edge of the first pin, the second pin edge of the first pin, the first pin edge of the second pin, and the second pin edge of the second pin are all the same;
the distance between the first pin edge of the first pin and the second pin edge of the first pin is set as a first distance, the distance between the first pin edge of the second pin and the second pin edge of the second pin is set as a second distance, and the first distance is the same as the second distance.
Preferably, the multiple groups of pin groups are arranged side by side at equal intervals.
Preferably, the first pin and the second pin are both made of copper material.
The invention also provides a binding structure of the display panel, which comprises two rows of binding terminal groups positioned on the glass substrate and the pin structure;
in the two rows of binding terminal groups on the glass substrate, each row of binding terminal group comprises a plurality of binding terminals which are parallel to each other and are arranged at equal intervals; the terminal groups in the first row and the terminal groups in the second row are staggered, and the binding terminals in the terminal groups in the first row and the binding terminals in the terminal groups in the second row are not on the same straight line;
the first pin edges of the first pins and the first pin edges of the second pins, which correspond to the multiple groups of pin groups on the circuit carrier, are respectively and correspondingly bound and attached to the two rows of binding terminal groups on the glass substrate.
Preferably, the width of the first lead edge of the first lead and the width of the first lead edge of the second lead are smaller than the width of the binding terminal on the glass substrate.
Preferably, a connector between a first lead edge of the first lead and a second lead edge of the first lead, and a connector between a first lead edge of the second lead and a second lead edge of the second lead are both opposite to an area between two rows of binding terminal groups on the glass substrate.
The implementation of the invention has the following beneficial effects: the pin structure provided by the invention adopts a double-layer crossing design mode, each group of pin groups comprises two pins which are crossed and do not coincide with each other, wherein the first pin edge of the first pin and the first pin edge of the second pin are staggered and arranged in parallel and are used for being jointed and bound with a binding terminal on a glass substrate, and the second pin edge of the first pin and the second pin edge of the second pin are not used for being jointed with the binding terminal.
The second pin edge of the second pin and the first pin edge of the first pin are arranged oppositely from top to bottom, and the second pin edge of the first pin and the first pin edge of the second pin are arranged oppositely from top to bottom. Meanwhile, the requirement on the alignment precision between the pin and the binding terminal can be reduced, and the maximum alignment precision can be required to be not more than 16 microns.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic view of a binding terminal on a glass substrate provided by the present invention.
Fig. 2 is a schematic diagram illustrating bonding between a pin on a chip on film and a bonding terminal on a glass substrate in the background art provided by the present invention.
Fig. 3 is a schematic structural diagram of the first pin and the second pin of the same pin group on the circuit carrier according to the present invention.
Fig. 4 is a structural diagram of a first lead provided by the present invention.
Fig. 5 is a structural diagram of a second lead provided by the present invention.
Fig. 6 is a cross-sectional view of a first lead and a second lead of the same set of leads provided by the present invention on a circuit carrier.
Fig. 7 is a schematic diagram of a first via on a circuit carrier provided by the present invention.
Fig. 8 is a schematic diagram of a second via on a circuit carrier provided by the present invention.
Fig. 9 is a side view of the bonding process between the first and second leads on the circuit carrier and the bonding terminals on the glass substrate according to the present invention.
Fig. 10 is a top view of the bonding between the first and second leads on the circuit carrier and the bonding terminals on the glass substrate according to the present invention.
Detailed Description
The present invention provides a lead structure, as shown in fig. 3, the lead structure includes: the multi-pin-group circuit board comprises a plurality of groups of pin groups 100 arranged on a circuit carrier 3, wherein the plurality of groups of pin groups 100 are arranged side by side at equal intervals, each group of pin groups 100 comprises a first pin 1 and a second pin 2, and the first pin 1 and the second pin 2 comprise a first pin edge and a second pin edge. As shown in fig. 4, the first lead 1 includes a first lead edge 11, a second lead edge 12, and a connector 13 between the first lead edge 11 and the second lead edge 12. As shown in fig. 5, the second lead 2 includes a first lead side 21, a second lead side 22, and a connection body 23 between the first lead side 21 and the second lead side 22.
In each group of pin groups 100, as shown in fig. 6, the first pin edge 11 of the first pin 1 and the first pin edge 21 of the second pin 2 are parallel and located on the same plane, the first pin edge 11 of the first pin 1 and the second pin edge 22 of the second pin 2 are disposed opposite to each other in the vertical direction, and the first pin edge 21 of the second pin 2 and the second pin edge 12 of the first pin 1 are disposed opposite to each other in the vertical direction.
Wherein, the first pin 1 and the second pin 2 in each pin group 100 are not overlapped; the circuit carrier 3 is a chip on film or a flexible circuit board.
Further, in each pin group 100, the first pin edge 11 of the first pin 1 and the first pin edge 21 of the second pin 2 are located at a first surface of the circuit carrier 3 (e.g., a lower surface of the circuit carrier 3), the second pin edge 12 of the first pin 1 and the second pin edge 22 of the second pin 2 are located at a second surface of the circuit carrier 3 (e.g., an upper surface of the circuit carrier 3), and the first surface and the second surface of the circuit carrier 3 are opposite surfaces.
Further, the length of the first lead edge 11 of the first lead 1 is greater than the length of the second lead edge 22 of the second lead 2, and the length of the first lead edge 21 of the second lead 2 is greater than the length of the second lead edge 12 of the first lead 1.
As shown in fig. 7, a first via hole 31 is disposed at the circuit carrier 3 at one end of the first lead edge 11 of the first lead 1, and the first lead edge 11 of the first lead 1 is electrically connected to the second lead edge 12 of the first lead 1 through the first via hole 31.
As shown in fig. 8, a second via hole 32 is disposed at the circuit carrier 3 at one end of the first lead edge 21 of the second lead 2, and the first lead edge 21 of the second lead 2 is electrically connected to the second lead edge 22 of the second lead 2 through the second via hole 32.
Further, the lengths of the first lead edge 11 of the first lead 1, the second lead edge 12 of the first lead 1, the first lead edge 21 of the second lead 2 and the second lead edge 22 of the second lead 2 are not less than the length of the lead on the glass substrate; and the length of the first lead edge 11 of the first lead 1 is the same as the length of the first lead edge 21 of the second lead 2, and the length of the second lead edge 12 of the first lead 1 is the same as the length of the second lead edge 22 of the second lead 2. That is, the lengths of the projections of the first lead edge 11 of the first lead 1, the second lead edge 12 of the first lead 1, the first lead edge 21 of the second lead 2, and the second lead edge 22 of the second lead 2 on the circuit carrier 3 are all the same.
Further, the widths of the first lead edge 11 of the first lead 1, the second lead edge 12 of the first lead 1, the first lead edge 21 of the second lead 2, and the second lead edge 22 of the second lead 2 are the same. That is, the widths of the projections of the first lead edge 11 of the first lead 1, the second lead edge 12 of the first lead 1, the first lead edge 21 of the second lead 2, and the second lead edge 22 of the second lead 2 on the circuit carrier 3 are all the same.
The distance between the first lead edge 11 of the first lead 1 and the second lead edge 12 of the first lead 1 is set as a first distance, the distance between the first lead edge 21 of the second lead 2 and the second lead edge 22 of the second lead 2 is set as a second distance, and the first distance and the second distance are the same.
Further, the first pin 1 and the second pin 2 are both made of copper material.
The present invention further provides a bonding structure of a display panel, as shown in fig. 9 and 10, the bonding structure includes two rows of bonding terminal sets on a glass substrate 30, and the above-mentioned pin structure.
In two rows of binding terminal groups on the glass substrate 30, each row of binding terminal group comprises a plurality of binding terminals 10 which are parallel to each other and are arranged at equal intervals; the first row of binding terminal groups and the second row of binding terminal groups are staggered, and the binding terminals 10 in the first row of binding terminal groups and the binding terminals 10 in the second row of binding terminal groups are not on the same straight line. The extension lines of the binding terminals 10 in the first row of binding terminal groups do not coincide with the binding terminals in the second row of binding terminal groups. Of course, the binding terminal 10 is also a pin.
The first lead edges 11 of the first leads 1 and the first lead edges 21 of the second leads 2 corresponding to the multiple lead groups 100 on the circuit carrier 3 are respectively and correspondingly bonded with the two rows of bonding terminal groups on the glass substrate 30.
Here, the bonding may be performed by an ACF (Anisotropic Conductive Film) hot pressing method, so that signal conduction between the first pin 1, the second pin 2, and the bonding terminal 10 is realized.
Preferably, the second lead edge 12 of the first leads 1 and the second lead edge 22 of the second leads 2 are used for accessing the test electrical signal output by the test device.
Further, the width of the first lead edge 11 of the first lead 1 and the width of the first lead edge 21 of the second lead 2 are smaller than the width of the bonding terminal 10 on the glass substrate 30.
Here, the width of the first lead side and the width of the binding terminal 10 are the widths of the first lead 1 and the second lead 2 viewed from a top view in fig. 10, and it is needless to say that the length of the first lead side, the length of the second lead side, and the length of the binding terminal 10 are the lengths of the first lead 1 and the second lead 2 viewed from a top view in fig. 10. That is, the length and width of the first lead edge are the length and width of the first lead edge projected on the circuit carrier, and the length and width of the second lead edge are the length and width of the second lead edge projected on the circuit carrier. The length and width of the binding terminal 10 are the length and width of the binding terminal 10 projected on the glass substrate.
Generally speaking, the width of the first lead edge and the width of the second lead edge both range from 7 to 9 micrometers, preferably 8 micrometers, and the width of the binding terminal 10 ranges from 9 to 11 micrometers, and optionally 10 micrometers.
In fig. 10, it can be seen that the first lead edge, the second lead edge, and the binding terminals 10 are all rectangular in shape when viewed from a top view, and adjacent binding terminals 10 in the same row are parallel to each other.
Further, as shown in fig. 10, the connecting body 13 between the first lead edge 11 of the first lead 1 and the second lead edge 12 of the first lead 1, and the connecting body 23 between the first lead edge 21 of the second lead 2 and the second lead edge 22 of the second lead 2 are opposite to the region 101 between the two rows of bonding terminal groups on the glass substrate 30.
In summary, the pin structure provided by the present invention adopts a double-layer cross design manner, each group of pin groups includes two pins that are cross and do not overlap with each other, wherein a first pin edge of a first pin and a first pin edge of a second pin are staggered and arranged in parallel to each other for bonding with a bonding terminal on a glass substrate, and a second pin edge of the first pin and a second pin edge of the second pin are not used for bonding with the bonding terminal.
The second pin edge of the second pin and the first pin edge of the first pin are arranged oppositely from top to bottom, and the second pin edge of the first pin and the first pin edge of the second pin are arranged oppositely from top to bottom. Therefore, the invention can be well applied to a display panel with high resolution.
Meanwhile, the requirement on the alignment precision between the pin and the binding terminal can be reduced, and the maximum alignment precision can be required to be not more than 16 microns.
Moreover, the connectors between the first pin edge and the second pin edge of the first pin and the connectors between the first pin edge and the second pin edge of the second pin adopt a crossed design mode, so that a blank area between two rows of binding terminals on the glass substrate is exposed, the transmission of bottom light under a microscope is facilitated, and personnel can conveniently identify the pins and the alignment condition between the binding terminals under the microscope.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (9)
1. A pin structure, comprising: the circuit carrier comprises a plurality of groups of pins arranged on the circuit carrier, wherein the plurality of groups of pins are arranged side by side, each group of pin groups comprises a first pin and a second pin, and the first pin and the second pin respectively comprise a first pin edge, a connector and a second pin edge which are sequentially connected; in each group of pin groups, a first pin edge of the first pin and a first pin edge of the second pin are parallel and are positioned on the same plane, the first pin edge of the first pin and a second pin edge of the second pin are arranged oppositely up and down and are positioned on the first plane, and the first pin edge of the second pin and the second pin edge of the first pin are arranged oppositely up and down and are positioned on the second plane; the first plane and the second plane are arranged in a staggered mode; in each group of pin groups, a first pin edge of the first pin and a first pin edge of the second pin are both located at a first surface of the circuit carrier, a second pin edge of the first pin and a second pin edge of the second pin are both located at a second surface of the circuit carrier, and the first surface and the second surface of the circuit carrier are two opposite surfaces;
the first pin and the second pin in each group of pin groups are not overlapped in a crossing way; the circuit carrier is a flip chip film or a flexible circuit board.
2. The lead structure of claim 1, wherein the length of the first lead edge of the first lead is greater than the length of the second lead edge of the second lead, and the length of the first lead edge of the second lead is greater than the length of the second lead edge of the first lead;
a first through hole is formed in the circuit carrier at one end of the first pin edge of the first pin, and the first pin edge of the first pin is in conductive connection with the second pin edge of the first pin through the first through hole;
and a second through hole is formed in the circuit carrier at one end of the first pin edge of the second pin, and the first pin edge of the second pin is in conductive connection with the second pin edge of the second pin through the second through hole.
3. The lead structure of claim 1, wherein the lengths of the first lead edge of the first lead, the second lead edge of the first lead, the first lead edge of the second lead, and the second lead edge of the second lead are not less than the lengths of leads on a glass substrate; and the length of the first pin edge of the first pin is the same as the length of the first pin edge of the second pin, and the length of the second pin edge of the first pin is the same as the length of the second pin edge of the second pin.
4. The lead structure of claim 1, wherein the first lead edge of the first lead, the second lead edge of the first lead, the first lead edge of the second lead, and the second lead edge of the second lead are all the same width;
the distance between the first pin edge of the first pin and the second pin edge of the first pin is set as a first distance, the distance between the first pin edge of the second pin and the second pin edge of the second pin is set as a second distance, and the first distance is the same as the second distance.
5. The pin structure of claim 1, wherein the groups of pins are arranged side-by-side with equal spacing between them.
6. The lead structure of claim 1, wherein the first lead and the second lead are both made of a copper material.
7. A bonding structure of a display panel, comprising two rows of bonding terminal sets on a glass substrate, and the pin structure of any one of claims 1 to 6;
in the two rows of binding terminal groups on the glass substrate, each row of binding terminal group comprises a plurality of binding terminals which are parallel to each other and are arranged at equal intervals; the terminal groups in the first row and the terminal groups in the second row are staggered, and the binding terminals in the terminal groups in the first row and the binding terminals in the terminal groups in the second row are not on the same straight line;
the first pin edges of the first pins and the first pin edges of the second pins, which correspond to the multiple groups of pin groups on the circuit carrier, are respectively and correspondingly bound and attached to the two rows of binding terminal groups on the glass substrate.
8. The bonding structure of the display panel according to claim 7, wherein a width of the first lead edge of the first lead and a width of the first lead edge of the second lead are smaller than a width of the bonding terminal on the glass substrate.
9. The bonding structure of the display panel according to claim 7, wherein a connector between the first lead edge of the first lead and the second lead edge of the first lead, and a connector between the first lead edge of the second lead and the second lead edge of the second lead are opposite to a region between the two rows of bonding terminal groups on the glass substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810352156.4A CN108718481B (en) | 2018-04-19 | 2018-04-19 | Pin structure and binding structure of display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201810352156.4A CN108718481B (en) | 2018-04-19 | 2018-04-19 | Pin structure and binding structure of display panel |
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| CN108718481A CN108718481A (en) | 2018-10-30 |
| CN108718481B true CN108718481B (en) | 2020-06-09 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111951682B (en) * | 2020-08-24 | 2022-05-17 | 厦门天马微电子有限公司 | Display panel and display device |
| CN115280906A (en) * | 2021-01-25 | 2022-11-01 | 京东方科技集团股份有限公司 | Bearing substrate, binding assembly and binding method thereof |
| CN114373390B (en) * | 2022-01-06 | 2023-06-02 | 武汉华星光电半导体显示技术有限公司 | Display panel and driving chip |
| CN116976272B (en) * | 2023-09-21 | 2023-12-22 | 华芯巨数(杭州)微电子有限公司 | Integrated circuit design optimization wiring method, electronic equipment and storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3300164B2 (en) * | 1994-06-28 | 2002-07-08 | エスエムケイ株式会社 | Jack board |
| CN1413072A (en) * | 2002-03-07 | 2003-04-23 | 富士康(昆山)电脑接插件有限公司 | Circuit board for cross-connected electric connector and its production method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070018292A1 (en) * | 2005-07-22 | 2007-01-25 | Sehat Sutardja | Packaging for high speed integrated circuits |
| US8291370B2 (en) * | 2010-01-19 | 2012-10-16 | Inventec Corporation | Pad layout method for surface mount circuit board and surface mount circuit board thereof |
| CN102170753A (en) * | 2011-01-31 | 2011-08-31 | 友达光电股份有限公司 | Circuit board pin structure |
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2018
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3300164B2 (en) * | 1994-06-28 | 2002-07-08 | エスエムケイ株式会社 | Jack board |
| CN1413072A (en) * | 2002-03-07 | 2003-04-23 | 富士康(昆山)电脑接插件有限公司 | Circuit board for cross-connected electric connector and its production method |
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