CN101047162A - 半导体器件及使用它的存储卡 - Google Patents
半导体器件及使用它的存储卡 Download PDFInfo
- Publication number
- CN101047162A CN101047162A CNA2007100913132A CN200710091313A CN101047162A CN 101047162 A CN101047162 A CN 101047162A CN A2007100913132 A CNA2007100913132 A CN A2007100913132A CN 200710091313 A CN200710091313 A CN 200710091313A CN 101047162 A CN101047162 A CN 101047162A
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- CN
- China
- Prior art keywords
- interarea
- distance
- substrate
- semiconductor device
- limit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
Claims (20)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006098271 | 2006-03-31 | ||
JP098271/2006 | 2006-03-31 | ||
JP277884/2006 | 2006-10-11 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101047162A true CN101047162A (zh) | 2007-10-03 |
CN100552937C CN100552937C (zh) | 2009-10-21 |
Family
ID=38771573
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2007100913132A Active CN100552937C (zh) | 2006-03-31 | 2007-03-29 | 半导体器件及使用它的存储卡 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN100552937C (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102386162A (zh) * | 2010-08-31 | 2012-03-21 | 株式会社东芝 | 半导体存储卡及其制造方法 |
CN102543909A (zh) * | 2012-03-01 | 2012-07-04 | 日月光半导体制造股份有限公司 | 不规则形状的封装结构及其制造方法 |
CN103945642A (zh) * | 2009-08-28 | 2014-07-23 | 日东电工株式会社 | 布线电路基板及其制造方法 |
-
2007
- 2007-03-29 CN CNB2007100913132A patent/CN100552937C/zh active Active
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103945642A (zh) * | 2009-08-28 | 2014-07-23 | 日东电工株式会社 | 布线电路基板及其制造方法 |
CN107846773A (zh) * | 2009-08-28 | 2018-03-27 | 日东电工株式会社 | 布线电路基板及其制造方法 |
CN102386162A (zh) * | 2010-08-31 | 2012-03-21 | 株式会社东芝 | 半导体存储卡及其制造方法 |
CN102386162B (zh) * | 2010-08-31 | 2014-11-12 | 株式会社东芝 | 半导体存储卡及其制造方法 |
CN102543909A (zh) * | 2012-03-01 | 2012-07-04 | 日月光半导体制造股份有限公司 | 不规则形状的封装结构及其制造方法 |
CN102543909B (zh) * | 2012-03-01 | 2016-08-17 | 日月光半导体制造股份有限公司 | 不规则形状的封装结构及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
CN100552937C (zh) | 2009-10-21 |
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Legal Events
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C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right | ||
TR01 | Transfer of patent right |
Effective date of registration: 20170803 Address after: Tokyo, Japan Patentee after: TOSHIBA MEMORY Corp. Address before: Tokyo, Japan Patentee before: Toshiba Corp. |
|
CP01 | Change in the name or title of a patent holder | ||
CP01 | Change in the name or title of a patent holder |
Address after: Tokyo, Japan Patentee after: TOSHIBA MEMORY Corp. Address before: Tokyo, Japan Patentee before: Japanese businessman Panjaya Co.,Ltd. Address after: Tokyo, Japan Patentee after: Kaixia Co.,Ltd. Address before: Tokyo, Japan Patentee before: TOSHIBA MEMORY Corp. |
|
TR01 | Transfer of patent right | ||
TR01 | Transfer of patent right |
Effective date of registration: 20220110 Address after: Tokyo, Japan Patentee after: Japanese businessman Panjaya Co.,Ltd. Address before: Tokyo, Japan Patentee before: TOSHIBA MEMORY Corp. |