CN1010349B - Interface of multichannel asynchronous communication - Google Patents
Interface of multichannel asynchronous communicationInfo
- Publication number
- CN1010349B CN1010349B CN 87100464 CN87100464A CN1010349B CN 1010349 B CN1010349 B CN 1010349B CN 87100464 CN87100464 CN 87100464 CN 87100464 A CN87100464 A CN 87100464A CN 1010349 B CN1010349 B CN 1010349B
- Authority
- CN
- China
- Prior art keywords
- asynchronous communication
- output terminal
- selector switch
- latchs
- communication controller
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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- Communication Control (AREA)
Abstract
The present invention provides an interface of multichannel asynchronous communication, which relates to the improvement of a computer interface device. The present invention is characterized in that a latching gate and a latching selector are respectively arranged on a serial output end and a serial input end of an asynchronous communication controller; more than two data transmission passages can be formed from input ends to output ends of the latching gate and the latching selector; the on-off of each data transmission passage can be controlled by computer instructions; thus, the present invention solves the problems that when used, an RS232C normal IBM PC and a compatible machine thereof can not be in online communication with a plurality of intelligent devices, a computer communication management system composed of the RS232C normal IBM PC and the compatible machine is difficult to utilize, etc.
Description
The invention relates to the improvement of IBM personal computer and compatible interface arrangement thereof.
In order to realize the information transmission with some intelligent apparatus such as other computing machine, plotting apparatus, serial printer, Chinese and English terminals, at present, the personal computer and the compatible thereof of the employing RS-232C standard of generally using on the market all have one or maximum two asynchronous communication serial line interfaces.Because the interface that such computing machine is equipped with is few, and the serial output terminal of the asynchronous communication controller of this interface and serial input terminal respectively have only a data transmission path, so above-mentioned condition restriction IBM personal computer and compatible thereof can only connect the machine communication with two intelligent apparatus at most, make to be difficult to utilize their to form computing machine communication management system.
Task of the present invention is to make them connect the machine communication with many intelligent apparatus for the IBM personal computer that adopts the RS-232C standard and compatible thereof provide a kind of communication interface that has improved.
Task of the present invention is finished in the following way.
The interface of multichannel asynchronous communication of the employing RS-232C standard that IBM personal computer and compatible thereof use comprises asynchronous communication controller, address decoder and level translator etc., it is characterized in that serial output terminal at asynchronous communication controller is provided with one and has the chip selection signal end, control end, input end and two above output terminals and they respectively with address decoder, data bus, the serial output terminal of asynchronous communication controller and level translator are connected latchs gate, be provided with one at the serial input terminal of asynchronous communication controller and have the chip selection signal end, control end, output terminal and two above input ends and they respectively with address decoder, data bus, the serial input terminal of asynchronous communication controller and level translator are connected latchs selector switch, latching gate is provided by address decoder with the chip selection signal that latchs selector switch, and their input ends to the data transmission path that forms between the output terminal all can be controlled its break-make by computer instruction.Like this, the serial data signal of asynchronous communication controller serial output terminal just can send to a plurality of external units selectively through latching the data transmission path that forms from the input end to the output terminal by the computer instruction regulation on the gate.The serial input terminal of asynchronous communication controller also can be stipulated formed data transmission path from the input end to the output terminal by computer instruction by latching on the selector switch, selects the one road to receive to the data that a plurality of external units are sent.
This shows, interface of multichannel asynchronous communication provided by the invention can make the IBM personal computer of employing RS-232C standard and the ability that compatible possesses multiplex communication thereof, has overcome them because interface can not connect the machine communication with many intelligent apparatus less and can not utilize their to form the problems such as communication management system of computing machine.
Provide embodiments of the invention below in conjunction with circuit structure block diagram shown in the drawings.
With reference to accompanying drawing:
(1) is address decoder among the figure.(2) be asynchronous communication controller.
It is that the ternary trigger integration member of D type of 74LS374 suitably is connected the back formation with some clamp resistances and latchs gate (3) that the present invention adopts model.This latchs gate can be that the latch of 74LS273 and 74LS32 or a door integration member suitably connect and compose by model also.
The ternary trigger of 74LS374D type has 8 input end (D
0To D
7), 8 output terminal (Q
0To Q
7), a control end (OC) and a clock signal terminal (CLK) are if at its 8 output terminal (Q
0To Q
7) on respectively connect a clamp resistance and these resistance the other end be connected to high level, then it can possess following function: will appear at 8 input end (D in clock signal (CLK) effectively the time
0To D
7) on level signal latch, and simultaneously determine 8 output terminal (Q according to this level
0To Q
7) all connect with control end (OC) and logically or a part of connect to form control end (OC) and 8 output terminal (Q with control end (OC)
0To Q
7) between data transmission path.
If will be connected to clock signal terminal (CLK), the input end (D of the ternary trigger of D type of the 74LS374 model of clamp resistance
0To D
7), a control end (OC) and 8 output terminal (Q
0To Q
7) respectively as the chip selection signal end, the control end that latch gate (3), input end with plural output terminal and link to each other with the serial output terminal and the level translator (6) of address decoder (1), data bus (5), asynchronous communication controller (2) respectively, computing machine just can send data-signal to a plurality of external units selectively by its realization.
The ternary trigger of the D type that model is 74LS374 with can make the gate that latchs after 8 clamp resistances are connected in a manner described with 8 circuit-switched data transmission channels, if the integration member of two or four this models is done suitable being connected with some clamp resistances, also can make the gate that latchs with 16 tunnel or 32 circuit-switched data transmission channels.
For latching selector switch (4), the present invention then adopts the selector switch integration member of 74LS151 model and the latch integration member of 74LS273 model to constitute jointly.
The 74LS151 selector switch has 8 data input end (D
0To D
7), three control ends (A, B, C) and an output terminal (Y), it can be according to the logic level on the control end (A, B, C) at 8 data input end (D
0To D
7) upward selection one tunnel and output terminal (Y) connection.
The 74LS273 latch has 8 data input end (D
0To D
7), 8 data output terminal (Q
0To Q
7) and a chip selection signal end (CP), it can be with data input pin (D when chip selection signal is effective
0To D
7) level signal latch and in output terminal (Q
0To Q
7) output.
Above-mentioned two kinds of integration members constitute the mode that latchs selector switch (4): from the output terminal (Q of 74LS273 latch
0To Q
7) go up optional three ends and link to each other to provide control level to the 74LS151 selector switch with the control end (A, B, C) of 74LS151 selector switch.
If will constitute above-mentioned chip selection signal end (CP), the data input pin (D that latchs the 74LS273 latch of selector switch
0To D
7) and output terminal (Y), the input end (D of 74LS151 selector switch
0To D
7) respectively as latching chip selection signal end, input end, an output terminal and the plural input end of selector switch (4), and link to each other with level translator (7) with the serial input terminal of address decoder (1), data bus (5), asynchronous communication controller (2) respectively.Data that a plurality of external units are sent then, computing machine just can realize selectively one by one reception by its.
74LS151 selector switch integration member with can make the selector switch that latchs after 74LS273 latch integration member suitably is connected with 8 circuit-switched data transmission channels, if 2 or 4 74LS151 selector switch integration members are done suitable being connected with 74LS237 latch integration member, also can make the selector switch that latchs with 16 tunnel or 32 circuit-switched data transmission channels.
It should be noted that being connected the level translator (6) that latchs on the gate (3) is to be the level translator of positive 12 volts and negative 12 volts of level with 0 volt and 5 volts of level conversion.The level translator (7) that is connected on a plurality of input ends that latch on the selector switch (4) is with positive 12 volts of level translators that become 0 volt and 5 volts level with negative 12 volts of level conversion.For the former, present embodiment has adopted the integration member of MC1488 model, then adopts the integration member of MC1489 for the latter, their inside is all integrated 4 level translator unit.
Claims (1)
1, the interface of multichannel asynchronous communication of the RS-232C standard of a kind of IBM personal computer and compatible thereof use comprises asynchronous communication controller (2), address decoder (1) and level translator (6,7) etc., it is characterized in that:
A, be provided with one at the serial output terminal of asynchronous communication controller (2) and have the chip selection signal end, control end, input end and two above output terminals and they respectively with address decoder (1) data bus (5), the serial output terminal of asynchronous communication controller (2) and level translator (6) are connected latchs gate (3), the said gate that latchs is made up of the ternary trigger integration member of 74LS374D type and several clamp resistances, connected mode is: respectively connect a clamp resistance on its 8 output terminals (Q to Q), the other end of these clamp resistances all connects high level
B, be provided with one at the serial input terminal of asynchronous communication controller (2) and have the chip selection signal end, control end, output terminal and two above input ends and they respectively with address decoder (1), data bus (5), the serial input terminal of asynchronous communication controller (2) and level translator (7) link to each other latchs selector switch (4), the said selector switch (4) that latchs is made up of 74LS273 latch integration member and 74LS151 selector switch integration member, connected mode is: the control end (A of optional three ends of 74LS273 latch output terminal (Q to Q) and 74LS151 selector switch, B, C) link to each other, and
C, the said chip selection signal end that latchs gate (3) and latch selector switch (4) is provided by address decoder (1), and their input ends to the data transmission path that forms between the output terminal all can be controlled its break-make by computer instruction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 87100464 CN1010349B (en) | 1987-01-27 | 1987-01-27 | Interface of multichannel asynchronous communication |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 87100464 CN1010349B (en) | 1987-01-27 | 1987-01-27 | Interface of multichannel asynchronous communication |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN87100464A CN87100464A (en) | 1988-08-10 |
| CN1010349B true CN1010349B (en) | 1990-11-07 |
Family
ID=4812885
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 87100464 Expired CN1010349B (en) | 1987-01-27 | 1987-01-27 | Interface of multichannel asynchronous communication |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1010349B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101859291B (en) * | 2010-06-13 | 2011-09-14 | 王新辉 | Multi-singlechip cooperative working method and system |
-
1987
- 1987-01-27 CN CN 87100464 patent/CN1010349B/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| CN87100464A (en) | 1988-08-10 |
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| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C13 | Decision | ||
| GR02 | Examined patent application | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C19 | Lapse of patent right due to non-payment of the annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |