CN213182729U

CN213182729U - Bus extension device based on FPGA chip

Info

Publication number: CN213182729U
Application number: CN202022117974.1U
Authority: CN
Inventors: 周林林; 王凯航; 周好
Original assignee: Shanghai Toupigeon Data Technology Co ltd
Current assignee: Shanghai Toupigeon Data Technology Co ltd
Priority date: 2020-09-24
Filing date: 2020-09-24
Publication date: 2021-05-11
Anticipated expiration: 2030-09-24

Abstract

The bus expansion device based on the FPGA chip is characterized in that a main controller and the FPGA chip are in communication connection through a first SPI bus and an address line respectively; the FPGA chip can also send a first interrupt signal to the main controller through the first interrupt pin; the FPGA chip is in communication connection with the plurality of intelligent card controllers through a plurality of second SPI buses; and the intelligent card controllers respectively send second interrupt signals to the FPGA chip through the second interrupt pins. The utility model discloses promoted the quantity that the SPI bus articulates from the machine by a wide margin under the prerequisite that keeps SPI bus transmission rate, the expansibility is strong.

Description

Bus extension device based on FPGA chip

Technical Field

The utility model belongs to the technical field of the communication technology and specifically relates to a bus extension device based on FPGA chip.

Background

In the field of cloud communication and some industries requiring management of smart cards, a smart card management device is often required; the device needs to acquire and manage information of a large number of smart cards and perform interactive application with a client in real time.

Because of the large number of smart cards, a large number of smart card controllers are required to be directly connected to the smart cards, thereby implementing the operation of the smart cards. High-speed (relative to UART) communication interfaces such as SPI are often used between the host controller and the smart card controller.

The SPI is a four-wire synchronous serial communication interface which is simple to use, high in speed and good in expansibility. The MISO, MOSI, CS and CLK four-wire connection master and slave are used for communication. Because the SPI interface quantity of master controller is all very limited, generally 2~ 3. Further, the frequency characteristics of the data interface may be degraded due to parasitic capacitance of the circuit, interface impedance, and the like. The more slaves that are hooked up to the SPI bus, the larger the parasitic capacitance of the interface. The parasitic capacitance will seriously affect the speed and accuracy of communication. There is therefore a need for an efficient means to extend the SPI bus interface.

In order to solve the problem of signal quality degradation and rate degradation caused by too many slaves in SPI multi-machine communication, some practitioners have already studied, for example, a simple and convenient method for improving the signal driving capability is to use a signal driver to enhance the signal driving capability after the signal output of the master. The effect is very limited.

In addition, another way is to use a multiplexer to transmit signals to the slaves respectively, which has the advantage that a large amount of gates are not needed to expand each signal line, so that the circuit becomes simple; in addition, the CS lines (chip select signals) can be more simplified. However, the multiplexer still has the problems of limited channel number and switching delay. And the standard SPI interface does not have an interrupt pin, so the data communication between the host and all the slaves is realized by the polling of the host.

Disclosure of Invention

The utility model discloses a solve current problem, aim at providing a bus extension device based on the FPGA chip.

In order to achieve the purpose, the technical scheme adopted by the utility model comprises a main controller, an FPGA chip and a plurality of intelligent card controllers, wherein the FPGA chip and the main controller are respectively in communication connection through a first SPI bus and an address line; the FPGA chip is also provided with a first interrupt pin which is electrically connected with the main controller and sends a first interrupt signal to the main controller;

the plurality of intelligent card controllers are in communication connection with the FPGA chip through a plurality of second SPI buses; the plurality of intelligent card controllers are also respectively provided with a second interrupt pin, and the second interrupt pin is electrically connected with the FPGA chip and sends a second interrupt signal to the FPGA chip.

When the main controller is communicated with the intelligent card controller, the address line sends the address information of the intelligent card controller to the FPGA chip, and the FPGA chip establishes communication with the intelligent card controller through the second SPI bus and sends a first interrupt signal to inform the main controller.

When the intelligent card controller is communicated with the main controller, a second interrupt signal is sent to the FPGA chip through a second interrupt pin, and the FPGA chip sends the first interrupt signal and address information to the main controller.

The main controller uses eight GPIO ports as address lines to be connected to eight IO ports of the FPGA chip, namely the eight GPIO ports form eight bits of one byte.

CLK, MISO and MOSI of a first SPI bus of the main controller are connected to three IO ports on the FPGA chip respectively, and a CS line is suspended.

And four lines of the second SPI buses of the plurality of intelligent card managers are respectively connected to four IO ports of the FPGA.

Compared with the prior art, the utility model discloses a set up first, second and break the pin, realized: in the process that the slave computer hopes to communicate with the host computer, after the FPGA identifies the intelligent card controller, before the interruption is initiated to the main controller, the communication link can be established and then the interruption is initiated to the main controller, and after the main controller receives the interruption, the main controller directly initiates the reading operation after acquiring the pin information.

The utility model greatly increases the number of the slave units connected with the SPI bus on the premise of keeping the transmission rate of the SPI bus, and has strong expansibility; the number of discrete circuit elements is reduced, the design integration level of the whole circuit is improved, the integration is easy, the stability is high, and the requirement on the consistency of element parameters is reduced; the utility model solves the problem of high time delay of the multiplexer, and ensures the communication speed of the SPI; the utility model discloses increased the pin of interrupt function on SPI protocol bus, also can realize interrupting mode transmission under the condition of compatible conventional communication mode, can make the resource overhead that the upper application saved the polling, further promote communication efficiency.

Drawings

Fig. 1 is a schematic structural diagram of an embodiment of the present invention;

fig. 2 is a schematic structural diagram of an embodiment of the present invention;

fig. 3 is a schematic diagram of the structure of the multiplexer.

Detailed Description

The present invention will now be further described with reference to the accompanying drawings.

Referring to fig. 3, fig. 3 is a schematic diagram of a multiplexer, which is a prior art scheme for transmitting signals to slaves respectively by using the multiplexer, and has advantages over a direct driver scheme: on one hand, a large number of gate circuits are not needed to expand each signal line, so that the circuit becomes simple; another aspect is that the CS lines (chip select signals) can be more reduced. The multi-channel selector encodes the address signal by BCD code, and when the host adopts 2-line addressing mode, it can control 4 channels (2)

) A slave machine.

Although the use of the multiplexer can improve the negative effects of the direct driver to some extent, it still cannot satisfy the requirements of good applications. Its disadvantages are as follows:

the multiplexer is used as an integrated gate circuit, the 'multi-path' of the multiplexer is limited, namely the number of channels of the multiplexer is limited, and the multiplexer is mostly 8-path or 16-path in practical application. Since SPI has 4 lines, 4 multiplexers are required to mount 8 slaves (16 slave devices can be mounted by a 16-channel selector). It can be seen that the scalability is also limited.

The multiplexer has switching delay, namely delay characteristic, the delay of a high-quality selector on the market is between tens of nanoseconds and tens of milliseconds, generally between tens of milliseconds and tens of milliseconds, so that the communication rate of 18Mbps in the conventional sense cannot be achieved by using the multiplexer for expansion.

The standard SPI interface does not have interrupt pins, so data communication between the master and all slaves must be accomplished by polling of the master. In many applications it is often desirable to use a separate thread to specifically poll the SPI interface to achieve the effect of "real-time" communication.

In order to solve the foregoing problems, the present embodiment provides a bus expansion device based on an FPGA chip, which is not only applicable to a smart card management device, but also applicable to all application scenarios requiring the extension of an SPI bus. And the present embodiment can also be applied to extensions of communication protocols such as UART, IIC, etc., with a small amount of modification without additional inventive work.

Referring to fig. 1 and 2, fig. 1 and 2 show an embodiment of the present invention, which relates to:

1) a main controller: the most core processing unit in the equipment, the host in SPI communication;

2) the FPGA chip is used as a bus expansion module in SPI communication to realize the expansion function of the SPI bus;

3) 128 smart card controllers: slave in SPI communication.

The main controller uses 8 GPIO ports as address lines to be connected to 8 IO ports of the FPGA. 8 GPIO ports of the main controller form 8 bits of a byte, which are defined as ADDR [7:0], and are respectively ADDR7 to ADDR0, and the FPGA chip side is the same.

Referring to fig. 1, SPI interface CLK, MISO, MOSI of master controller are connected to three IO ports on the FPGA chip respectively to define it as M _ CLK, M _ MISO, M _ MOSI respectively, the CS line of master controller is unsettled can, with SPI interface connection to the IO port of FPGA chip of 128 smart card controllers simultaneously, the connected mode is: 4 lines of the SPI interface of each intelligent card manager are respectively connected to 4 IO ports of the FPGA chip.

Referring to fig. 1, assuming that 128 smart card managers are numbered 0-127, the 4 lines connecting the first smart card manager are: s0_ CLK, S0_ MISO, S0_ MOSI, S0_ CS, the 4 lines connecting the second smart card manager are: s1_ CLK, S1_ MISO, S1_ MOSI, S1_ CS. And so on for the rest.

In the present embodiment, if the main controller is to communicate with the smart card controller 0, then:

1) when the SPI bus is idle (no data communication is required), ADDR is in a floating state. When the main controller is to communicate with the intelligent card controller 0, setting ADDR to 0, namely setting GPIO pins of all associated ADDR to low level;

2) after detecting the change of the ADDR, the FPGA chip decodes the address value to be 0, at the moment, CLK, MISO and MOSI are immediately and respectively switched to S0_ CLK, S0_ MISO and S0_ MOSI in the FPGA chip, and then S0_ CS is set to be at a low level;

3) at the moment, a pulse low level (a first interrupt signal) is generated through a first interrupt pin between the FPGA chip and the main controller, so that the main controller is informed that the communication link is established;

4) the main controller is generally high level aiming at a first interrupt pin of the FPGA chip, and can know that the communication link is completely prepared after receiving the pulse low level, and then directly initiates data communication.

If a certain smart card is to communicate with the main controller, then:

because the SPI bus adopts a master-slave communication mode, the slave machine cannot directly send data to the host machine, and the host machine needs to actively fetch the data. In order to avoid SPI polling, the utility model discloses first interrupt pin has been added for the controller. Therefore, when the slave needs to communicate with the master, the following steps are executed:

1) after the smart card controller prepares the data, a low level pulse (second interrupt signal) is generated through a second interrupt pin between the smart card controller and the FPGA chip. After the FPGA chip detects the second interrupt signal and identifies which intelligent card controller sends an interrupt, the address of the FPGA chip is coded to carry out an ADDR register, and then a first interrupt signal is generated to a first interrupt pin of the main controller;

2) because the first interrupt signal is not generated in the process that the main controller actively initiates communication, the main controller needs to read the ADDR register and record the serial number of the intelligent card controller;

3) the main controller executes a communication process according to the serial number of the intelligent card controller, and the steps are the same as the above process;

4) and after the reading is finished, the FPGA chip clears the mark of the first interrupt signal.

The embodiments of the present invention have been described in conjunction with the accompanying drawings and examples, the structures of which are not intended to limit the present invention, and those skilled in the art can make modifications as required, and all changes and modifications within the scope of the appended claims are within the scope of protection.

Claims

1. The utility model provides a bus extension device based on FPGA chip which characterized in that: including main control unit, FPGA chip and a plurality of smart card controller, wherein:

the FPGA chip and the main controller are in communication connection through a first SPI bus and an address line respectively; the FPGA chip is also provided with a first interrupt pin which is electrically connected with the main controller and sends a first interrupt signal to the main controller;

2. The FPGA chip-based bus expansion device of claim 1, wherein: when the main controller is communicated with the intelligent card controller, the address line sends the address information of the intelligent card controller to the FPGA chip, and the FPGA chip establishes communication with the intelligent card controller through the second SPI bus and sends a first interrupt signal to inform the main controller.

3. The FPGA chip-based bus expansion device of claim 1, wherein: when the intelligent card controller is communicated with the main controller, a second interrupt signal is sent to the FPGA chip through a second interrupt pin, and the FPGA chip sends the first interrupt signal and address information to the main controller.

4. The FPGA chip-based bus expansion device of any one of claims 1 to 3, wherein: the main controller uses eight GPIO ports as address lines to be connected to eight IO ports of the FPGA chip, namely the eight GPIO ports form eight bits of one byte.

5. The FPGA chip-based bus expansion device of any one of claims 1 to 3, wherein: CLK, MISO, MOSI of the first SPI bus of main control unit are connected to three IO ports on the FPGA chip respectively, and the CS line is unsettled.

6. The FPGA chip-based bus expansion device of any one of claims 1 to 3, wherein: and four lines of second SPI buses of the plurality of intelligent card managers are respectively connected to four IO ports of the FPGA.