CN101017510B - Method for calculating junction temperature of microelectronics using heat resistance network model - Google Patents

Method for calculating junction temperature of microelectronics using heat resistance network model Download PDF

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CN101017510B
CN101017510B CN2006100342216A CN200610034221A CN101017510B CN 101017510 B CN101017510 B CN 101017510B CN 2006100342216 A CN2006100342216 A CN 2006100342216A CN 200610034221 A CN200610034221 A CN 200610034221A CN 101017510 B CN101017510 B CN 101017510B
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junction temperature
thermal resistance
resistance network
microelectronic component
boundary condition
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邱宝军
蒋明
何小琦
杨邦朝
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China Electronic Product Reliability and Environmental Testing Research Institute
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Abstract

This invention discloses one thermal resistant network module and discloses one method to computer micro electron part by use of thermal resistance network, which comprises the following steps: according to the resistance network module to get unknown parameters temperature expression; processing thermal test to get micro electron part relative temperature data; extracting micro electron part parameters; establishing electron part limit element artificial module; correcting the limit module to ensure limit module accuracy to get effect module for limit artificial data; establishing optimization function to process optimization process to determine the unknown parameters value to get each boundary condition temperature.

Description

A kind of method of utilizing thermal resistance network Model Calculation microelectronic component junction temperature
Technical field
The present invention relates to the thermal reliability technology of microelectronics Packaging, relate in particular to a kind of method of utilizing thermal resistance network Model Calculation microelectronic component junction temperature.
Background technology
For a long time, how to allow the convenient junction temperature of calculating the microelectronic component under the actual working environment of engineering technical personnel be no more than maximum allowable junction temperature to ensure the device chip working temperature, not one effectively, method easily, and, brought difficulty also for thermal design accurately owing to lack the IC standard thermal model.Along with miniaturization day by day, the high assembled density of microelectronics Packaging, make that the microelectronics Packaging heat flow density is increasing, the thermal reliability problem is more and more outstanding.
The general user uses microelectronics Packaging thermal resistance (θ more at present JaOr θ Jc) come the thermal behavior of characterization of microelectronic encapsulation and calculate junction temperature, θ Ja, θ JcAccording to canonical measures such as JEDEC, SEMI, MIL.But, θ JaBe the function of environment, along with the variation of environmental baseline, thermal resistance value changes thereupon, therefore is not suitable for to calculate junction temperature under the complex environment; θ JcBe not subjected to the influence of environment, but only be applicable to the situation that the encapsulation hull-skin temperature all equates.And because the limitation of metering system itself is difficult to the relatively thermal resistance value between the different vendor, data can not be transformed into actual environment from measurement environment, and these have limited θ JaOr θ JcUse in practice.
At traditional microelectronics Packaging thermal resistance (θ JaOr θ Jc) deficiency, European and Japanese scientific research personnel has proposed succinct thermal model (CTM), address this problem preferably to a certain extent, adaptable model has Mahalingam model, Joiner model, Lemzcyk model, Bar-Cohen model, Lasance model.But Mahalingam model, Joiner model and Lemzcyk model can not be independent of boundary condition, because accurately characterization of microelectronic encapsulates thermal behavior, or model is too complicated, uses inconvenience, all can not really be applied to the detection of thermal design and actual working environment.The Bar-Cohen model is only realized the independent edges condition under the isothermal boundary condition, be applied to convection boundary condition, and error surpasses 16%.There is very important systematic error in the Lasance model, and thermal resistance network, modeling method be than Bar-Cohen model complexity, and has bigger randomness; The precision of Lasance model is 90%, and can not provide the formula that embodies of junction temperature.Aforesaid succinct thermal model all adopts a fixing thermal resistance network expression formula to represent the thermal behavior of microelectronics Packaging under isothermal boundary condition and convection boundary condition, model lacks theoretical support, just reduce the error of junction temperature prediction by optimization means, junction temperature predicated error＞10% under the convection heat transfer condition, the restriction that does not fundamentally solve boundary condition, the accurate thermal behavior of standard microelectronics Packaging, and can't be applied to actual environment and be convenient to its device junction temperature of the on-the-spot prediction of engineering technical personnel.
Summary of the invention
At the shortcoming of prior art, the purpose of this invention is to provide a kind of method of utilizing thermal resistance network Model Calculation microelectronic component junction temperature, solve traditional thermal resistance lagging edge circle and change and the deficiency of variation and succinct thermal model junction temperature precision of prediction difference.
To achieve these goals, technical scheme of the present invention is: a kind of method of utilizing thermal resistance network Model Calculation microelectronic component junction temperature, described thermal resistance network model is a star structure, it is made of four nodes of representative end face, side, bottom surface and pin that the knot with the microelectronic component that encapsulates links to each other, each node with the knot between by representing that respectively end face, side, bottom surface and pin link to each other to the branch road thermal resistance of device thermolysis, this method may further comprise the steps:
(1) obtains having the microelectronic component junction temperature expression formula of unknowm coefficient according to described thermal resistance network model; For the isothermal boundary condition, the junction temperature expression formula is T j = Σ k = 1 n A k i T k i + A n + 1 i q ; For convection boundary condition, the junction temperature expression formula is T j = Σ k = 1 n A k c T k c + A n + 1 c q ; Tj is the junction temperature of device in the formula, and Tk is the area weighted mean on the K surface of device, and q is the power consumption of device, and Ak, An+1 are coefficient;
(2) carry out the relevant junction temperature data that the heat test obtains microelectronic component;
(3) extract micro electron part parameters, comprise structural parameters, material parameter and power consumption;
(4) set up electron part limit element artificial module;
(5) with finite element model gained result and the contrast of hot test result, finite element model is revised, guaranteed the correctness of finite element model, obtain effective finite element model;
(6) carry out finite element simulation, obtain emulated data;
(7) set up majorized function, emulated data is optimized processing, thereby determine that the value of unknowm coefficient in the microelectronic component junction temperature expression formula tries to achieve the junction temperature of device under each boundary condition; Described majorized function is Σ k = 1 n ( T j A - T j B ) 2 = min , T in the formula j ABe finite element software emulation gained junction temperature, T j BBe the junction temperature of thermal resistance network Model Calculation gained, adopt the surface respond method to be optimized, determine the coefficient Ak in the junction temperature expression formula under isothermal boundary condition and the convection boundary condition by making min value minimum.
By adopting infrared thermography or electrical measuring method to obtain the relevant junction temperature data of microelectronic component.
Described material parameter is mainly the pyroconductivity of material.
By adopting the common finite element analysis software to set up electron part limit element artificial module.
Described emulated data is by adopting effective finite element model, with microelectronic component in the practical engineering application environment the radiating condition that might run into reduce the typical boundary condition of a cover, carry out computer simulation emulation, obtain the Temperature Distribution of device under multiple boundary condition, and adopt the area weighted mean of each figuratrix of area weighted average method extraction device.
Compared with prior art, the present invention proposes nominal thermal resistance network model under device ground intrinsic thermal resistance network model under the isothermal boundary condition and the convection boundary condition, set up the thermal resistance network model independent edges condition, accurate characterization of microelectronic encapsulation thermal behavior, be used for junction temperature, thermal design evaluation that the actual environment engineering technical personnel predict device.Foundation is used for the hot cell model of integrated thermal design, and final is for setting up IC standard thermal model storehouse.
Description of drawings
The present invention is described in further detail below in conjunction with accompanying drawing.
Fig. 1 is an intrinsic thermal resistance star network synoptic diagram.
Fig. 2 is nominal thermal resistance star network synoptic diagram.
Fig. 3 is the intrinsic thermal resistance network synoptic diagram of concrete example.
Embodiment
See also Fig. 1 and Fig. 2, thermal resistance network of the present invention adopts star structure to represent, four nodes with the representative end face, side, bottom surface and the pin that link to each other with knot constitute, link to each other by the branch road thermal resistance between each node and the knot, each branch road thermal resistance is represented the effect that end face, side, bottom surface and pin dispel the heat to device respectively.The intrinsic thermal resistance network adopts identical structure with nominal thermal resistance network, and the intrinsic thermal resistance network is used for the isothermal boundary condition, and nominal thermal resistance network is used for convection boundary condition.
Be the modeling and the junction temperature computation process of microelectronic component below:
(1) existing thermal resistance definition is improved, propose the thermal resistance network model of microelectronics Packaging.
The present invention is example with the two-dimensional temperature field, the temperature field of two dimension infinitely segmented, because unlimited segmentation, so can adopt the definition of traditional thermal resistance to analyze to the unit of each segmentation.Adopt the circuit principle of similitude at last, proved the essential distinction of packaging thermal resistance under the microelectronics Packaging thermal resistance and concurrent condition under the isothermal boundary condition, proposed characterization of microelectronic respectively and be encapsulated in intrinsic thermal resistance and nominal thermal resistance under isothermal boundary condition and the convection boundary condition.Concrete expression formula is (1).
Figure GA20192014200610034221601D00041
For stable state, linear system, the microelectronics Packaging three-dimensional temperature field can be considered by several two-dimensional temperature fields and is formed by stacking.Consistent with top two-dimensional temperature field thermal resistance expanded definition, the present invention correspondingly expands the definition of three-dimensional temperature field thermal resistance, as the formula (2).Same, the pairing thermal resistance of isothermal boundary condition is the intrinsic thermal resistance, the pairing thermal resistance of convection boundary condition is nominal thermal resistance.
Figure GA20192014200610034221601D00042
According to improving one's methods of top thermal resistance, make θ jc=An+1 propose the junction temperature predictor formula (be the computing formula of thermal resistance network) of microelectronics Packaging under isothermal border and convection boundary condition:
For the isothermal boundary condition, adopt intrinsic thermal resistance network model, the predictor formula of junction temperature is (3)
T j = Σ k = 1 n A k i T k i + A n + 1 i q - - - ( 3 )
In the formula: Tj is that the junction temperature Tk of device is that the surface weighted average temperature q on the K surface of device is that power consumption Ak, the An+1 of device is coefficient.
For convection boundary condition, adopt nominal thermal resistance network model, the predictor formula of junction temperature is (4)
T j = Σ k = 1 n A k c T k c + A n + 1 c q - - - ( 4 )
In the formula: Tj is that the junction temperature Tk of device is that the area weighted mean q on the K surface of device is that power consumption Ak, the An+1 of device is coefficient.
(2) carry out the heat test
Carry out the junction temperature data of heat test acquisition device, can adopt infrared thermography, electrical measuring method etc.
(3) parameter of extraction device comprises structural parameters, material parameter, power consumption, and material parameter is mainly the pyroconductivity of material.
(4) set up the detailed limit element artificial module of device;
Can adopt the common finite element analysis software, as ANSYS etc.
(5) with finite element model gained result and the contrast of hot test result, finite element model is revised, guaranteed the correctness of finite element model, obtain effective finite element model.
(6) carry out finite element simulation, obtain emulated data.
Adopt finite element model through checking, with device in the practical engineering application environment the radiating condition that might run into reduce the typical boundary condition of a cover, 38 kinds of boundary conditions that proposed in the works as DELPHI, carry out computer simulation emulation, obtain the Temperature Distribution of the device under 38 kinds of boundary conditions.Adopt the area weighted mean (Tk) of area weighted average method each figuratrix of extraction device (end face, side, bottom surface and pin).
(7) set up majorized function, emulated data is optimized processing, obtain the junction temperature expression formula with the surface respond method.
The majorized function of selecting for use is
Σ k = 1 n ( T j A - T j B ) 2 = min , - - - ( 5 ) T j ABe finite element software emulation gained junction temperature, T j BJunction temperature for thermal resistance network Model Calculation gained.Adopt surface respond method (RSM) to be optimized, determine the coefficient Ak in the junction temperature calculating formula under isothermal boundary condition and the convection boundary condition by making (5) formula minimum.
(8) determine the thermal resistance network structure,, calculate the branch road thermal resistance of thermal resistance network according to the junction temperature expression formula
Thermal resistance network among the present invention adopts star structure, four nodes with the representative end face, side, bottom surface and the pin that link to each other with knot constitute, each node with the knot between link to each other by the branch road thermal resistance, each branch road thermal resistance is represented the effect to the device heat radiation of end face, side, bottom surface and pin respectively, according to the junction temperature calculating formula, employing formula (6) is calculated each branch road thermal resistance of thermal resistance network.The intrinsic thermal resistance network adopts identical structure with nominal thermal resistance network, and the intrinsic thermal resistance network is used for the isothermal boundary condition, and nominal thermal resistance network is used for convection boundary condition.
R k＝A n+1/A k (6)
(9) the thermal resistance network model is verified.
The present invention adopts finite element model by verification experimental verification junction temperature analog result and the thermal resistance network The model calculation under various boundary to compare and carry out the thermal resistance network verification of model.The junction temperature predicated error that requires the thermal resistance network model is less than 5%.
Seeing also Fig. 2, is that example is set up the succinct thermal model of star-network after the expansion thermal resistance defines with one 28 pin PLCC module.This module profile 11.43 * 11.43 * 3.81mm, 0.66mm is wide for lead-in wire, from the outside 2.66mm of midplane, chip 3.65 * 3.65 * 0.38mm.Lead frame is an aldary, and the mould closure material is an epoxy resin.Use comparatively extensively in the research of the succinct abroad thermal model of this PLCC module, the finite element analogy result of model is by verifications such as Bar-Cohen.
This model is applied 25 kinds of isothermal boundary conditions, adopt the finite element simulation technology, calculate the junction temperature of the device under 25 kinds of isothermal boundary conditions, and adopt the surface respond method to set up the intrinsic thermal resistance network model of device, the concrete computing formula of junction temperature is as follows:
Figure GA20192014200610034221601D00061
Calculate each branch road thermal resistance according to formula (6).
Finite element analogy result under 25 kinds of boundary conditions and thermal resistance network predicted the outcome to be compared, and the precision of prediction of junction temperature reaches 98%, has accurately characterized the device thermal behavior.Utilize the thermal resistance network model of setting up, can determine the junction temperature of the device under any isothermal boundary condition easily.Accelerate thermal design ground process greatly, under actual service conditions, need only each face ground temperature of simple test device, just can accurately predict the working temperature of device, guarantee the thermal reliability of device.The thermal resistance network of setting up not only can be used for the junction temperature of prediction device under the actual environment, also can be used for setting up the hot cell model of integrated thermal design.

Claims (5)

1. method of utilizing thermal resistance network Model Calculation microelectronic component junction temperature, described thermal resistance network model is a star structure, it is made of four nodes of representative end face, side, bottom surface and pin that the knot with the microelectronic component that encapsulates links to each other, each node with the knot between by representing that respectively end face, side, bottom surface and pin link to each other to the branch road thermal resistance of device thermolysis, this method may further comprise the steps:
(1) obtains having the microelectronic component junction temperature expression formula of unknowm coefficient according to described thermal resistance network model; For the isothermal boundary condition, the junction temperature expression formula is
Figure FSB00000104720000011
For convection boundary condition, the junction temperature expression formula is
Figure FSB00000104720000012
T in the formula jBe the junction temperature of device, T kBe the area weighted mean on the K surface of device, q is the power consumption of device, A k, A N+1Be coefficient;
(2) carry out the relevant junction temperature data that the heat test obtains microelectronic component;
(3) extract micro electron part parameters, comprise structural parameters, material parameter and power consumption;
(4) set up electron part limit element artificial module;
(5) with finite element model gained result and the contrast of hot test result, finite element model is revised, guaranteed the correctness of finite element model, obtain effective finite element model;
(6) carry out finite element simulation, obtain emulated data;
(7) set up majorized function, emulated data is optimized processing, thereby determine that the value of unknowm coefficient in the microelectronic component junction temperature expression formula tries to achieve the junction temperature of device under each boundary condition; Described majorized function is
Figure FSB00000104720000013
T in the formula j ABe finite element software emulation gained junction temperature, T j BBe the junction temperature of thermal resistance network Model Calculation gained, adopt the surface respond method to be optimized, determine the coefficient A in the junction temperature expression formula under isothermal boundary condition and the convection boundary condition by making min value minimum k
2. the method for utilizing thermal resistance network Model Calculation microelectronic component junction temperature as claimed in claim 1 is characterized in that, by adopting infrared thermography or electrical measuring method to obtain the relevant junction temperature data of microelectronic component.
3. the method for utilizing thermal resistance network Model Calculation microelectronic component junction temperature as claimed in claim 1 is characterized in that described material parameter is the pyroconductivity of material.
4. the method for utilizing thermal resistance network Model Calculation microelectronic component junction temperature as claimed in claim 1 is characterized in that, by adopting the common finite element analysis software to set up electron part limit element artificial module.
5. the method for utilizing thermal resistance network Model Calculation microelectronic component junction temperature as claimed in claim 1, it is characterized in that, described emulated data is by adopting effective finite element model, with microelectronic component in the practical engineering application environment the radiating condition that might run into reduce the typical boundary condition of a cover, carry out computer simulation emulation, obtain the Temperature Distribution of device under multiple boundary condition, and adopt the area weighted mean of each figuratrix of area weighted average method extraction device.
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